2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/serial_8250.h>
15 #include <linux/platform_device.h>
16 #include <linux/gpio.h>
18 #include <asm/mach/map.h>
20 #include <mach/dm646x.h>
21 #include <mach/clock.h>
22 #include <mach/cputype.h>
23 #include <mach/edma.h>
24 #include <mach/irqs.h>
27 #include <mach/time.h>
28 #include <mach/serial.h>
29 #include <mach/common.h>
36 * Device specific clocks
38 #define DM646X_REF_FREQ 27000000
39 #define DM646X_AUX_FREQ 24000000
41 static struct pll_data pll1_data
= {
43 .phys_base
= DAVINCI_PLL1_BASE
,
46 static struct pll_data pll2_data
= {
48 .phys_base
= DAVINCI_PLL2_BASE
,
51 static struct clk ref_clk
= {
53 .rate
= DM646X_REF_FREQ
,
56 static struct clk aux_clkin
= {
58 .rate
= DM646X_AUX_FREQ
,
61 static struct clk pll1_clk
= {
64 .pll_data
= &pll1_data
,
68 static struct clk pll1_sysclk1
= {
69 .name
= "pll1_sysclk1",
75 static struct clk pll1_sysclk2
= {
76 .name
= "pll1_sysclk2",
82 static struct clk pll1_sysclk3
= {
83 .name
= "pll1_sysclk3",
89 static struct clk pll1_sysclk4
= {
90 .name
= "pll1_sysclk4",
96 static struct clk pll1_sysclk5
= {
97 .name
= "pll1_sysclk5",
103 static struct clk pll1_sysclk6
= {
104 .name
= "pll1_sysclk6",
110 static struct clk pll1_sysclk8
= {
111 .name
= "pll1_sysclk8",
117 static struct clk pll1_sysclk9
= {
118 .name
= "pll1_sysclk9",
124 static struct clk pll1_sysclkbp
= {
125 .name
= "pll1_sysclkbp",
127 .flags
= CLK_PLL
| PRE_PLL
,
131 static struct clk pll1_aux_clk
= {
132 .name
= "pll1_aux_clk",
134 .flags
= CLK_PLL
| PRE_PLL
,
137 static struct clk pll2_clk
= {
140 .pll_data
= &pll2_data
,
144 static struct clk pll2_sysclk1
= {
145 .name
= "pll2_sysclk1",
151 static struct clk dsp_clk
= {
153 .parent
= &pll1_sysclk1
,
154 .lpsc
= DM646X_LPSC_C64X_CPU
,
156 .usecount
= 1, /* REVISIT how to disable? */
159 static struct clk arm_clk
= {
161 .parent
= &pll1_sysclk2
,
162 .lpsc
= DM646X_LPSC_ARM
,
163 .flags
= ALWAYS_ENABLED
,
166 static struct clk edma_cc_clk
= {
168 .parent
= &pll1_sysclk2
,
169 .lpsc
= DM646X_LPSC_TPCC
,
170 .flags
= ALWAYS_ENABLED
,
173 static struct clk edma_tc0_clk
= {
175 .parent
= &pll1_sysclk2
,
176 .lpsc
= DM646X_LPSC_TPTC0
,
177 .flags
= ALWAYS_ENABLED
,
180 static struct clk edma_tc1_clk
= {
182 .parent
= &pll1_sysclk2
,
183 .lpsc
= DM646X_LPSC_TPTC1
,
184 .flags
= ALWAYS_ENABLED
,
187 static struct clk edma_tc2_clk
= {
189 .parent
= &pll1_sysclk2
,
190 .lpsc
= DM646X_LPSC_TPTC2
,
191 .flags
= ALWAYS_ENABLED
,
194 static struct clk edma_tc3_clk
= {
196 .parent
= &pll1_sysclk2
,
197 .lpsc
= DM646X_LPSC_TPTC3
,
198 .flags
= ALWAYS_ENABLED
,
201 static struct clk uart0_clk
= {
203 .parent
= &aux_clkin
,
204 .lpsc
= DM646X_LPSC_UART0
,
207 static struct clk uart1_clk
= {
209 .parent
= &aux_clkin
,
210 .lpsc
= DM646X_LPSC_UART1
,
213 static struct clk uart2_clk
= {
215 .parent
= &aux_clkin
,
216 .lpsc
= DM646X_LPSC_UART2
,
219 static struct clk i2c_clk
= {
221 .parent
= &pll1_sysclk3
,
222 .lpsc
= DM646X_LPSC_I2C
,
225 static struct clk gpio_clk
= {
227 .parent
= &pll1_sysclk3
,
228 .lpsc
= DM646X_LPSC_GPIO
,
231 static struct clk mcasp0_clk
= {
233 .parent
= &pll1_sysclk3
,
234 .lpsc
= DM646X_LPSC_McASP0
,
237 static struct clk mcasp1_clk
= {
239 .parent
= &pll1_sysclk3
,
240 .lpsc
= DM646X_LPSC_McASP1
,
243 static struct clk aemif_clk
= {
245 .parent
= &pll1_sysclk3
,
246 .lpsc
= DM646X_LPSC_AEMIF
,
247 .flags
= ALWAYS_ENABLED
,
250 static struct clk emac_clk
= {
252 .parent
= &pll1_sysclk3
,
253 .lpsc
= DM646X_LPSC_EMAC
,
256 static struct clk pwm0_clk
= {
258 .parent
= &pll1_sysclk3
,
259 .lpsc
= DM646X_LPSC_PWM0
,
260 .usecount
= 1, /* REVIST: disabling hangs system */
263 static struct clk pwm1_clk
= {
265 .parent
= &pll1_sysclk3
,
266 .lpsc
= DM646X_LPSC_PWM1
,
267 .usecount
= 1, /* REVIST: disabling hangs system */
270 static struct clk timer0_clk
= {
272 .parent
= &pll1_sysclk3
,
273 .lpsc
= DM646X_LPSC_TIMER0
,
276 static struct clk timer1_clk
= {
278 .parent
= &pll1_sysclk3
,
279 .lpsc
= DM646X_LPSC_TIMER1
,
282 static struct clk timer2_clk
= {
284 .parent
= &pll1_sysclk3
,
285 .flags
= ALWAYS_ENABLED
, /* no LPSC, always enabled; c.f. spruep9a */
288 static struct clk vpif0_clk
= {
291 .lpsc
= DM646X_LPSC_VPSSMSTR
,
292 .flags
= ALWAYS_ENABLED
,
295 static struct clk vpif1_clk
= {
298 .lpsc
= DM646X_LPSC_VPSSSLV
,
299 .flags
= ALWAYS_ENABLED
,
302 struct davinci_clk dm646x_clks
[] = {
303 CLK(NULL
, "ref", &ref_clk
),
304 CLK(NULL
, "aux", &aux_clkin
),
305 CLK(NULL
, "pll1", &pll1_clk
),
306 CLK(NULL
, "pll1_sysclk", &pll1_sysclk1
),
307 CLK(NULL
, "pll1_sysclk", &pll1_sysclk2
),
308 CLK(NULL
, "pll1_sysclk", &pll1_sysclk3
),
309 CLK(NULL
, "pll1_sysclk", &pll1_sysclk4
),
310 CLK(NULL
, "pll1_sysclk", &pll1_sysclk5
),
311 CLK(NULL
, "pll1_sysclk", &pll1_sysclk6
),
312 CLK(NULL
, "pll1_sysclk", &pll1_sysclk8
),
313 CLK(NULL
, "pll1_sysclk", &pll1_sysclk9
),
314 CLK(NULL
, "pll1_sysclk", &pll1_sysclkbp
),
315 CLK(NULL
, "pll1_aux", &pll1_aux_clk
),
316 CLK(NULL
, "pll2", &pll2_clk
),
317 CLK(NULL
, "pll2_sysclk1", &pll2_sysclk1
),
318 CLK(NULL
, "dsp", &dsp_clk
),
319 CLK(NULL
, "arm", &arm_clk
),
320 CLK(NULL
, "edma_cc", &edma_cc_clk
),
321 CLK(NULL
, "edma_tc0", &edma_tc0_clk
),
322 CLK(NULL
, "edma_tc1", &edma_tc1_clk
),
323 CLK(NULL
, "edma_tc2", &edma_tc2_clk
),
324 CLK(NULL
, "edma_tc3", &edma_tc3_clk
),
325 CLK(NULL
, "uart0", &uart0_clk
),
326 CLK(NULL
, "uart1", &uart1_clk
),
327 CLK(NULL
, "uart2", &uart2_clk
),
328 CLK("i2c_davinci.1", NULL
, &i2c_clk
),
329 CLK(NULL
, "gpio", &gpio_clk
),
330 CLK(NULL
, "mcasp0", &mcasp0_clk
),
331 CLK(NULL
, "mcasp1", &mcasp1_clk
),
332 CLK(NULL
, "aemif", &aemif_clk
),
333 CLK("davinci_emac.1", NULL
, &emac_clk
),
334 CLK(NULL
, "pwm0", &pwm0_clk
),
335 CLK(NULL
, "pwm1", &pwm1_clk
),
336 CLK(NULL
, "timer0", &timer0_clk
),
337 CLK(NULL
, "timer1", &timer1_clk
),
338 CLK("watchdog", NULL
, &timer2_clk
),
339 CLK(NULL
, "vpif0", &vpif0_clk
),
340 CLK(NULL
, "vpif1", &vpif1_clk
),
341 CLK(NULL
, NULL
, NULL
),
344 static struct emac_platform_data dm646x_emac_pdata
= {
345 .ctrl_reg_offset
= DM646X_EMAC_CNTRL_OFFSET
,
346 .ctrl_mod_reg_offset
= DM646X_EMAC_CNTRL_MOD_OFFSET
,
347 .ctrl_ram_offset
= DM646X_EMAC_CNTRL_RAM_OFFSET
,
348 .mdio_reg_offset
= DM646X_EMAC_MDIO_OFFSET
,
349 .ctrl_ram_size
= DM646X_EMAC_CNTRL_RAM_SIZE
,
350 .version
= EMAC_VERSION_2
,
353 static struct resource dm646x_emac_resources
[] = {
355 .start
= DM646X_EMAC_BASE
,
356 .end
= DM646X_EMAC_BASE
+ 0x47ff,
357 .flags
= IORESOURCE_MEM
,
360 .start
= IRQ_DM646X_EMACRXTHINT
,
361 .end
= IRQ_DM646X_EMACRXTHINT
,
362 .flags
= IORESOURCE_IRQ
,
365 .start
= IRQ_DM646X_EMACRXINT
,
366 .end
= IRQ_DM646X_EMACRXINT
,
367 .flags
= IORESOURCE_IRQ
,
370 .start
= IRQ_DM646X_EMACTXINT
,
371 .end
= IRQ_DM646X_EMACTXINT
,
372 .flags
= IORESOURCE_IRQ
,
375 .start
= IRQ_DM646X_EMACMISCINT
,
376 .end
= IRQ_DM646X_EMACMISCINT
,
377 .flags
= IORESOURCE_IRQ
,
381 static struct platform_device dm646x_emac_device
= {
382 .name
= "davinci_emac",
385 .platform_data
= &dm646x_emac_pdata
,
387 .num_resources
= ARRAY_SIZE(dm646x_emac_resources
),
388 .resource
= dm646x_emac_resources
,
395 * Device specific mux setup
397 * soc description mux mode mode mux dbg
398 * reg offset mask mode
400 static const struct mux_config dm646x_pins
[] = {
401 #ifdef CONFIG_DAVINCI_MUX
402 MUX_CFG(DM646X
, ATAEN
, 0, 0, 1, 1, true)
404 MUX_CFG(DM646X
, AUDCK1
, 0, 29, 1, 0, false)
406 MUX_CFG(DM646X
, AUDCK0
, 0, 28, 1, 0, false)
408 MUX_CFG(DM646X
, CRGMUX
, 0, 24, 7, 5, true)
410 MUX_CFG(DM646X
, STSOMUX_DISABLE
, 0, 22, 3, 0, true)
412 MUX_CFG(DM646X
, STSIMUX_DISABLE
, 0, 20, 3, 0, true)
414 MUX_CFG(DM646X
, PTSOMUX_DISABLE
, 0, 18, 3, 0, true)
416 MUX_CFG(DM646X
, PTSIMUX_DISABLE
, 0, 16, 3, 0, true)
418 MUX_CFG(DM646X
, STSOMUX
, 0, 22, 3, 2, true)
420 MUX_CFG(DM646X
, STSIMUX
, 0, 20, 3, 2, true)
422 MUX_CFG(DM646X
, PTSOMUX_PARALLEL
, 0, 18, 3, 2, true)
424 MUX_CFG(DM646X
, PTSIMUX_PARALLEL
, 0, 16, 3, 2, true)
426 MUX_CFG(DM646X
, PTSOMUX_SERIAL
, 0, 18, 3, 3, true)
428 MUX_CFG(DM646X
, PTSIMUX_SERIAL
, 0, 16, 3, 3, true)
432 static u8 dm646x_default_priorities
[DAVINCI_N_AINTC_IRQ
] = {
433 [IRQ_DM646X_VP_VERTINT0
] = 7,
434 [IRQ_DM646X_VP_VERTINT1
] = 7,
435 [IRQ_DM646X_VP_VERTINT2
] = 7,
436 [IRQ_DM646X_VP_VERTINT3
] = 7,
437 [IRQ_DM646X_VP_ERRINT
] = 7,
438 [IRQ_DM646X_RESERVED_1
] = 7,
439 [IRQ_DM646X_RESERVED_2
] = 7,
440 [IRQ_DM646X_WDINT
] = 7,
441 [IRQ_DM646X_CRGENINT0
] = 7,
442 [IRQ_DM646X_CRGENINT1
] = 7,
443 [IRQ_DM646X_TSIFINT0
] = 7,
444 [IRQ_DM646X_TSIFINT1
] = 7,
445 [IRQ_DM646X_VDCEINT
] = 7,
446 [IRQ_DM646X_USBINT
] = 7,
447 [IRQ_DM646X_USBDMAINT
] = 7,
448 [IRQ_DM646X_PCIINT
] = 7,
449 [IRQ_CCINT0
] = 7, /* dma */
450 [IRQ_CCERRINT
] = 7, /* dma */
451 [IRQ_TCERRINT0
] = 7, /* dma */
452 [IRQ_TCERRINT
] = 7, /* dma */
453 [IRQ_DM646X_TCERRINT2
] = 7,
454 [IRQ_DM646X_TCERRINT3
] = 7,
455 [IRQ_DM646X_IDE
] = 7,
456 [IRQ_DM646X_HPIINT
] = 7,
457 [IRQ_DM646X_EMACRXTHINT
] = 7,
458 [IRQ_DM646X_EMACRXINT
] = 7,
459 [IRQ_DM646X_EMACTXINT
] = 7,
460 [IRQ_DM646X_EMACMISCINT
] = 7,
461 [IRQ_DM646X_MCASP0TXINT
] = 7,
462 [IRQ_DM646X_MCASP0RXINT
] = 7,
464 [IRQ_DM646X_RESERVED_3
] = 7,
465 [IRQ_DM646X_MCASP1TXINT
] = 7, /* clockevent */
466 [IRQ_TINT0_TINT34
] = 7, /* clocksource */
467 [IRQ_TINT1_TINT12
] = 7, /* DSP timer */
468 [IRQ_TINT1_TINT34
] = 7, /* system tick */
471 [IRQ_DM646X_VLQINT
] = 7,
475 [IRQ_DM646X_UARTINT2
] = 7,
476 [IRQ_DM646X_SPINT0
] = 7,
477 [IRQ_DM646X_SPINT1
] = 7,
478 [IRQ_DM646X_DSP2ARMINT
] = 7,
479 [IRQ_DM646X_RESERVED_4
] = 7,
480 [IRQ_DM646X_PSCINT
] = 7,
481 [IRQ_DM646X_GPIO0
] = 7,
482 [IRQ_DM646X_GPIO1
] = 7,
483 [IRQ_DM646X_GPIO2
] = 7,
484 [IRQ_DM646X_GPIO3
] = 7,
485 [IRQ_DM646X_GPIO4
] = 7,
486 [IRQ_DM646X_GPIO5
] = 7,
487 [IRQ_DM646X_GPIO6
] = 7,
488 [IRQ_DM646X_GPIO7
] = 7,
489 [IRQ_DM646X_GPIOBNK0
] = 7,
490 [IRQ_DM646X_GPIOBNK1
] = 7,
491 [IRQ_DM646X_GPIOBNK2
] = 7,
492 [IRQ_DM646X_DDRINT
] = 7,
493 [IRQ_DM646X_AEMIFINT
] = 7,
499 /*----------------------------------------------------------------------*/
501 static const s8 dma_chan_dm646x_no_event
[] = {
509 /* Four Transfer Controllers on DM646x */
511 dm646x_queue_tc_mapping
[][2] = {
512 /* {event queue no, TC no} */
521 dm646x_queue_priority_mapping
[][2] = {
522 /* {event queue no, Priority} */
530 static struct edma_soc_info dm646x_edma_info
[] = {
533 .n_region
= 6, /* 0-1, 4-7 */
537 .noevent
= dma_chan_dm646x_no_event
,
538 .queue_tc_mapping
= dm646x_queue_tc_mapping
,
539 .queue_priority_mapping
= dm646x_queue_priority_mapping
,
543 static struct resource edma_resources
[] = {
547 .end
= 0x01c00000 + SZ_64K
- 1,
548 .flags
= IORESOURCE_MEM
,
553 .end
= 0x01c10000 + SZ_1K
- 1,
554 .flags
= IORESOURCE_MEM
,
559 .end
= 0x01c10400 + SZ_1K
- 1,
560 .flags
= IORESOURCE_MEM
,
565 .end
= 0x01c10800 + SZ_1K
- 1,
566 .flags
= IORESOURCE_MEM
,
571 .end
= 0x01c10c00 + SZ_1K
- 1,
572 .flags
= IORESOURCE_MEM
,
577 .flags
= IORESOURCE_IRQ
,
581 .start
= IRQ_CCERRINT
,
582 .flags
= IORESOURCE_IRQ
,
584 /* not using TC*_ERR */
587 static struct platform_device dm646x_edma_device
= {
590 .dev
.platform_data
= dm646x_edma_info
,
591 .num_resources
= ARRAY_SIZE(edma_resources
),
592 .resource
= edma_resources
,
595 static struct resource dm646x_mcasp0_resources
[] = {
598 .start
= DAVINCI_DM646X_MCASP0_REG_BASE
,
599 .end
= DAVINCI_DM646X_MCASP0_REG_BASE
+ (SZ_1K
<< 1) - 1,
600 .flags
= IORESOURCE_MEM
,
602 /* first TX, then RX */
604 .start
= DAVINCI_DM646X_DMA_MCASP0_AXEVT0
,
605 .end
= DAVINCI_DM646X_DMA_MCASP0_AXEVT0
,
606 .flags
= IORESOURCE_DMA
,
609 .start
= DAVINCI_DM646X_DMA_MCASP0_AREVT0
,
610 .end
= DAVINCI_DM646X_DMA_MCASP0_AREVT0
,
611 .flags
= IORESOURCE_DMA
,
615 static struct resource dm646x_mcasp1_resources
[] = {
618 .start
= DAVINCI_DM646X_MCASP1_REG_BASE
,
619 .end
= DAVINCI_DM646X_MCASP1_REG_BASE
+ (SZ_1K
<< 1) - 1,
620 .flags
= IORESOURCE_MEM
,
622 /* DIT mode, only TX event */
624 .start
= DAVINCI_DM646X_DMA_MCASP1_AXEVT1
,
625 .end
= DAVINCI_DM646X_DMA_MCASP1_AXEVT1
,
626 .flags
= IORESOURCE_DMA
,
628 /* DIT mode, dummy entry */
632 .flags
= IORESOURCE_DMA
,
636 static struct platform_device dm646x_mcasp0_device
= {
637 .name
= "davinci-mcasp",
639 .num_resources
= ARRAY_SIZE(dm646x_mcasp0_resources
),
640 .resource
= dm646x_mcasp0_resources
,
643 static struct platform_device dm646x_mcasp1_device
= {
644 .name
= "davinci-mcasp",
646 .num_resources
= ARRAY_SIZE(dm646x_mcasp1_resources
),
647 .resource
= dm646x_mcasp1_resources
,
650 static struct platform_device dm646x_dit_device
= {
655 /*----------------------------------------------------------------------*/
657 static struct map_desc dm646x_io_desc
[] = {
660 .pfn
= __phys_to_pfn(IO_PHYS
),
665 .virtual = SRAM_VIRT
,
666 .pfn
= __phys_to_pfn(0x00010000),
668 /* MT_MEMORY_NONCACHED requires supersection alignment */
673 /* Contents of JTAG ID register used to identify exact cpu type */
674 static struct davinci_id dm646x_ids
[] = {
678 .manufacturer
= 0x017,
679 .cpu_id
= DAVINCI_CPU_ID_DM6467
,
684 static void __iomem
*dm646x_psc_bases
[] = {
685 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE
),
689 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
690 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
691 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
692 * T1_TOP: Timer 1, top : <unused>
694 struct davinci_timer_info dm646x_timer_info
= {
695 .timers
= davinci_timer_instance
,
696 .clockevent_id
= T0_BOT
,
697 .clocksource_id
= T0_TOP
,
700 static struct plat_serial8250_port dm646x_serial_platform_data
[] = {
702 .mapbase
= DAVINCI_UART0_BASE
,
704 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
706 .iotype
= UPIO_MEM32
,
710 .mapbase
= DAVINCI_UART1_BASE
,
712 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
714 .iotype
= UPIO_MEM32
,
718 .mapbase
= DAVINCI_UART2_BASE
,
719 .irq
= IRQ_DM646X_UARTINT2
,
720 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
722 .iotype
= UPIO_MEM32
,
730 static struct platform_device dm646x_serial_device
= {
731 .name
= "serial8250",
732 .id
= PLAT8250_DEV_PLATFORM
,
734 .platform_data
= dm646x_serial_platform_data
,
738 static struct davinci_soc_info davinci_soc_info_dm646x
= {
739 .io_desc
= dm646x_io_desc
,
740 .io_desc_num
= ARRAY_SIZE(dm646x_io_desc
),
741 .jtag_id_base
= IO_ADDRESS(0x01c40028),
743 .ids_num
= ARRAY_SIZE(dm646x_ids
),
744 .cpu_clks
= dm646x_clks
,
745 .psc_bases
= dm646x_psc_bases
,
746 .psc_bases_num
= ARRAY_SIZE(dm646x_psc_bases
),
747 .pinmux_base
= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE
),
748 .pinmux_pins
= dm646x_pins
,
749 .pinmux_pins_num
= ARRAY_SIZE(dm646x_pins
),
750 .intc_base
= IO_ADDRESS(DAVINCI_ARM_INTC_BASE
),
751 .intc_type
= DAVINCI_INTC_TYPE_AINTC
,
752 .intc_irq_prios
= dm646x_default_priorities
,
753 .intc_irq_num
= DAVINCI_N_AINTC_IRQ
,
754 .timer_info
= &dm646x_timer_info
,
755 .gpio_base
= IO_ADDRESS(DAVINCI_GPIO_BASE
),
756 .gpio_num
= 43, /* Only 33 usable */
757 .gpio_irq
= IRQ_DM646X_GPIOBNK0
,
758 .serial_dev
= &dm646x_serial_device
,
759 .emac_pdata
= &dm646x_emac_pdata
,
760 .sram_dma
= 0x10010000,
764 void __init
dm646x_init_mcasp0(struct snd_platform_data
*pdata
)
766 dm646x_mcasp0_device
.dev
.platform_data
= pdata
;
767 platform_device_register(&dm646x_mcasp0_device
);
770 void __init
dm646x_init_mcasp1(struct snd_platform_data
*pdata
)
772 dm646x_mcasp1_device
.dev
.platform_data
= pdata
;
773 platform_device_register(&dm646x_mcasp1_device
);
774 platform_device_register(&dm646x_dit_device
);
777 void __init
dm646x_init(void)
779 davinci_common_init(&davinci_soc_info_dm646x
);
782 static int __init
dm646x_init_devices(void)
784 if (!cpu_is_davinci_dm646x())
787 platform_device_register(&dm646x_edma_device
);
788 platform_device_register(&dm646x_emac_device
);
791 postcore_initcall(dm646x_init_devices
);