arch/arm/mach-davinci/dm646x.c

   1 /*
   2  * TI DaVinci DM644x chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/serial_8250.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/gpio.h>
  17
  18 #include <asm/mach/map.h>
  19
  20 #include <mach/dm646x.h>
  21 #include <mach/clock.h>
  22 #include <mach/cputype.h>
  23 #include <mach/edma.h>
  24 #include <mach/irqs.h>
  25 #include <mach/psc.h>
  26 #include <mach/mux.h>
  27 #include <mach/time.h>
  28 #include <mach/serial.h>
  29 #include <mach/common.h>
  30 #include <mach/asp.h>
  31
  32 #include "clock.h"
  33 #include "mux.h"
  34
  35 /*
  36  * Device specific clocks
  37  */
  38 #define DM646X_REF_FREQ         27000000
  39 #define DM646X_AUX_FREQ         24000000
  40
  41 static struct pll_data pll1_data = {
  42         .num       = 1,
  43         .phys_base = DAVINCI_PLL1_BASE,
  44 };
  45
  46 static struct pll_data pll2_data = {
  47         .num       = 2,
  48         .phys_base = DAVINCI_PLL2_BASE,
  49 };
  50
  51 static struct clk ref_clk = {
  52         .name = "ref_clk",
  53         .rate = DM646X_REF_FREQ,
  54 };
  55
  56 static struct clk aux_clkin = {
  57         .name = "aux_clkin",
  58         .rate = DM646X_AUX_FREQ,
  59 };
  60
  61 static struct clk pll1_clk = {
  62         .name = "pll1",
  63         .parent = &ref_clk,
  64         .pll_data = &pll1_data,
  65         .flags = CLK_PLL,
  66 };
  67
  68 static struct clk pll1_sysclk1 = {
  69         .name = "pll1_sysclk1",
  70         .parent = &pll1_clk,
  71         .flags = CLK_PLL,
  72         .div_reg = PLLDIV1,
  73 };
  74
  75 static struct clk pll1_sysclk2 = {
  76         .name = "pll1_sysclk2",
  77         .parent = &pll1_clk,
  78         .flags = CLK_PLL,
  79         .div_reg = PLLDIV2,
  80 };
  81
  82 static struct clk pll1_sysclk3 = {
  83         .name = "pll1_sysclk3",
  84         .parent = &pll1_clk,
  85         .flags = CLK_PLL,
  86         .div_reg = PLLDIV3,
  87 };
  88
  89 static struct clk pll1_sysclk4 = {
  90         .name = "pll1_sysclk4",
  91         .parent = &pll1_clk,
  92         .flags = CLK_PLL,
  93         .div_reg = PLLDIV4,
  94 };
  95
  96 static struct clk pll1_sysclk5 = {
  97         .name = "pll1_sysclk5",
  98         .parent = &pll1_clk,
  99         .flags = CLK_PLL,
 100         .div_reg = PLLDIV5,
 101 };
 102
 103 static struct clk pll1_sysclk6 = {
 104         .name = "pll1_sysclk6",
 105         .parent = &pll1_clk,
 106         .flags = CLK_PLL,
 107         .div_reg = PLLDIV6,
 108 };
 109
 110 static struct clk pll1_sysclk8 = {
 111         .name = "pll1_sysclk8",
 112         .parent = &pll1_clk,
 113         .flags = CLK_PLL,
 114         .div_reg = PLLDIV8,
 115 };
 116
 117 static struct clk pll1_sysclk9 = {
 118         .name = "pll1_sysclk9",
 119         .parent = &pll1_clk,
 120         .flags = CLK_PLL,
 121         .div_reg = PLLDIV9,
 122 };
 123
 124 static struct clk pll1_sysclkbp = {
 125         .name = "pll1_sysclkbp",
 126         .parent = &pll1_clk,
 127         .flags = CLK_PLL | PRE_PLL,
 128         .div_reg = BPDIV,
 129 };
 130
 131 static struct clk pll1_aux_clk = {
 132         .name = "pll1_aux_clk",
 133         .parent = &pll1_clk,
 134         .flags = CLK_PLL | PRE_PLL,
 135 };
 136
 137 static struct clk pll2_clk = {
 138         .name = "pll2_clk",
 139         .parent = &ref_clk,
 140         .pll_data = &pll2_data,
 141         .flags = CLK_PLL,
 142 };
 143
 144 static struct clk pll2_sysclk1 = {
 145         .name = "pll2_sysclk1",
 146         .parent = &pll2_clk,
 147         .flags = CLK_PLL,
 148         .div_reg = PLLDIV1,
 149 };
 150
 151 static struct clk dsp_clk = {
 152         .name = "dsp",
 153         .parent = &pll1_sysclk1,
 154         .lpsc = DM646X_LPSC_C64X_CPU,
 155         .flags = PSC_DSP,
 156         .usecount = 1,                  /* REVISIT how to disable? */
 157 };
 158
 159 static struct clk arm_clk = {
 160         .name = "arm",
 161         .parent = &pll1_sysclk2,
 162         .lpsc = DM646X_LPSC_ARM,
 163         .flags = ALWAYS_ENABLED,
 164 };
 165
 166 static struct clk edma_cc_clk = {
 167         .name = "edma_cc",
 168         .parent = &pll1_sysclk2,
 169         .lpsc = DM646X_LPSC_TPCC,
 170         .flags = ALWAYS_ENABLED,
 171 };
 172
 173 static struct clk edma_tc0_clk = {
 174         .name = "edma_tc0",
 175         .parent = &pll1_sysclk2,
 176         .lpsc = DM646X_LPSC_TPTC0,
 177         .flags = ALWAYS_ENABLED,
 178 };
 179
 180 static struct clk edma_tc1_clk = {
 181         .name = "edma_tc1",
 182         .parent = &pll1_sysclk2,
 183         .lpsc = DM646X_LPSC_TPTC1,
 184         .flags = ALWAYS_ENABLED,
 185 };
 186
 187 static struct clk edma_tc2_clk = {
 188         .name = "edma_tc2",
 189         .parent = &pll1_sysclk2,
 190         .lpsc = DM646X_LPSC_TPTC2,
 191         .flags = ALWAYS_ENABLED,
 192 };
 193
 194 static struct clk edma_tc3_clk = {
 195         .name = "edma_tc3",
 196         .parent = &pll1_sysclk2,
 197         .lpsc = DM646X_LPSC_TPTC3,
 198         .flags = ALWAYS_ENABLED,
 199 };
 200
 201 static struct clk uart0_clk = {
 202         .name = "uart0",
 203         .parent = &aux_clkin,
 204         .lpsc = DM646X_LPSC_UART0,
 205 };
 206
 207 static struct clk uart1_clk = {
 208         .name = "uart1",
 209         .parent = &aux_clkin,
 210         .lpsc = DM646X_LPSC_UART1,
 211 };
 212
 213 static struct clk uart2_clk = {
 214         .name = "uart2",
 215         .parent = &aux_clkin,
 216         .lpsc = DM646X_LPSC_UART2,
 217 };
 218
 219 static struct clk i2c_clk = {
 220         .name = "I2CCLK",
 221         .parent = &pll1_sysclk3,
 222         .lpsc = DM646X_LPSC_I2C,
 223 };
 224
 225 static struct clk gpio_clk = {
 226         .name = "gpio",
 227         .parent = &pll1_sysclk3,
 228         .lpsc = DM646X_LPSC_GPIO,
 229 };
 230
 231 static struct clk mcasp0_clk = {
 232         .name = "mcasp0",
 233         .parent = &pll1_sysclk3,
 234         .lpsc = DM646X_LPSC_McASP0,
 235 };
 236
 237 static struct clk mcasp1_clk = {
 238         .name = "mcasp1",
 239         .parent = &pll1_sysclk3,
 240         .lpsc = DM646X_LPSC_McASP1,
 241 };
 242
 243 static struct clk aemif_clk = {
 244         .name = "aemif",
 245         .parent = &pll1_sysclk3,
 246         .lpsc = DM646X_LPSC_AEMIF,
 247         .flags = ALWAYS_ENABLED,
 248 };
 249
 250 static struct clk emac_clk = {
 251         .name = "emac",
 252         .parent = &pll1_sysclk3,
 253         .lpsc = DM646X_LPSC_EMAC,
 254 };
 255
 256 static struct clk pwm0_clk = {
 257         .name = "pwm0",
 258         .parent = &pll1_sysclk3,
 259         .lpsc = DM646X_LPSC_PWM0,
 260         .usecount = 1,            /* REVIST: disabling hangs system */
 261 };
 262
 263 static struct clk pwm1_clk = {
 264         .name = "pwm1",
 265         .parent = &pll1_sysclk3,
 266         .lpsc = DM646X_LPSC_PWM1,
 267         .usecount = 1,            /* REVIST: disabling hangs system */
 268 };
 269
 270 static struct clk timer0_clk = {
 271         .name = "timer0",
 272         .parent = &pll1_sysclk3,
 273         .lpsc = DM646X_LPSC_TIMER0,
 274 };
 275
 276 static struct clk timer1_clk = {
 277         .name = "timer1",
 278         .parent = &pll1_sysclk3,
 279         .lpsc = DM646X_LPSC_TIMER1,
 280 };
 281
 282 static struct clk timer2_clk = {
 283         .name = "timer2",
 284         .parent = &pll1_sysclk3,
 285         .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
 286 };
 287
 288 static struct clk vpif0_clk = {
 289         .name = "vpif0",
 290         .parent = &ref_clk,
 291         .lpsc = DM646X_LPSC_VPSSMSTR,
 292         .flags = ALWAYS_ENABLED,
 293 };
 294
 295 static struct clk vpif1_clk = {
 296         .name = "vpif1",
 297         .parent = &ref_clk,
 298         .lpsc = DM646X_LPSC_VPSSSLV,
 299         .flags = ALWAYS_ENABLED,
 300 };
 301
 302 struct davinci_clk dm646x_clks[] = {
 303         CLK(NULL, "ref", &ref_clk),
 304         CLK(NULL, "aux", &aux_clkin),
 305         CLK(NULL, "pll1", &pll1_clk),
 306         CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
 307         CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
 308         CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
 309         CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
 310         CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
 311         CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
 312         CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
 313         CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
 314         CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
 315         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 316         CLK(NULL, "pll2", &pll2_clk),
 317         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 318         CLK(NULL, "dsp", &dsp_clk),
 319         CLK(NULL, "arm", &arm_clk),
 320         CLK(NULL, "edma_cc", &edma_cc_clk),
 321         CLK(NULL, "edma_tc0", &edma_tc0_clk),
 322         CLK(NULL, "edma_tc1", &edma_tc1_clk),
 323         CLK(NULL, "edma_tc2", &edma_tc2_clk),
 324         CLK(NULL, "edma_tc3", &edma_tc3_clk),
 325         CLK(NULL, "uart0", &uart0_clk),
 326         CLK(NULL, "uart1", &uart1_clk),
 327         CLK(NULL, "uart2", &uart2_clk),
 328         CLK("i2c_davinci.1", NULL, &i2c_clk),
 329         CLK(NULL, "gpio", &gpio_clk),
 330         CLK(NULL, "mcasp0", &mcasp0_clk),
 331         CLK(NULL, "mcasp1", &mcasp1_clk),
 332         CLK(NULL, "aemif", &aemif_clk),
 333         CLK("davinci_emac.1", NULL, &emac_clk),
 334         CLK(NULL, "pwm0", &pwm0_clk),
 335         CLK(NULL, "pwm1", &pwm1_clk),
 336         CLK(NULL, "timer0", &timer0_clk),
 337         CLK(NULL, "timer1", &timer1_clk),
 338         CLK("watchdog", NULL, &timer2_clk),
 339         CLK(NULL, "vpif0", &vpif0_clk),
 340         CLK(NULL, "vpif1", &vpif1_clk),
 341         CLK(NULL, NULL, NULL),
 342 };
 343
 344 static struct emac_platform_data dm646x_emac_pdata = {
 345         .ctrl_reg_offset        = DM646X_EMAC_CNTRL_OFFSET,
 346         .ctrl_mod_reg_offset    = DM646X_EMAC_CNTRL_MOD_OFFSET,
 347         .ctrl_ram_offset        = DM646X_EMAC_CNTRL_RAM_OFFSET,
 348         .mdio_reg_offset        = DM646X_EMAC_MDIO_OFFSET,
 349         .ctrl_ram_size          = DM646X_EMAC_CNTRL_RAM_SIZE,
 350         .version                = EMAC_VERSION_2,
 351 };
 352
 353 static struct resource dm646x_emac_resources[] = {
 354         {
 355                 .start  = DM646X_EMAC_BASE,
 356                 .end    = DM646X_EMAC_BASE + 0x47ff,
 357                 .flags  = IORESOURCE_MEM,
 358         },
 359         {
 360                 .start  = IRQ_DM646X_EMACRXTHINT,
 361                 .end    = IRQ_DM646X_EMACRXTHINT,
 362                 .flags  = IORESOURCE_IRQ,
 363         },
 364         {
 365                 .start  = IRQ_DM646X_EMACRXINT,
 366                 .end    = IRQ_DM646X_EMACRXINT,
 367                 .flags  = IORESOURCE_IRQ,
 368         },
 369         {
 370                 .start  = IRQ_DM646X_EMACTXINT,
 371                 .end    = IRQ_DM646X_EMACTXINT,
 372                 .flags  = IORESOURCE_IRQ,
 373         },
 374         {
 375                 .start  = IRQ_DM646X_EMACMISCINT,
 376                 .end    = IRQ_DM646X_EMACMISCINT,
 377                 .flags  = IORESOURCE_IRQ,
 378         },
 379 };
 380
 381 static struct platform_device dm646x_emac_device = {
 382         .name           = "davinci_emac",
 383         .id             = 1,
 384         .dev = {
 385                 .platform_data  = &dm646x_emac_pdata,
 386         },
 387         .num_resources  = ARRAY_SIZE(dm646x_emac_resources),
 388         .resource       = dm646x_emac_resources,
 389 };
 390
 391 #define PINMUX0         0x00
 392 #define PINMUX1         0x04
 393
 394 /*
 395  * Device specific mux setup
 396  *
 397  *      soc     description     mux  mode   mode  mux    dbg
 398  *                              reg  offset mask  mode
 399  */
 400 static const struct mux_config dm646x_pins[] = {
 401 #ifdef CONFIG_DAVINCI_MUX
 402 MUX_CFG(DM646X, ATAEN,          0,   0,     1,    1,     true)
 403
 404 MUX_CFG(DM646X, AUDCK1,         0,   29,    1,    0,     false)
 405
 406 MUX_CFG(DM646X, AUDCK0,         0,   28,    1,    0,     false)
 407
 408 MUX_CFG(DM646X, CRGMUX,                 0,   24,    7,    5,     true)
 409
 410 MUX_CFG(DM646X, STSOMUX_DISABLE,        0,   22,    3,    0,     true)
 411
 412 MUX_CFG(DM646X, STSIMUX_DISABLE,        0,   20,    3,    0,     true)
 413
 414 MUX_CFG(DM646X, PTSOMUX_DISABLE,        0,   18,    3,    0,     true)
 415
 416 MUX_CFG(DM646X, PTSIMUX_DISABLE,        0,   16,    3,    0,     true)
 417
 418 MUX_CFG(DM646X, STSOMUX,                0,   22,    3,    2,     true)
 419
 420 MUX_CFG(DM646X, STSIMUX,                0,   20,    3,    2,     true)
 421
 422 MUX_CFG(DM646X, PTSOMUX_PARALLEL,       0,   18,    3,    2,     true)
 423
 424 MUX_CFG(DM646X, PTSIMUX_PARALLEL,       0,   16,    3,    2,     true)
 425
 426 MUX_CFG(DM646X, PTSOMUX_SERIAL,         0,   18,    3,    3,     true)
 427
 428 MUX_CFG(DM646X, PTSIMUX_SERIAL,         0,   16,    3,    3,     true)
 429 #endif
 430 };
 431
 432 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 433         [IRQ_DM646X_VP_VERTINT0]        = 7,
 434         [IRQ_DM646X_VP_VERTINT1]        = 7,
 435         [IRQ_DM646X_VP_VERTINT2]        = 7,
 436         [IRQ_DM646X_VP_VERTINT3]        = 7,
 437         [IRQ_DM646X_VP_ERRINT]          = 7,
 438         [IRQ_DM646X_RESERVED_1]         = 7,
 439         [IRQ_DM646X_RESERVED_2]         = 7,
 440         [IRQ_DM646X_WDINT]              = 7,
 441         [IRQ_DM646X_CRGENINT0]          = 7,
 442         [IRQ_DM646X_CRGENINT1]          = 7,
 443         [IRQ_DM646X_TSIFINT0]           = 7,
 444         [IRQ_DM646X_TSIFINT1]           = 7,
 445         [IRQ_DM646X_VDCEINT]            = 7,
 446         [IRQ_DM646X_USBINT]             = 7,
 447         [IRQ_DM646X_USBDMAINT]          = 7,
 448         [IRQ_DM646X_PCIINT]             = 7,
 449         [IRQ_CCINT0]                    = 7,    /* dma */
 450         [IRQ_CCERRINT]                  = 7,    /* dma */
 451         [IRQ_TCERRINT0]                 = 7,    /* dma */
 452         [IRQ_TCERRINT]                  = 7,    /* dma */
 453         [IRQ_DM646X_TCERRINT2]          = 7,
 454         [IRQ_DM646X_TCERRINT3]          = 7,
 455         [IRQ_DM646X_IDE]                = 7,
 456         [IRQ_DM646X_HPIINT]             = 7,
 457         [IRQ_DM646X_EMACRXTHINT]        = 7,
 458         [IRQ_DM646X_EMACRXINT]          = 7,
 459         [IRQ_DM646X_EMACTXINT]          = 7,
 460         [IRQ_DM646X_EMACMISCINT]        = 7,
 461         [IRQ_DM646X_MCASP0TXINT]        = 7,
 462         [IRQ_DM646X_MCASP0RXINT]        = 7,
 463         [IRQ_AEMIFINT]                  = 7,
 464         [IRQ_DM646X_RESERVED_3]         = 7,
 465         [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
 466         [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
 467         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 468         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 469         [IRQ_PWMINT0]                   = 7,
 470         [IRQ_PWMINT1]                   = 7,
 471         [IRQ_DM646X_VLQINT]             = 7,
 472         [IRQ_I2C]                       = 7,
 473         [IRQ_UARTINT0]                  = 7,
 474         [IRQ_UARTINT1]                  = 7,
 475         [IRQ_DM646X_UARTINT2]           = 7,
 476         [IRQ_DM646X_SPINT0]             = 7,
 477         [IRQ_DM646X_SPINT1]             = 7,
 478         [IRQ_DM646X_DSP2ARMINT]         = 7,
 479         [IRQ_DM646X_RESERVED_4]         = 7,
 480         [IRQ_DM646X_PSCINT]             = 7,
 481         [IRQ_DM646X_GPIO0]              = 7,
 482         [IRQ_DM646X_GPIO1]              = 7,
 483         [IRQ_DM646X_GPIO2]              = 7,
 484         [IRQ_DM646X_GPIO3]              = 7,
 485         [IRQ_DM646X_GPIO4]              = 7,
 486         [IRQ_DM646X_GPIO5]              = 7,
 487         [IRQ_DM646X_GPIO6]              = 7,
 488         [IRQ_DM646X_GPIO7]              = 7,
 489         [IRQ_DM646X_GPIOBNK0]           = 7,
 490         [IRQ_DM646X_GPIOBNK1]           = 7,
 491         [IRQ_DM646X_GPIOBNK2]           = 7,
 492         [IRQ_DM646X_DDRINT]             = 7,
 493         [IRQ_DM646X_AEMIFINT]           = 7,
 494         [IRQ_COMMTX]                    = 7,
 495         [IRQ_COMMRX]                    = 7,
 496         [IRQ_EMUINT]                    = 7,
 497 };
 498
 499 /*----------------------------------------------------------------------*/
 500
 501 static const s8 dma_chan_dm646x_no_event[] = {
 502          0,  1,  2,  3, 13,
 503         14, 15, 24, 25, 26,
 504         27, 30, 31, 54, 55,
 505         56,
 506         -1
 507 };
 508
 509 /* Four Transfer Controllers on DM646x */
 510 static const s8
 511 dm646x_queue_tc_mapping[][2] = {
 512         /* {event queue no, TC no} */
 513         {0, 0},
 514         {1, 1},
 515         {2, 2},
 516         {3, 3},
 517         {-1, -1},
 518 };
 519
 520 static const s8
 521 dm646x_queue_priority_mapping[][2] = {
 522         /* {event queue no, Priority} */
 523         {0, 4},
 524         {1, 0},
 525         {2, 5},
 526         {3, 1},
 527         {-1, -1},
 528 };
 529
 530 static struct edma_soc_info dm646x_edma_info[] = {
 531         {
 532                 .n_channel              = 64,
 533                 .n_region               = 6,    /* 0-1, 4-7 */
 534                 .n_slot                 = 512,
 535                 .n_tc                   = 4,
 536                 .n_cc                   = 1,
 537                 .noevent                = dma_chan_dm646x_no_event,
 538                 .queue_tc_mapping       = dm646x_queue_tc_mapping,
 539                 .queue_priority_mapping = dm646x_queue_priority_mapping,
 540         },
 541 };
 542
 543 static struct resource edma_resources[] = {
 544         {
 545                 .name   = "edma_cc0",
 546                 .start  = 0x01c00000,
 547                 .end    = 0x01c00000 + SZ_64K - 1,
 548                 .flags  = IORESOURCE_MEM,
 549         },
 550         {
 551                 .name   = "edma_tc0",
 552                 .start  = 0x01c10000,
 553                 .end    = 0x01c10000 + SZ_1K - 1,
 554                 .flags  = IORESOURCE_MEM,
 555         },
 556         {
 557                 .name   = "edma_tc1",
 558                 .start  = 0x01c10400,
 559                 .end    = 0x01c10400 + SZ_1K - 1,
 560                 .flags  = IORESOURCE_MEM,
 561         },
 562         {
 563                 .name   = "edma_tc2",
 564                 .start  = 0x01c10800,
 565                 .end    = 0x01c10800 + SZ_1K - 1,
 566                 .flags  = IORESOURCE_MEM,
 567         },
 568         {
 569                 .name   = "edma_tc3",
 570                 .start  = 0x01c10c00,
 571                 .end    = 0x01c10c00 + SZ_1K - 1,
 572                 .flags  = IORESOURCE_MEM,
 573         },
 574         {
 575                 .name   = "edma0",
 576                 .start  = IRQ_CCINT0,
 577                 .flags  = IORESOURCE_IRQ,
 578         },
 579         {
 580                 .name   = "edma0_err",
 581                 .start  = IRQ_CCERRINT,
 582                 .flags  = IORESOURCE_IRQ,
 583         },
 584         /* not using TC*_ERR */
 585 };
 586
 587 static struct platform_device dm646x_edma_device = {
 588         .name                   = "edma",
 589         .id                     = 0,
 590         .dev.platform_data      = dm646x_edma_info,
 591         .num_resources          = ARRAY_SIZE(edma_resources),
 592         .resource               = edma_resources,
 593 };
 594
 595 static struct resource dm646x_mcasp0_resources[] = {
 596         {
 597                 .name   = "mcasp0",
 598                 .start  = DAVINCI_DM646X_MCASP0_REG_BASE,
 599                 .end    = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
 600                 .flags  = IORESOURCE_MEM,
 601         },
 602         /* first TX, then RX */
 603         {
 604                 .start  = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
 605                 .end    = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
 606                 .flags  = IORESOURCE_DMA,
 607         },
 608         {
 609                 .start  = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
 610                 .end    = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
 611                 .flags  = IORESOURCE_DMA,
 612         },
 613 };
 614
 615 static struct resource dm646x_mcasp1_resources[] = {
 616         {
 617                 .name   = "mcasp1",
 618                 .start  = DAVINCI_DM646X_MCASP1_REG_BASE,
 619                 .end    = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
 620                 .flags  = IORESOURCE_MEM,
 621         },
 622         /* DIT mode, only TX event */
 623         {
 624                 .start  = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
 625                 .end    = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
 626                 .flags  = IORESOURCE_DMA,
 627         },
 628         /* DIT mode, dummy entry */
 629         {
 630                 .start  = -1,
 631                 .end    = -1,
 632                 .flags  = IORESOURCE_DMA,
 633         },
 634 };
 635
 636 static struct platform_device dm646x_mcasp0_device = {
 637         .name           = "davinci-mcasp",
 638         .id             = 0,
 639         .num_resources  = ARRAY_SIZE(dm646x_mcasp0_resources),
 640         .resource       = dm646x_mcasp0_resources,
 641 };
 642
 643 static struct platform_device dm646x_mcasp1_device = {
 644         .name           = "davinci-mcasp",
 645         .id             = 1,
 646         .num_resources  = ARRAY_SIZE(dm646x_mcasp1_resources),
 647         .resource       = dm646x_mcasp1_resources,
 648 };
 649
 650 static struct platform_device dm646x_dit_device = {
 651         .name   = "spdif-dit",
 652         .id     = -1,
 653 };
 654
 655 /*----------------------------------------------------------------------*/
 656
 657 static struct map_desc dm646x_io_desc[] = {
 658         {
 659                 .virtual        = IO_VIRT,
 660                 .pfn            = __phys_to_pfn(IO_PHYS),
 661                 .length         = IO_SIZE,
 662                 .type           = MT_DEVICE
 663         },
 664         {
 665                 .virtual        = SRAM_VIRT,
 666                 .pfn            = __phys_to_pfn(0x00010000),
 667                 .length         = SZ_32K,
 668                 /* MT_MEMORY_NONCACHED requires supersection alignment */
 669                 .type           = MT_DEVICE,
 670         },
 671 };
 672
 673 /* Contents of JTAG ID register used to identify exact cpu type */
 674 static struct davinci_id dm646x_ids[] = {
 675         {
 676                 .variant        = 0x0,
 677                 .part_no        = 0xb770,
 678                 .manufacturer   = 0x017,
 679                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 680                 .name           = "dm6467",
 681         },
 682 };
 683
 684 static void __iomem *dm646x_psc_bases[] = {
 685         IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 686 };
 687
 688 /*
 689  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 690  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 691  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 692  * T1_TOP: Timer 1, top   :  <unused>
 693  */
 694 struct davinci_timer_info dm646x_timer_info = {
 695         .timers         = davinci_timer_instance,
 696         .clockevent_id  = T0_BOT,
 697         .clocksource_id = T0_TOP,
 698 };
 699
 700 static struct plat_serial8250_port dm646x_serial_platform_data[] = {
 701         {
 702                 .mapbase        = DAVINCI_UART0_BASE,
 703                 .irq            = IRQ_UARTINT0,
 704                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 705                                   UPF_IOREMAP,
 706                 .iotype         = UPIO_MEM32,
 707                 .regshift       = 2,
 708         },
 709         {
 710                 .mapbase        = DAVINCI_UART1_BASE,
 711                 .irq            = IRQ_UARTINT1,
 712                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 713                                   UPF_IOREMAP,
 714                 .iotype         = UPIO_MEM32,
 715                 .regshift       = 2,
 716         },
 717         {
 718                 .mapbase        = DAVINCI_UART2_BASE,
 719                 .irq            = IRQ_DM646X_UARTINT2,
 720                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 721                                   UPF_IOREMAP,
 722                 .iotype         = UPIO_MEM32,
 723                 .regshift       = 2,
 724         },
 725         {
 726                 .flags          = 0
 727         },
 728 };
 729
 730 static struct platform_device dm646x_serial_device = {
 731         .name                   = "serial8250",
 732         .id                     = PLAT8250_DEV_PLATFORM,
 733         .dev                    = {
 734                 .platform_data  = dm646x_serial_platform_data,
 735         },
 736 };
 737
 738 static struct davinci_soc_info davinci_soc_info_dm646x = {
 739         .io_desc                = dm646x_io_desc,
 740         .io_desc_num            = ARRAY_SIZE(dm646x_io_desc),
 741         .jtag_id_base           = IO_ADDRESS(0x01c40028),
 742         .ids                    = dm646x_ids,
 743         .ids_num                = ARRAY_SIZE(dm646x_ids),
 744         .cpu_clks               = dm646x_clks,
 745         .psc_bases              = dm646x_psc_bases,
 746         .psc_bases_num          = ARRAY_SIZE(dm646x_psc_bases),
 747         .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 748         .pinmux_pins            = dm646x_pins,
 749         .pinmux_pins_num        = ARRAY_SIZE(dm646x_pins),
 750         .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
 751         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 752         .intc_irq_prios         = dm646x_default_priorities,
 753         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 754         .timer_info             = &dm646x_timer_info,
 755         .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
 756         .gpio_num               = 43, /* Only 33 usable */
 757         .gpio_irq               = IRQ_DM646X_GPIOBNK0,
 758         .serial_dev             = &dm646x_serial_device,
 759         .emac_pdata             = &dm646x_emac_pdata,
 760         .sram_dma               = 0x10010000,
 761         .sram_len               = SZ_32K,
 762 };
 763
 764 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
 765 {
 766         dm646x_mcasp0_device.dev.platform_data = pdata;
 767         platform_device_register(&dm646x_mcasp0_device);
 768 }
 769
 770 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
 771 {
 772         dm646x_mcasp1_device.dev.platform_data = pdata;
 773         platform_device_register(&dm646x_mcasp1_device);
 774         platform_device_register(&dm646x_dit_device);
 775 }
 776
 777 void __init dm646x_init(void)
 778 {
 779         davinci_common_init(&davinci_soc_info_dm646x);
 780 }
 781
 782 static int __init dm646x_init_devices(void)
 783 {
 784         if (!cpu_is_davinci_dm646x())
 785                 return 0;
 786
 787         platform_device_register(&dm646x_edma_device);
 788         platform_device_register(&dm646x_emac_device);
 789         return 0;
 790 }
 791 postcore_initcall(dm646x_init_devices);