2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/dma-mapping.h>
12 #include <linux/dmaengine.h>
13 #include <linux/init.h>
14 #include <linux/clk.h>
15 #include <linux/serial_8250.h>
16 #include <linux/platform_device.h>
17 #include <linux/platform_data/edma.h>
18 #include <linux/platform_data/gpio-davinci.h>
20 #include <asm/mach/map.h>
22 #include <mach/cputype.h>
23 #include <mach/irqs.h>
26 #include <mach/time.h>
27 #include <mach/serial.h>
28 #include <mach/common.h>
35 #define DAVINCI_VPIF_BASE (0x01C12000)
37 #define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
39 #define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
43 * Device specific clocks
45 #define DM646X_REF_FREQ 27000000
46 #define DM646X_AUX_FREQ 24000000
48 #define DM646X_EMAC_BASE 0x01c80000
49 #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
50 #define DM646X_EMAC_CNTRL_OFFSET 0x0000
51 #define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
52 #define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
53 #define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
55 static struct pll_data pll1_data
= {
57 .phys_base
= DAVINCI_PLL1_BASE
,
60 static struct pll_data pll2_data
= {
62 .phys_base
= DAVINCI_PLL2_BASE
,
65 static struct clk ref_clk
= {
67 .rate
= DM646X_REF_FREQ
,
68 .set_rate
= davinci_simple_set_rate
,
71 static struct clk aux_clkin
= {
73 .rate
= DM646X_AUX_FREQ
,
76 static struct clk pll1_clk
= {
79 .pll_data
= &pll1_data
,
83 static struct clk pll1_sysclk1
= {
84 .name
= "pll1_sysclk1",
90 static struct clk pll1_sysclk2
= {
91 .name
= "pll1_sysclk2",
97 static struct clk pll1_sysclk3
= {
98 .name
= "pll1_sysclk3",
104 static struct clk pll1_sysclk4
= {
105 .name
= "pll1_sysclk4",
111 static struct clk pll1_sysclk5
= {
112 .name
= "pll1_sysclk5",
118 static struct clk pll1_sysclk6
= {
119 .name
= "pll1_sysclk6",
125 static struct clk pll1_sysclk8
= {
126 .name
= "pll1_sysclk8",
132 static struct clk pll1_sysclk9
= {
133 .name
= "pll1_sysclk9",
139 static struct clk pll1_sysclkbp
= {
140 .name
= "pll1_sysclkbp",
142 .flags
= CLK_PLL
| PRE_PLL
,
146 static struct clk pll1_aux_clk
= {
147 .name
= "pll1_aux_clk",
149 .flags
= CLK_PLL
| PRE_PLL
,
152 static struct clk pll2_clk
= {
155 .pll_data
= &pll2_data
,
159 static struct clk pll2_sysclk1
= {
160 .name
= "pll2_sysclk1",
166 static struct clk dsp_clk
= {
168 .parent
= &pll1_sysclk1
,
169 .lpsc
= DM646X_LPSC_C64X_CPU
,
170 .usecount
= 1, /* REVISIT how to disable? */
173 static struct clk arm_clk
= {
175 .parent
= &pll1_sysclk2
,
176 .lpsc
= DM646X_LPSC_ARM
,
177 .flags
= ALWAYS_ENABLED
,
180 static struct clk edma_cc_clk
= {
182 .parent
= &pll1_sysclk2
,
183 .lpsc
= DM646X_LPSC_TPCC
,
184 .flags
= ALWAYS_ENABLED
,
187 static struct clk edma_tc0_clk
= {
189 .parent
= &pll1_sysclk2
,
190 .lpsc
= DM646X_LPSC_TPTC0
,
191 .flags
= ALWAYS_ENABLED
,
194 static struct clk edma_tc1_clk
= {
196 .parent
= &pll1_sysclk2
,
197 .lpsc
= DM646X_LPSC_TPTC1
,
198 .flags
= ALWAYS_ENABLED
,
201 static struct clk edma_tc2_clk
= {
203 .parent
= &pll1_sysclk2
,
204 .lpsc
= DM646X_LPSC_TPTC2
,
205 .flags
= ALWAYS_ENABLED
,
208 static struct clk edma_tc3_clk
= {
210 .parent
= &pll1_sysclk2
,
211 .lpsc
= DM646X_LPSC_TPTC3
,
212 .flags
= ALWAYS_ENABLED
,
215 static struct clk uart0_clk
= {
217 .parent
= &aux_clkin
,
218 .lpsc
= DM646X_LPSC_UART0
,
221 static struct clk uart1_clk
= {
223 .parent
= &aux_clkin
,
224 .lpsc
= DM646X_LPSC_UART1
,
227 static struct clk uart2_clk
= {
229 .parent
= &aux_clkin
,
230 .lpsc
= DM646X_LPSC_UART2
,
233 static struct clk i2c_clk
= {
235 .parent
= &pll1_sysclk3
,
236 .lpsc
= DM646X_LPSC_I2C
,
239 static struct clk gpio_clk
= {
241 .parent
= &pll1_sysclk3
,
242 .lpsc
= DM646X_LPSC_GPIO
,
245 static struct clk mcasp0_clk
= {
247 .parent
= &pll1_sysclk3
,
248 .lpsc
= DM646X_LPSC_McASP0
,
251 static struct clk mcasp1_clk
= {
253 .parent
= &pll1_sysclk3
,
254 .lpsc
= DM646X_LPSC_McASP1
,
257 static struct clk aemif_clk
= {
259 .parent
= &pll1_sysclk3
,
260 .lpsc
= DM646X_LPSC_AEMIF
,
261 .flags
= ALWAYS_ENABLED
,
264 static struct clk emac_clk
= {
266 .parent
= &pll1_sysclk3
,
267 .lpsc
= DM646X_LPSC_EMAC
,
270 static struct clk pwm0_clk
= {
272 .parent
= &pll1_sysclk3
,
273 .lpsc
= DM646X_LPSC_PWM0
,
274 .usecount
= 1, /* REVIST: disabling hangs system */
277 static struct clk pwm1_clk
= {
279 .parent
= &pll1_sysclk3
,
280 .lpsc
= DM646X_LPSC_PWM1
,
281 .usecount
= 1, /* REVIST: disabling hangs system */
284 static struct clk timer0_clk
= {
286 .parent
= &pll1_sysclk3
,
287 .lpsc
= DM646X_LPSC_TIMER0
,
290 static struct clk timer1_clk
= {
292 .parent
= &pll1_sysclk3
,
293 .lpsc
= DM646X_LPSC_TIMER1
,
296 static struct clk timer2_clk
= {
298 .parent
= &pll1_sysclk3
,
299 .flags
= ALWAYS_ENABLED
, /* no LPSC, always enabled; c.f. spruep9a */
303 static struct clk ide_clk
= {
305 .parent
= &pll1_sysclk4
,
306 .lpsc
= DAVINCI_LPSC_ATA
,
309 static struct clk vpif0_clk
= {
312 .lpsc
= DM646X_LPSC_VPSSMSTR
,
313 .flags
= ALWAYS_ENABLED
,
316 static struct clk vpif1_clk
= {
319 .lpsc
= DM646X_LPSC_VPSSSLV
,
320 .flags
= ALWAYS_ENABLED
,
323 static struct clk_lookup dm646x_clks
[] = {
324 CLK(NULL
, "ref", &ref_clk
),
325 CLK(NULL
, "aux", &aux_clkin
),
326 CLK(NULL
, "pll1", &pll1_clk
),
327 CLK(NULL
, "pll1_sysclk", &pll1_sysclk1
),
328 CLK(NULL
, "pll1_sysclk", &pll1_sysclk2
),
329 CLK(NULL
, "pll1_sysclk", &pll1_sysclk3
),
330 CLK(NULL
, "pll1_sysclk", &pll1_sysclk4
),
331 CLK(NULL
, "pll1_sysclk", &pll1_sysclk5
),
332 CLK(NULL
, "pll1_sysclk", &pll1_sysclk6
),
333 CLK(NULL
, "pll1_sysclk", &pll1_sysclk8
),
334 CLK(NULL
, "pll1_sysclk", &pll1_sysclk9
),
335 CLK(NULL
, "pll1_sysclk", &pll1_sysclkbp
),
336 CLK(NULL
, "pll1_aux", &pll1_aux_clk
),
337 CLK(NULL
, "pll2", &pll2_clk
),
338 CLK(NULL
, "pll2_sysclk1", &pll2_sysclk1
),
339 CLK(NULL
, "dsp", &dsp_clk
),
340 CLK(NULL
, "arm", &arm_clk
),
341 CLK(NULL
, "edma_cc", &edma_cc_clk
),
342 CLK(NULL
, "edma_tc0", &edma_tc0_clk
),
343 CLK(NULL
, "edma_tc1", &edma_tc1_clk
),
344 CLK(NULL
, "edma_tc2", &edma_tc2_clk
),
345 CLK(NULL
, "edma_tc3", &edma_tc3_clk
),
346 CLK("serial8250.0", NULL
, &uart0_clk
),
347 CLK("serial8250.1", NULL
, &uart1_clk
),
348 CLK("serial8250.2", NULL
, &uart2_clk
),
349 CLK("i2c_davinci.1", NULL
, &i2c_clk
),
350 CLK(NULL
, "gpio", &gpio_clk
),
351 CLK("davinci-mcasp.0", NULL
, &mcasp0_clk
),
352 CLK("davinci-mcasp.1", NULL
, &mcasp1_clk
),
353 CLK(NULL
, "aemif", &aemif_clk
),
354 CLK("davinci_emac.1", NULL
, &emac_clk
),
355 CLK("davinci_mdio.0", "fck", &emac_clk
),
356 CLK(NULL
, "pwm0", &pwm0_clk
),
357 CLK(NULL
, "pwm1", &pwm1_clk
),
358 CLK(NULL
, "timer0", &timer0_clk
),
359 CLK(NULL
, "timer1", &timer1_clk
),
360 CLK("davinci-wdt", NULL
, &timer2_clk
),
361 CLK("palm_bk3710", NULL
, &ide_clk
),
362 CLK(NULL
, "vpif0", &vpif0_clk
),
363 CLK(NULL
, "vpif1", &vpif1_clk
),
364 CLK(NULL
, NULL
, NULL
),
367 static struct emac_platform_data dm646x_emac_pdata
= {
368 .ctrl_reg_offset
= DM646X_EMAC_CNTRL_OFFSET
,
369 .ctrl_mod_reg_offset
= DM646X_EMAC_CNTRL_MOD_OFFSET
,
370 .ctrl_ram_offset
= DM646X_EMAC_CNTRL_RAM_OFFSET
,
371 .ctrl_ram_size
= DM646X_EMAC_CNTRL_RAM_SIZE
,
372 .version
= EMAC_VERSION_2
,
375 static struct resource dm646x_emac_resources
[] = {
377 .start
= DM646X_EMAC_BASE
,
378 .end
= DM646X_EMAC_BASE
+ SZ_16K
- 1,
379 .flags
= IORESOURCE_MEM
,
382 .start
= IRQ_DM646X_EMACRXTHINT
,
383 .end
= IRQ_DM646X_EMACRXTHINT
,
384 .flags
= IORESOURCE_IRQ
,
387 .start
= IRQ_DM646X_EMACRXINT
,
388 .end
= IRQ_DM646X_EMACRXINT
,
389 .flags
= IORESOURCE_IRQ
,
392 .start
= IRQ_DM646X_EMACTXINT
,
393 .end
= IRQ_DM646X_EMACTXINT
,
394 .flags
= IORESOURCE_IRQ
,
397 .start
= IRQ_DM646X_EMACMISCINT
,
398 .end
= IRQ_DM646X_EMACMISCINT
,
399 .flags
= IORESOURCE_IRQ
,
403 static struct platform_device dm646x_emac_device
= {
404 .name
= "davinci_emac",
407 .platform_data
= &dm646x_emac_pdata
,
409 .num_resources
= ARRAY_SIZE(dm646x_emac_resources
),
410 .resource
= dm646x_emac_resources
,
413 static struct resource dm646x_mdio_resources
[] = {
415 .start
= DM646X_EMAC_MDIO_BASE
,
416 .end
= DM646X_EMAC_MDIO_BASE
+ SZ_4K
- 1,
417 .flags
= IORESOURCE_MEM
,
421 static struct platform_device dm646x_mdio_device
= {
422 .name
= "davinci_mdio",
424 .num_resources
= ARRAY_SIZE(dm646x_mdio_resources
),
425 .resource
= dm646x_mdio_resources
,
429 * Device specific mux setup
431 * soc description mux mode mode mux dbg
432 * reg offset mask mode
434 static const struct mux_config dm646x_pins
[] = {
435 #ifdef CONFIG_DAVINCI_MUX
436 MUX_CFG(DM646X
, ATAEN
, 0, 0, 5, 1, true)
438 MUX_CFG(DM646X
, AUDCK1
, 0, 29, 1, 0, false)
440 MUX_CFG(DM646X
, AUDCK0
, 0, 28, 1, 0, false)
442 MUX_CFG(DM646X
, CRGMUX
, 0, 24, 7, 5, true)
444 MUX_CFG(DM646X
, STSOMUX_DISABLE
, 0, 22, 3, 0, true)
446 MUX_CFG(DM646X
, STSIMUX_DISABLE
, 0, 20, 3, 0, true)
448 MUX_CFG(DM646X
, PTSOMUX_DISABLE
, 0, 18, 3, 0, true)
450 MUX_CFG(DM646X
, PTSIMUX_DISABLE
, 0, 16, 3, 0, true)
452 MUX_CFG(DM646X
, STSOMUX
, 0, 22, 3, 2, true)
454 MUX_CFG(DM646X
, STSIMUX
, 0, 20, 3, 2, true)
456 MUX_CFG(DM646X
, PTSOMUX_PARALLEL
, 0, 18, 3, 2, true)
458 MUX_CFG(DM646X
, PTSIMUX_PARALLEL
, 0, 16, 3, 2, true)
460 MUX_CFG(DM646X
, PTSOMUX_SERIAL
, 0, 18, 3, 3, true)
462 MUX_CFG(DM646X
, PTSIMUX_SERIAL
, 0, 16, 3, 3, true)
466 static u8 dm646x_default_priorities
[DAVINCI_N_AINTC_IRQ
] = {
467 [IRQ_DM646X_VP_VERTINT0
] = 7,
468 [IRQ_DM646X_VP_VERTINT1
] = 7,
469 [IRQ_DM646X_VP_VERTINT2
] = 7,
470 [IRQ_DM646X_VP_VERTINT3
] = 7,
471 [IRQ_DM646X_VP_ERRINT
] = 7,
472 [IRQ_DM646X_RESERVED_1
] = 7,
473 [IRQ_DM646X_RESERVED_2
] = 7,
474 [IRQ_DM646X_WDINT
] = 7,
475 [IRQ_DM646X_CRGENINT0
] = 7,
476 [IRQ_DM646X_CRGENINT1
] = 7,
477 [IRQ_DM646X_TSIFINT0
] = 7,
478 [IRQ_DM646X_TSIFINT1
] = 7,
479 [IRQ_DM646X_VDCEINT
] = 7,
480 [IRQ_DM646X_USBINT
] = 7,
481 [IRQ_DM646X_USBDMAINT
] = 7,
482 [IRQ_DM646X_PCIINT
] = 7,
483 [IRQ_CCINT0
] = 7, /* dma */
484 [IRQ_CCERRINT
] = 7, /* dma */
485 [IRQ_TCERRINT0
] = 7, /* dma */
486 [IRQ_TCERRINT
] = 7, /* dma */
487 [IRQ_DM646X_TCERRINT2
] = 7,
488 [IRQ_DM646X_TCERRINT3
] = 7,
489 [IRQ_DM646X_IDE
] = 7,
490 [IRQ_DM646X_HPIINT
] = 7,
491 [IRQ_DM646X_EMACRXTHINT
] = 7,
492 [IRQ_DM646X_EMACRXINT
] = 7,
493 [IRQ_DM646X_EMACTXINT
] = 7,
494 [IRQ_DM646X_EMACMISCINT
] = 7,
495 [IRQ_DM646X_MCASP0TXINT
] = 7,
496 [IRQ_DM646X_MCASP0RXINT
] = 7,
497 [IRQ_DM646X_RESERVED_3
] = 7,
498 [IRQ_DM646X_MCASP1TXINT
] = 7,
499 [IRQ_TINT0_TINT12
] = 7, /* clockevent */
500 [IRQ_TINT0_TINT34
] = 7, /* clocksource */
501 [IRQ_TINT1_TINT12
] = 7, /* DSP timer */
502 [IRQ_TINT1_TINT34
] = 7, /* system tick */
505 [IRQ_DM646X_VLQINT
] = 7,
509 [IRQ_DM646X_UARTINT2
] = 7,
510 [IRQ_DM646X_SPINT0
] = 7,
511 [IRQ_DM646X_SPINT1
] = 7,
512 [IRQ_DM646X_DSP2ARMINT
] = 7,
513 [IRQ_DM646X_RESERVED_4
] = 7,
514 [IRQ_DM646X_PSCINT
] = 7,
515 [IRQ_DM646X_GPIO0
] = 7,
516 [IRQ_DM646X_GPIO1
] = 7,
517 [IRQ_DM646X_GPIO2
] = 7,
518 [IRQ_DM646X_GPIO3
] = 7,
519 [IRQ_DM646X_GPIO4
] = 7,
520 [IRQ_DM646X_GPIO5
] = 7,
521 [IRQ_DM646X_GPIO6
] = 7,
522 [IRQ_DM646X_GPIO7
] = 7,
523 [IRQ_DM646X_GPIOBNK0
] = 7,
524 [IRQ_DM646X_GPIOBNK1
] = 7,
525 [IRQ_DM646X_GPIOBNK2
] = 7,
526 [IRQ_DM646X_DDRINT
] = 7,
527 [IRQ_DM646X_AEMIFINT
] = 7,
533 /*----------------------------------------------------------------------*/
535 /* Four Transfer Controllers on DM646x */
536 static s8 dm646x_queue_priority_mapping
[][2] = {
537 /* {event queue no, Priority} */
545 static const struct dma_slave_map dm646x_edma_map
[] = {
546 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) },
547 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) },
548 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) },
549 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
550 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
553 static struct edma_soc_info dm646x_edma_pdata
= {
554 .queue_priority_mapping
= dm646x_queue_priority_mapping
,
555 .default_queue
= EVENTQ_1
,
556 .slave_map
= dm646x_edma_map
,
557 .slavecnt
= ARRAY_SIZE(dm646x_edma_map
),
560 static struct resource edma_resources
[] = {
564 .end
= 0x01c00000 + SZ_64K
- 1,
565 .flags
= IORESOURCE_MEM
,
570 .end
= 0x01c10000 + SZ_1K
- 1,
571 .flags
= IORESOURCE_MEM
,
576 .end
= 0x01c10400 + SZ_1K
- 1,
577 .flags
= IORESOURCE_MEM
,
582 .end
= 0x01c10800 + SZ_1K
- 1,
583 .flags
= IORESOURCE_MEM
,
588 .end
= 0x01c10c00 + SZ_1K
- 1,
589 .flags
= IORESOURCE_MEM
,
592 .name
= "edma3_ccint",
594 .flags
= IORESOURCE_IRQ
,
597 .name
= "edma3_ccerrint",
598 .start
= IRQ_CCERRINT
,
599 .flags
= IORESOURCE_IRQ
,
601 /* not using TC*_ERR */
604 static const struct platform_device_info dm646x_edma_device __initconst
= {
607 .dma_mask
= DMA_BIT_MASK(32),
608 .res
= edma_resources
,
609 .num_res
= ARRAY_SIZE(edma_resources
),
610 .data
= &dm646x_edma_pdata
,
611 .size_data
= sizeof(dm646x_edma_pdata
),
614 static struct resource dm646x_mcasp0_resources
[] = {
617 .start
= DAVINCI_DM646X_MCASP0_REG_BASE
,
618 .end
= DAVINCI_DM646X_MCASP0_REG_BASE
+ (SZ_1K
<< 1) - 1,
619 .flags
= IORESOURCE_MEM
,
623 .start
= DAVINCI_DM646X_DMA_MCASP0_AXEVT0
,
624 .end
= DAVINCI_DM646X_DMA_MCASP0_AXEVT0
,
625 .flags
= IORESOURCE_DMA
,
629 .start
= DAVINCI_DM646X_DMA_MCASP0_AREVT0
,
630 .end
= DAVINCI_DM646X_DMA_MCASP0_AREVT0
,
631 .flags
= IORESOURCE_DMA
,
635 .start
= IRQ_DM646X_MCASP0TXINT
,
636 .flags
= IORESOURCE_IRQ
,
640 .start
= IRQ_DM646X_MCASP0RXINT
,
641 .flags
= IORESOURCE_IRQ
,
645 /* DIT mode only, rx is not supported */
646 static struct resource dm646x_mcasp1_resources
[] = {
649 .start
= DAVINCI_DM646X_MCASP1_REG_BASE
,
650 .end
= DAVINCI_DM646X_MCASP1_REG_BASE
+ (SZ_1K
<< 1) - 1,
651 .flags
= IORESOURCE_MEM
,
655 .start
= DAVINCI_DM646X_DMA_MCASP1_AXEVT1
,
656 .end
= DAVINCI_DM646X_DMA_MCASP1_AXEVT1
,
657 .flags
= IORESOURCE_DMA
,
661 .start
= IRQ_DM646X_MCASP1TXINT
,
662 .flags
= IORESOURCE_IRQ
,
666 static struct platform_device dm646x_mcasp0_device
= {
667 .name
= "davinci-mcasp",
669 .num_resources
= ARRAY_SIZE(dm646x_mcasp0_resources
),
670 .resource
= dm646x_mcasp0_resources
,
673 static struct platform_device dm646x_mcasp1_device
= {
674 .name
= "davinci-mcasp",
676 .num_resources
= ARRAY_SIZE(dm646x_mcasp1_resources
),
677 .resource
= dm646x_mcasp1_resources
,
680 static struct platform_device dm646x_dit_device
= {
685 static u64 vpif_dma_mask
= DMA_BIT_MASK(32);
687 static struct resource vpif_resource
[] = {
689 .start
= DAVINCI_VPIF_BASE
,
690 .end
= DAVINCI_VPIF_BASE
+ 0x03ff,
691 .flags
= IORESOURCE_MEM
,
695 static struct platform_device vpif_dev
= {
699 .dma_mask
= &vpif_dma_mask
,
700 .coherent_dma_mask
= DMA_BIT_MASK(32),
702 .resource
= vpif_resource
,
703 .num_resources
= ARRAY_SIZE(vpif_resource
),
706 static struct resource vpif_display_resource
[] = {
708 .start
= IRQ_DM646X_VP_VERTINT2
,
709 .end
= IRQ_DM646X_VP_VERTINT2
,
710 .flags
= IORESOURCE_IRQ
,
713 .start
= IRQ_DM646X_VP_VERTINT3
,
714 .end
= IRQ_DM646X_VP_VERTINT3
,
715 .flags
= IORESOURCE_IRQ
,
719 static struct platform_device vpif_display_dev
= {
720 .name
= "vpif_display",
723 .dma_mask
= &vpif_dma_mask
,
724 .coherent_dma_mask
= DMA_BIT_MASK(32),
726 .resource
= vpif_display_resource
,
727 .num_resources
= ARRAY_SIZE(vpif_display_resource
),
730 static struct resource vpif_capture_resource
[] = {
732 .start
= IRQ_DM646X_VP_VERTINT0
,
733 .end
= IRQ_DM646X_VP_VERTINT0
,
734 .flags
= IORESOURCE_IRQ
,
737 .start
= IRQ_DM646X_VP_VERTINT1
,
738 .end
= IRQ_DM646X_VP_VERTINT1
,
739 .flags
= IORESOURCE_IRQ
,
743 static struct platform_device vpif_capture_dev
= {
744 .name
= "vpif_capture",
747 .dma_mask
= &vpif_dma_mask
,
748 .coherent_dma_mask
= DMA_BIT_MASK(32),
750 .resource
= vpif_capture_resource
,
751 .num_resources
= ARRAY_SIZE(vpif_capture_resource
),
754 static struct resource dm646x_gpio_resources
[] = {
756 .start
= DAVINCI_GPIO_BASE
,
757 .end
= DAVINCI_GPIO_BASE
+ SZ_4K
- 1,
758 .flags
= IORESOURCE_MEM
,
761 .start
= IRQ_DM646X_GPIOBNK0
,
762 .end
= IRQ_DM646X_GPIOBNK2
,
763 .flags
= IORESOURCE_IRQ
,
767 static struct davinci_gpio_platform_data dm646x_gpio_platform_data
= {
771 int __init
dm646x_gpio_register(void)
773 return davinci_gpio_register(dm646x_gpio_resources
,
774 ARRAY_SIZE(dm646x_gpio_resources
),
775 &dm646x_gpio_platform_data
);
777 /*----------------------------------------------------------------------*/
779 static struct map_desc dm646x_io_desc
[] = {
782 .pfn
= __phys_to_pfn(IO_PHYS
),
788 /* Contents of JTAG ID register used to identify exact cpu type */
789 static struct davinci_id dm646x_ids
[] = {
793 .manufacturer
= 0x017,
794 .cpu_id
= DAVINCI_CPU_ID_DM6467
,
795 .name
= "dm6467_rev1.x",
800 .manufacturer
= 0x017,
801 .cpu_id
= DAVINCI_CPU_ID_DM6467
,
802 .name
= "dm6467_rev3.x",
806 static u32 dm646x_psc_bases
[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE
};
809 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
810 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
811 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
812 * T1_TOP: Timer 1, top : <unused>
814 static struct davinci_timer_info dm646x_timer_info
= {
815 .timers
= davinci_timer_instance
,
816 .clockevent_id
= T0_BOT
,
817 .clocksource_id
= T0_TOP
,
820 static struct plat_serial8250_port dm646x_serial0_platform_data
[] = {
822 .mapbase
= DAVINCI_UART0_BASE
,
824 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
826 .iotype
= UPIO_MEM32
,
833 static struct plat_serial8250_port dm646x_serial1_platform_data
[] = {
835 .mapbase
= DAVINCI_UART1_BASE
,
837 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
839 .iotype
= UPIO_MEM32
,
846 static struct plat_serial8250_port dm646x_serial2_platform_data
[] = {
848 .mapbase
= DAVINCI_UART2_BASE
,
849 .irq
= IRQ_DM646X_UARTINT2
,
850 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
852 .iotype
= UPIO_MEM32
,
860 struct platform_device dm646x_serial_device
[] = {
862 .name
= "serial8250",
863 .id
= PLAT8250_DEV_PLATFORM
,
865 .platform_data
= dm646x_serial0_platform_data
,
869 .name
= "serial8250",
870 .id
= PLAT8250_DEV_PLATFORM1
,
872 .platform_data
= dm646x_serial1_platform_data
,
876 .name
= "serial8250",
877 .id
= PLAT8250_DEV_PLATFORM2
,
879 .platform_data
= dm646x_serial2_platform_data
,
886 static struct davinci_soc_info davinci_soc_info_dm646x
= {
887 .io_desc
= dm646x_io_desc
,
888 .io_desc_num
= ARRAY_SIZE(dm646x_io_desc
),
889 .jtag_id_reg
= 0x01c40028,
891 .ids_num
= ARRAY_SIZE(dm646x_ids
),
892 .cpu_clks
= dm646x_clks
,
893 .psc_bases
= dm646x_psc_bases
,
894 .psc_bases_num
= ARRAY_SIZE(dm646x_psc_bases
),
895 .pinmux_base
= DAVINCI_SYSTEM_MODULE_BASE
,
896 .pinmux_pins
= dm646x_pins
,
897 .pinmux_pins_num
= ARRAY_SIZE(dm646x_pins
),
898 .intc_base
= DAVINCI_ARM_INTC_BASE
,
899 .intc_type
= DAVINCI_INTC_TYPE_AINTC
,
900 .intc_irq_prios
= dm646x_default_priorities
,
901 .intc_irq_num
= DAVINCI_N_AINTC_IRQ
,
902 .timer_info
= &dm646x_timer_info
,
903 .emac_pdata
= &dm646x_emac_pdata
,
904 .sram_dma
= 0x10010000,
908 void __init
dm646x_init_mcasp0(struct snd_platform_data
*pdata
)
910 dm646x_mcasp0_device
.dev
.platform_data
= pdata
;
911 platform_device_register(&dm646x_mcasp0_device
);
914 void __init
dm646x_init_mcasp1(struct snd_platform_data
*pdata
)
916 dm646x_mcasp1_device
.dev
.platform_data
= pdata
;
917 platform_device_register(&dm646x_mcasp1_device
);
918 platform_device_register(&dm646x_dit_device
);
921 void dm646x_setup_vpif(struct vpif_display_config
*display_config
,
922 struct vpif_capture_config
*capture_config
)
926 value
= __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS
));
927 value
&= ~VSCLKDIS_MASK
;
928 __raw_writel(value
, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS
));
930 value
= __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN
));
931 value
&= ~VDD3P3V_VID_MASK
;
932 __raw_writel(value
, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN
));
934 davinci_cfg_reg(DM646X_STSOMUX_DISABLE
);
935 davinci_cfg_reg(DM646X_STSIMUX_DISABLE
);
936 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE
);
937 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE
);
939 vpif_display_dev
.dev
.platform_data
= display_config
;
940 vpif_capture_dev
.dev
.platform_data
= capture_config
;
941 platform_device_register(&vpif_dev
);
942 platform_device_register(&vpif_display_dev
);
943 platform_device_register(&vpif_capture_dev
);
946 int __init
dm646x_init_edma(struct edma_rsv_info
*rsv
)
948 struct platform_device
*edma_pdev
;
950 dm646x_edma_pdata
.rsv
= rsv
;
952 edma_pdev
= platform_device_register_full(&dm646x_edma_device
);
953 return IS_ERR(edma_pdev
) ? PTR_ERR(edma_pdev
) : 0;
956 void __init
dm646x_init(void)
958 davinci_common_init(&davinci_soc_info_dm646x
);
959 davinci_map_sysmod();
960 davinci_clk_init(davinci_soc_info_dm646x
.cpu_clks
);
963 static int __init
dm646x_init_devices(void)
967 if (!cpu_is_davinci_dm646x())
970 platform_device_register(&dm646x_mdio_device
);
971 platform_device_register(&dm646x_emac_device
);
973 ret
= davinci_init_wdt();
975 pr_warn("%s: watchdog init failed: %d\n", __func__
, ret
);
979 postcore_initcall(dm646x_init_devices
);