2 * TI DaVinci GPIO Support
4 * Copyright (c) 2006-2007 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/errno.h>
14 #include <linux/kernel.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
19 #include <mach/gpio.h>
21 #include <asm/mach/irq.h>
23 struct davinci_gpio_regs
{
36 #define chip2controller(chip) \
37 container_of(chip, struct davinci_gpio_controller, chip)
39 static struct davinci_gpio_controller chips
[DIV_ROUND_UP(DAVINCI_N_GPIO
, 32)];
41 static struct davinci_gpio_regs __iomem __init
*gpio2regs(unsigned gpio
)
44 void __iomem
*base
= davinci_soc_info
.gpio_base
;
48 else if (gpio
< 32 * 2)
50 else if (gpio
< 32 * 3)
52 else if (gpio
< 32 * 4)
54 else if (gpio
< 32 * 5)
61 static inline struct davinci_gpio_regs __iomem
*irq2regs(int irq
)
63 struct davinci_gpio_regs __iomem
*g
;
65 g
= (__force
struct davinci_gpio_regs __iomem
*)get_irq_chip_data(irq
);
70 static int __init
davinci_gpio_irq_setup(void);
72 /*--------------------------------------------------------------------------*/
74 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
75 static inline int __davinci_direction(struct gpio_chip
*chip
,
76 unsigned offset
, bool out
, int value
)
78 struct davinci_gpio_controller
*d
= chip2controller(chip
);
79 struct davinci_gpio_regs __iomem
*g
= d
->regs
;
82 u32 mask
= 1 << offset
;
84 spin_lock_irqsave(&d
->lock
, flags
);
85 temp
= __raw_readl(&g
->dir
);
88 __raw_writel(mask
, value
? &g
->set_data
: &g
->clr_data
);
92 __raw_writel(temp
, &g
->dir
);
93 spin_unlock_irqrestore(&d
->lock
, flags
);
98 static int davinci_direction_in(struct gpio_chip
*chip
, unsigned offset
)
100 return __davinci_direction(chip
, offset
, false, 0);
104 davinci_direction_out(struct gpio_chip
*chip
, unsigned offset
, int value
)
106 return __davinci_direction(chip
, offset
, true, value
);
110 * Read the pin's value (works even if it's set up as output);
111 * returns zero/nonzero.
113 * Note that changes are synched to the GPIO clock, so reading values back
114 * right after you've set them may give old values.
116 static int davinci_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
118 struct davinci_gpio_controller
*d
= chip2controller(chip
);
119 struct davinci_gpio_regs __iomem
*g
= d
->regs
;
121 return (1 << offset
) & __raw_readl(&g
->in_data
);
125 * Assuming the pin is muxed as a gpio output, set its output value.
128 davinci_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
130 struct davinci_gpio_controller
*d
= chip2controller(chip
);
131 struct davinci_gpio_regs __iomem
*g
= d
->regs
;
133 __raw_writel((1 << offset
), value
? &g
->set_data
: &g
->clr_data
);
136 static int __init
davinci_gpio_setup(void)
140 struct davinci_soc_info
*soc_info
= &davinci_soc_info
;
141 struct davinci_gpio_regs
*regs
;
143 if (soc_info
->gpio_type
!= GPIO_TYPE_DAVINCI
)
147 * The gpio banks conceptually expose a segmented bitmap,
148 * and "ngpio" is one more than the largest zero-based
149 * bit index that's valid.
151 ngpio
= soc_info
->gpio_num
;
153 pr_err("GPIO setup: how many GPIOs?\n");
157 if (WARN_ON(DAVINCI_N_GPIO
< ngpio
))
158 ngpio
= DAVINCI_N_GPIO
;
160 for (i
= 0, base
= 0; base
< ngpio
; i
++, base
+= 32) {
161 chips
[i
].chip
.label
= "DaVinci";
163 chips
[i
].chip
.direction_input
= davinci_direction_in
;
164 chips
[i
].chip
.get
= davinci_gpio_get
;
165 chips
[i
].chip
.direction_output
= davinci_direction_out
;
166 chips
[i
].chip
.set
= davinci_gpio_set
;
168 chips
[i
].chip
.base
= base
;
169 chips
[i
].chip
.ngpio
= ngpio
- base
;
170 if (chips
[i
].chip
.ngpio
> 32)
171 chips
[i
].chip
.ngpio
= 32;
173 spin_lock_init(&chips
[i
].lock
);
175 regs
= gpio2regs(base
);
176 chips
[i
].regs
= regs
;
177 chips
[i
].set_data
= ®s
->set_data
;
178 chips
[i
].clr_data
= ®s
->clr_data
;
179 chips
[i
].in_data
= ®s
->in_data
;
181 gpiochip_add(&chips
[i
].chip
);
184 soc_info
->gpio_ctlrs
= chips
;
185 soc_info
->gpio_ctlrs_num
= DIV_ROUND_UP(ngpio
, 32);
187 davinci_gpio_irq_setup();
190 pure_initcall(davinci_gpio_setup
);
192 /*--------------------------------------------------------------------------*/
194 * We expect irqs will normally be set up as input pins, but they can also be
195 * used as output pins ... which is convenient for testing.
197 * NOTE: The first few GPIOs also have direct INTC hookups in addition
198 * to their GPIOBNK0 irq, with a bit less overhead.
200 * All those INTC hookups (direct, plus several IRQ banks) can also
201 * serve as EDMA event triggers.
204 static void gpio_irq_disable(unsigned irq
)
206 struct davinci_gpio_regs __iomem
*g
= irq2regs(irq
);
207 u32 mask
= (u32
) get_irq_data(irq
);
209 __raw_writel(mask
, &g
->clr_falling
);
210 __raw_writel(mask
, &g
->clr_rising
);
213 static void gpio_irq_enable(unsigned irq
)
215 struct davinci_gpio_regs __iomem
*g
= irq2regs(irq
);
216 u32 mask
= (u32
) get_irq_data(irq
);
217 unsigned status
= irq_desc
[irq
].status
;
219 status
&= IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
;
221 status
= IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
;
223 if (status
& IRQ_TYPE_EDGE_FALLING
)
224 __raw_writel(mask
, &g
->set_falling
);
225 if (status
& IRQ_TYPE_EDGE_RISING
)
226 __raw_writel(mask
, &g
->set_rising
);
229 static int gpio_irq_type(unsigned irq
, unsigned trigger
)
231 struct davinci_gpio_regs __iomem
*g
= irq2regs(irq
);
232 u32 mask
= (u32
) get_irq_data(irq
);
234 if (trigger
& ~(IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
237 irq_desc
[irq
].status
&= ~IRQ_TYPE_SENSE_MASK
;
238 irq_desc
[irq
].status
|= trigger
;
240 /* don't enable the IRQ if it's currently disabled */
241 if (irq_desc
[irq
].depth
== 0) {
242 __raw_writel(mask
, (trigger
& IRQ_TYPE_EDGE_FALLING
)
243 ? &g
->set_falling
: &g
->clr_falling
);
244 __raw_writel(mask
, (trigger
& IRQ_TYPE_EDGE_RISING
)
245 ? &g
->set_rising
: &g
->clr_rising
);
250 static struct irq_chip gpio_irqchip
= {
252 .enable
= gpio_irq_enable
,
253 .disable
= gpio_irq_disable
,
254 .set_type
= gpio_irq_type
,
258 gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
260 struct davinci_gpio_regs __iomem
*g
= irq2regs(irq
);
263 /* we only care about one bank */
267 /* temporarily mask (level sensitive) parent IRQ */
268 desc
->chip
->mask(irq
);
269 desc
->chip
->ack(irq
);
276 status
= __raw_readl(&g
->intstat
) & mask
;
279 __raw_writel(status
, &g
->intstat
);
283 /* now demux them to the right lowlevel handler */
284 n
= (int)get_irq_data(irq
);
288 generic_handle_irq(n
- 1);
292 desc
->chip
->unmask(irq
);
293 /* now it may re-trigger */
296 static int gpio_to_irq_banked(struct gpio_chip
*chip
, unsigned offset
)
298 struct davinci_gpio_controller
*d
= chip2controller(chip
);
300 if (d
->irq_base
>= 0)
301 return d
->irq_base
+ offset
;
306 static int gpio_to_irq_unbanked(struct gpio_chip
*chip
, unsigned offset
)
308 struct davinci_soc_info
*soc_info
= &davinci_soc_info
;
310 /* NOTE: we assume for now that only irqs in the first gpio_chip
311 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
313 if (offset
< soc_info
->gpio_unbanked
)
314 return soc_info
->gpio_irq
+ offset
;
319 static int gpio_irq_type_unbanked(unsigned irq
, unsigned trigger
)
321 struct davinci_gpio_regs __iomem
*g
= irq2regs(irq
);
322 u32 mask
= (u32
) get_irq_data(irq
);
324 if (trigger
& ~(IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
327 __raw_writel(mask
, (trigger
& IRQ_TYPE_EDGE_FALLING
)
328 ? &g
->set_falling
: &g
->clr_falling
);
329 __raw_writel(mask
, (trigger
& IRQ_TYPE_EDGE_RISING
)
330 ? &g
->set_rising
: &g
->clr_rising
);
336 * NOTE: for suspend/resume, probably best to make a platform_device with
337 * suspend_late/resume_resume calls hooking into results of the set_wake()
338 * calls ... so if no gpios are wakeup events the clock can be disabled,
339 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
340 * (dm6446) can be set appropriately for GPIOV33 pins.
343 static int __init
davinci_gpio_irq_setup(void)
345 unsigned gpio
, irq
, bank
;
348 unsigned ngpio
, bank_irq
;
349 struct davinci_soc_info
*soc_info
= &davinci_soc_info
;
350 struct davinci_gpio_regs __iomem
*g
;
352 ngpio
= soc_info
->gpio_num
;
354 bank_irq
= soc_info
->gpio_irq
;
356 printk(KERN_ERR
"Don't know first GPIO bank IRQ.\n");
360 clk
= clk_get(NULL
, "gpio");
362 printk(KERN_ERR
"Error %ld getting gpio clock?\n",
368 /* Arrange gpio_to_irq() support, handling either direct IRQs or
369 * banked IRQs. Having GPIOs in the first GPIO bank use direct
370 * IRQs, while the others use banked IRQs, would need some setup
371 * tweaks to recognize hardware which can do that.
373 for (gpio
= 0, bank
= 0; gpio
< ngpio
; bank
++, gpio
+= 32) {
374 chips
[bank
].chip
.to_irq
= gpio_to_irq_banked
;
375 chips
[bank
].irq_base
= soc_info
->gpio_unbanked
377 : (soc_info
->intc_irq_num
+ gpio
);
381 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
382 * controller only handling trigger modes. We currently assume no
383 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
385 if (soc_info
->gpio_unbanked
) {
386 static struct irq_chip gpio_irqchip_unbanked
;
388 /* pass "bank 0" GPIO IRQs to AINTC */
389 chips
[0].chip
.to_irq
= gpio_to_irq_unbanked
;
392 /* AINTC handles mask/unmask; GPIO handles triggering */
394 gpio_irqchip_unbanked
= *get_irq_desc_chip(irq_to_desc(irq
));
395 gpio_irqchip_unbanked
.name
= "GPIO-AINTC";
396 gpio_irqchip_unbanked
.set_type
= gpio_irq_type_unbanked
;
398 /* default trigger: both edges */
400 __raw_writel(~0, &g
->set_falling
);
401 __raw_writel(~0, &g
->set_rising
);
403 /* set the direct IRQs up to use that irqchip */
404 for (gpio
= 0; gpio
< soc_info
->gpio_unbanked
; gpio
++, irq
++) {
405 set_irq_chip(irq
, &gpio_irqchip_unbanked
);
406 set_irq_data(irq
, (void *) __gpio_mask(gpio
));
407 set_irq_chip_data(irq
, (__force
void *) g
);
408 irq_desc
[irq
].status
|= IRQ_TYPE_EDGE_BOTH
;
415 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
416 * then chain through our own handler.
418 for (gpio
= 0, irq
= gpio_to_irq(0), bank
= 0;
420 bank
++, bank_irq
++) {
423 /* disabled by default, enabled only as needed */
425 __raw_writel(~0, &g
->clr_falling
);
426 __raw_writel(~0, &g
->clr_rising
);
428 /* set up all irqs in this bank */
429 set_irq_chained_handler(bank_irq
, gpio_irq_handler
);
430 set_irq_chip_data(bank_irq
, (__force
void *) g
);
431 set_irq_data(bank_irq
, (void *) irq
);
433 for (i
= 0; i
< 16 && gpio
< ngpio
; i
++, irq
++, gpio
++) {
434 set_irq_chip(irq
, &gpio_irqchip
);
435 set_irq_chip_data(irq
, (__force
void *) g
);
436 set_irq_data(irq
, (void *) __gpio_mask(gpio
));
437 set_irq_handler(irq
, handle_simple_irq
);
438 set_irq_flags(irq
, IRQF_VALID
);
445 /* BINTEN -- per-bank interrupt enable. genirq would also let these
446 * bits be set/cleared dynamically.
448 __raw_writel(binten
, soc_info
->gpio_base
+ 0x08);
450 printk(KERN_INFO
"DaVinci: %d gpio irqs\n", irq
- gpio_to_irq(0));