arch/arm/mach-ep93xx/core.c

   1 /*
   2  * arch/arm/mach-ep93xx/core.c
   3  * Core routines for Cirrus EP93xx chips.
   4  *
   5  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
   6  *
   7  * Thanks go to Michael Burian and Ray Lehtiniemi for their key
   8  * role in the ep93xx linux community.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or (at
  13  * your option) any later version.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/sched.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/serial.h>
  23 #include <linux/tty.h>
  24 #include <linux/bitops.h>
  25 #include <linux/serial.h>
  26 #include <linux/serial_8250.h>
  27 #include <linux/serial_core.h>
  28 #include <linux/device.h>
  29 #include <linux/mm.h>
  30 #include <linux/time.h>
  31 #include <linux/timex.h>
  32 #include <linux/delay.h>
  33 #include <linux/termios.h>
  34 #include <linux/amba/bus.h>
  35 #include <linux/amba/serial.h>
  36
  37 #include <asm/types.h>
  38 #include <asm/setup.h>
  39 #include <asm/memory.h>
  40 #include <asm/hardware.h>
  41 #include <asm/irq.h>
  42 #include <asm/system.h>
  43 #include <asm/tlbflush.h>
  44 #include <asm/pgtable.h>
  45 #include <asm/io.h>
  46
  47 #include <asm/mach/map.h>
  48 #include <asm/mach/time.h>
  49 #include <asm/mach/irq.h>
  50 #include <asm/arch/gpio.h>
  51
  52 #include <asm/hardware/vic.h>
  53
  54
  55 /*************************************************************************
  56  * Static I/O mappings that are needed for all EP93xx platforms
  57  *************************************************************************/
  58 static struct map_desc ep93xx_io_desc[] __initdata = {
  59         {
  60                 .virtual        = EP93XX_AHB_VIRT_BASE,
  61                 .pfn            = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
  62                 .length         = EP93XX_AHB_SIZE,
  63                 .type           = MT_DEVICE,
  64         }, {
  65                 .virtual        = EP93XX_APB_VIRT_BASE,
  66                 .pfn            = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
  67                 .length         = EP93XX_APB_SIZE,
  68                 .type           = MT_DEVICE,
  69         },
  70 };
  71
  72 void __init ep93xx_map_io(void)
  73 {
  74         iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
  75 }
  76
  77
  78 /*************************************************************************
  79  * Timer handling for EP93xx
  80  *************************************************************************
  81  * The ep93xx has four internal timers.  Timers 1, 2 (both 16 bit) and
  82  * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
  83  * an interrupt on underflow.  Timer 4 (40 bit) counts down at 983.04 kHz,
  84  * is free-running, and can't generate interrupts.
  85  *
  86  * The 508 kHz timers are ideal for use for the timer interrupt, as the
  87  * most common values of HZ divide 508 kHz nicely.  We pick one of the 16
  88  * bit timers (timer 1) since we don't need more than 16 bits of reload
  89  * value as long as HZ >= 8.
  90  *
  91  * The higher clock rate of timer 4 makes it a better choice than the
  92  * other timers for use in gettimeoffset(), while the fact that it can't
  93  * generate interrupts means we don't have to worry about not being able
  94  * to use this timer for something else.  We also use timer 4 for keeping
  95  * track of lost jiffies.
  96  */
  97 static unsigned int last_jiffy_time;
  98
  99 #define TIMER4_TICKS_PER_JIFFY          ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
 100
 101 static int ep93xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 102 {
 103         write_seqlock(&xtime_lock);
 104
 105         __raw_writel(1, EP93XX_TIMER1_CLEAR);
 106         while ((signed long)
 107                 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
 108                                                 >= TIMER4_TICKS_PER_JIFFY) {
 109                 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
 110                 timer_tick(regs);
 111         }
 112
 113         write_sequnlock(&xtime_lock);
 114
 115         return IRQ_HANDLED;
 116 }
 117
 118 static struct irqaction ep93xx_timer_irq = {
 119         .name           = "ep93xx timer",
 120         .flags          = SA_INTERRUPT | SA_TIMER,
 121         .handler        = ep93xx_timer_interrupt,
 122 };
 123
 124 static void __init ep93xx_timer_init(void)
 125 {
 126         /* Enable periodic HZ timer.  */
 127         __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
 128         __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
 129         __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
 130
 131         /* Enable lost jiffy timer.  */
 132         __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
 133
 134         setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
 135 }
 136
 137 static unsigned long ep93xx_gettimeoffset(void)
 138 {
 139         int offset;
 140
 141         offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
 142
 143         /* Calculate (1000000 / 983040) * offset.  */
 144         return offset + (53 * offset / 3072);
 145 }
 146
 147 struct sys_timer ep93xx_timer = {
 148         .init           = ep93xx_timer_init,
 149         .offset         = ep93xx_gettimeoffset,
 150 };
 151
 152
 153 /*************************************************************************
 154  * GPIO handling for EP93xx
 155  *************************************************************************/
 156 static unsigned char gpio_int_enable[2];
 157 static unsigned char gpio_int_type1[2];
 158 static unsigned char gpio_int_type2[2];
 159
 160 static void update_gpio_ab_int_params(int port)
 161 {
 162         if (port == 0) {
 163                 __raw_writeb(0, EP93XX_GPIO_A_INT_ENABLE);
 164                 __raw_writeb(gpio_int_type2[0], EP93XX_GPIO_A_INT_TYPE2);
 165                 __raw_writeb(gpio_int_type1[0], EP93XX_GPIO_A_INT_TYPE1);
 166                 __raw_writeb(gpio_int_enable[0], EP93XX_GPIO_A_INT_ENABLE);
 167         } else if (port == 1) {
 168                 __raw_writeb(0, EP93XX_GPIO_B_INT_ENABLE);
 169                 __raw_writeb(gpio_int_type2[1], EP93XX_GPIO_B_INT_TYPE2);
 170                 __raw_writeb(gpio_int_type1[1], EP93XX_GPIO_B_INT_TYPE1);
 171                 __raw_writeb(gpio_int_enable[1], EP93XX_GPIO_B_INT_ENABLE);
 172         }
 173 }
 174
 175
 176 static unsigned char data_register_offset[8] = {
 177         0x00, 0x04, 0x08, 0x0c, 0x20, 0x30, 0x38, 0x40,
 178 };
 179
 180 static unsigned char data_direction_register_offset[8] = {
 181         0x10, 0x14, 0x18, 0x1c, 0x24, 0x34, 0x3c, 0x44,
 182 };
 183
 184 void gpio_line_config(int line, int direction)
 185 {
 186         unsigned int data_direction_register;
 187         unsigned long flags;
 188         unsigned char v;
 189
 190         data_direction_register =
 191                 EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]);
 192
 193         local_irq_save(flags);
 194         if (direction == GPIO_OUT) {
 195                 if (line >= 0 && line < 16) {
 196                         gpio_int_enable[line >> 3] &= ~(1 << (line & 7));
 197                         update_gpio_ab_int_params(line >> 3);
 198                 }
 199
 200                 v = __raw_readb(data_direction_register);
 201                 v |= 1 << (line & 7);
 202                 __raw_writeb(v, data_direction_register);
 203         } else if (direction == GPIO_IN) {
 204                 v = __raw_readb(data_direction_register);
 205                 v &= ~(1 << (line & 7));
 206                 __raw_writeb(v, data_direction_register);
 207         }
 208         local_irq_restore(flags);
 209 }
 210 EXPORT_SYMBOL(gpio_line_config);
 211
 212 int gpio_line_get(int line)
 213 {
 214         unsigned int data_register;
 215
 216         data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]);
 217
 218         return !!(__raw_readb(data_register) & (1 << (line & 7)));
 219 }
 220 EXPORT_SYMBOL(gpio_line_get);
 221
 222 void gpio_line_set(int line, int value)
 223 {
 224         unsigned int data_register;
 225         unsigned long flags;
 226         unsigned char v;
 227
 228         data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]);
 229
 230         local_irq_save(flags);
 231         if (value == EP93XX_GPIO_HIGH) {
 232                 v = __raw_readb(data_register);
 233                 v |= 1 << (line & 7);
 234                 __raw_writeb(v, data_register);
 235         } else if (value == EP93XX_GPIO_LOW) {
 236                 v = __raw_readb(data_register);
 237                 v &= ~(1 << (line & 7));
 238                 __raw_writeb(v, data_register);
 239         }
 240         local_irq_restore(flags);
 241 }
 242 EXPORT_SYMBOL(gpio_line_set);
 243
 244
 245 /*************************************************************************
 246  * EP93xx IRQ handling
 247  *************************************************************************/
 248 static void ep93xx_gpio_ab_irq_handler(unsigned int irq,
 249                 struct irqdesc *desc, struct pt_regs *regs)
 250 {
 251         unsigned char status;
 252         int i;
 253
 254         status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
 255         for (i = 0; i < 8; i++) {
 256                 if (status & (1 << i)) {
 257                         desc = irq_desc + IRQ_EP93XX_GPIO(0) + i;
 258                         desc_handle_irq(IRQ_EP93XX_GPIO(0) + i, desc, regs);
 259                 }
 260         }
 261
 262         status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
 263         for (i = 0; i < 8; i++) {
 264                 if (status & (1 << i)) {
 265                         desc = irq_desc + IRQ_EP93XX_GPIO(8) + i;
 266                         desc_handle_irq(IRQ_EP93XX_GPIO(8) + i, desc, regs);
 267                 }
 268         }
 269 }
 270
 271 static void ep93xx_gpio_ab_irq_mask_ack(unsigned int irq)
 272 {
 273         int line = irq - IRQ_EP93XX_GPIO(0);
 274         int port = line >> 3;
 275
 276         gpio_int_enable[port] &= ~(1 << (line & 7));
 277         update_gpio_ab_int_params(port);
 278
 279         if (line >> 3) {
 280                 __raw_writel(1 << (line & 7), EP93XX_GPIO_B_INT_ACK);
 281         } else {
 282                 __raw_writel(1 << (line & 7), EP93XX_GPIO_A_INT_ACK);
 283         }
 284 }
 285
 286 static void ep93xx_gpio_ab_irq_mask(unsigned int irq)
 287 {
 288         int line = irq - IRQ_EP93XX_GPIO(0);
 289         int port = line >> 3;
 290
 291         gpio_int_enable[port] &= ~(1 << (line & 7));
 292         update_gpio_ab_int_params(port);
 293 }
 294
 295 static void ep93xx_gpio_ab_irq_unmask(unsigned int irq)
 296 {
 297         int line = irq - IRQ_EP93XX_GPIO(0);
 298         int port = line >> 3;
 299
 300         gpio_int_enable[port] |= 1 << (line & 7);
 301         update_gpio_ab_int_params(port);
 302 }
 303
 304
 305 /*
 306  * gpio_int_type1 controls whether the interrupt is level (0) or
 307  * edge (1) triggered, while gpio_int_type2 controls whether it
 308  * triggers on low/falling (0) or high/rising (1).
 309  */
 310 static int ep93xx_gpio_ab_irq_type(unsigned int irq, unsigned int type)
 311 {
 312         int port;
 313         int line;
 314
 315         line = irq - IRQ_EP93XX_GPIO(0);
 316         gpio_line_config(line, GPIO_IN);
 317
 318         port = line >> 3;
 319         line &= 7;
 320
 321         if (type & IRQT_RISING) {
 322                 gpio_int_type1[port] |= 1 << line;
 323                 gpio_int_type2[port] |= 1 << line;
 324         } else if (type & IRQT_FALLING) {
 325                 gpio_int_type1[port] |= 1 << line;
 326                 gpio_int_type2[port] &= ~(1 << line);
 327         } else if (type & IRQT_HIGH) {
 328                 gpio_int_type1[port] &= ~(1 << line);
 329                 gpio_int_type2[port] |= 1 << line;
 330         } else if (type & IRQT_LOW) {
 331                 gpio_int_type1[port] &= ~(1 << line);
 332                 gpio_int_type2[port] &= ~(1 << line);
 333         }
 334         update_gpio_ab_int_params(port);
 335
 336         return 0;
 337 }
 338
 339 static struct irqchip ep93xx_gpio_ab_irq_chip = {
 340         .ack            = ep93xx_gpio_ab_irq_mask_ack,
 341         .mask           = ep93xx_gpio_ab_irq_mask,
 342         .unmask         = ep93xx_gpio_ab_irq_unmask,
 343         .set_type       = ep93xx_gpio_ab_irq_type,
 344 };
 345
 346
 347 void __init ep93xx_init_irq(void)
 348 {
 349         int irq;
 350
 351         vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
 352         vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
 353
 354         for (irq = IRQ_EP93XX_GPIO(0) ; irq <= IRQ_EP93XX_GPIO(15); irq++) {
 355                 set_irq_chip(irq, &ep93xx_gpio_ab_irq_chip);
 356                 set_irq_handler(irq, do_level_IRQ);
 357                 set_irq_flags(irq, IRQF_VALID);
 358         }
 359         set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
 360 }
 361
 362
 363 /*************************************************************************
 364  * EP93xx peripheral handling
 365  *************************************************************************/
 366 #define EP93XX_UART_MCR_OFFSET          (0x0100)
 367
 368 static void ep93xx_uart_set_mctrl(struct amba_device *dev,
 369                                   void __iomem *base, unsigned int mctrl)
 370 {
 371         unsigned int mcr;
 372
 373         mcr = 0;
 374         if (!(mctrl & TIOCM_RTS))
 375                 mcr |= 2;
 376         if (!(mctrl & TIOCM_DTR))
 377                 mcr |= 1;
 378
 379         __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
 380 }
 381
 382 static struct amba_pl010_data ep93xx_uart_data = {
 383         .set_mctrl      = ep93xx_uart_set_mctrl,
 384 };
 385
 386 static struct amba_device uart1_device = {
 387         .dev            = {
 388                 .bus_id         = "apb:uart1",
 389                 .platform_data  = &ep93xx_uart_data,
 390         },
 391         .res            = {
 392                 .start  = EP93XX_UART1_PHYS_BASE,
 393                 .end    = EP93XX_UART1_PHYS_BASE + 0x0fff,
 394                 .flags  = IORESOURCE_MEM,
 395         },
 396         .irq            = { IRQ_EP93XX_UART1, NO_IRQ },
 397         .periphid       = 0x00041010,
 398 };
 399
 400 static struct amba_device uart2_device = {
 401         .dev            = {
 402                 .bus_id         = "apb:uart2",
 403                 .platform_data  = &ep93xx_uart_data,
 404         },
 405         .res            = {
 406                 .start  = EP93XX_UART2_PHYS_BASE,
 407                 .end    = EP93XX_UART2_PHYS_BASE + 0x0fff,
 408                 .flags  = IORESOURCE_MEM,
 409         },
 410         .irq            = { IRQ_EP93XX_UART2, NO_IRQ },
 411         .periphid       = 0x00041010,
 412 };
 413
 414 static struct amba_device uart3_device = {
 415         .dev            = {
 416                 .bus_id         = "apb:uart3",
 417                 .platform_data  = &ep93xx_uart_data,
 418         },
 419         .res            = {
 420                 .start  = EP93XX_UART3_PHYS_BASE,
 421                 .end    = EP93XX_UART3_PHYS_BASE + 0x0fff,
 422                 .flags  = IORESOURCE_MEM,
 423         },
 424         .irq            = { IRQ_EP93XX_UART3, NO_IRQ },
 425         .periphid       = 0x00041010,
 426 };
 427
 428
 429 static struct platform_device ep93xx_rtc_device = {
 430        .name           = "ep93xx-rtc",
 431        .id             = -1,
 432        .num_resources  = 0,
 433 };
 434
 435
 436 void __init ep93xx_init_devices(void)
 437 {
 438         unsigned int v;
 439
 440         /*
 441          * Disallow access to MaverickCrunch initially.
 442          */
 443         v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
 444         v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
 445         __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
 446         __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
 447
 448         amba_device_register(&uart1_device, &iomem_resource);
 449         amba_device_register(&uart2_device, &iomem_resource);
 450         amba_device_register(&uart3_device, &iomem_resource);
 451
 452         platform_device_register(&ep93xx_rtc_device);
 453 }