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ARM: EXYNOS: fix cycle count for periodic mode of clock event timers
[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-exynos / common.c
1 /*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for EXYNOS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/io.h>
16 #include <linux/device.h>
17 #include <linux/gpio.h>
18 #include <linux/sched.h>
19 #include <linux/serial_core.h>
20 #include <linux/of.h>
21 #include <linux/of_irq.h>
22
23 #include <asm/proc-fns.h>
24 #include <asm/exception.h>
25 #include <asm/hardware/cache-l2x0.h>
26 #include <asm/hardware/gic.h>
27 #include <asm/mach/map.h>
28 #include <asm/mach/irq.h>
29 #include <asm/cacheflush.h>
30
31 #include <mach/regs-irq.h>
32 #include <mach/regs-pmu.h>
33 #include <mach/regs-gpio.h>
34 #include <mach/pmu.h>
35
36 #include <plat/cpu.h>
37 #include <plat/clock.h>
38 #include <plat/devs.h>
39 #include <plat/pm.h>
40 #include <plat/sdhci.h>
41 #include <plat/gpio-cfg.h>
42 #include <plat/adc-core.h>
43 #include <plat/fb-core.h>
44 #include <plat/fimc-core.h>
45 #include <plat/iic-core.h>
46 #include <plat/tv-core.h>
47 #include <plat/regs-serial.h>
48
49 #include "common.h"
50 #define L2_AUX_VAL 0x7C470001
51 #define L2_AUX_MASK 0xC200ffff
52
53 static const char name_exynos4210[] = "EXYNOS4210";
54 static const char name_exynos4212[] = "EXYNOS4212";
55 static const char name_exynos4412[] = "EXYNOS4412";
56
57 static struct cpu_table cpu_ids[] __initdata = {
58 {
59 .idcode = EXYNOS4210_CPU_ID,
60 .idmask = EXYNOS4_CPU_MASK,
61 .map_io = exynos4_map_io,
62 .init_clocks = exynos4_init_clocks,
63 .init_uarts = exynos4_init_uarts,
64 .init = exynos_init,
65 .name = name_exynos4210,
66 }, {
67 .idcode = EXYNOS4212_CPU_ID,
68 .idmask = EXYNOS4_CPU_MASK,
69 .map_io = exynos4_map_io,
70 .init_clocks = exynos4_init_clocks,
71 .init_uarts = exynos4_init_uarts,
72 .init = exynos_init,
73 .name = name_exynos4212,
74 }, {
75 .idcode = EXYNOS4412_CPU_ID,
76 .idmask = EXYNOS4_CPU_MASK,
77 .map_io = exynos4_map_io,
78 .init_clocks = exynos4_init_clocks,
79 .init_uarts = exynos4_init_uarts,
80 .init = exynos_init,
81 .name = name_exynos4412,
82 },
83 };
84
85 /* Initial IO mappings */
86
87 static struct map_desc exynos_iodesc[] __initdata = {
88 {
89 .virtual = (unsigned long)S5P_VA_CHIPID,
90 .pfn = __phys_to_pfn(EXYNOS4_PA_CHIPID),
91 .length = SZ_4K,
92 .type = MT_DEVICE,
93 }, {
94 .virtual = (unsigned long)S3C_VA_SYS,
95 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
96 .length = SZ_64K,
97 .type = MT_DEVICE,
98 }, {
99 .virtual = (unsigned long)S3C_VA_TIMER,
100 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
101 .length = SZ_16K,
102 .type = MT_DEVICE,
103 }, {
104 .virtual = (unsigned long)S3C_VA_WATCHDOG,
105 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
106 .length = SZ_4K,
107 .type = MT_DEVICE,
108 }, {
109 .virtual = (unsigned long)S5P_VA_SROMC,
110 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
111 .length = SZ_4K,
112 .type = MT_DEVICE,
113 }, {
114 .virtual = (unsigned long)S5P_VA_SYSTIMER,
115 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
116 .length = SZ_4K,
117 .type = MT_DEVICE,
118 }, {
119 .virtual = (unsigned long)S5P_VA_PMU,
120 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
121 .length = SZ_64K,
122 .type = MT_DEVICE,
123 }, {
124 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
125 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
126 .length = SZ_4K,
127 .type = MT_DEVICE,
128 }, {
129 .virtual = (unsigned long)S5P_VA_GIC_CPU,
130 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
131 .length = SZ_64K,
132 .type = MT_DEVICE,
133 }, {
134 .virtual = (unsigned long)S5P_VA_GIC_DIST,
135 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
136 .length = SZ_64K,
137 .type = MT_DEVICE,
138 }, {
139 .virtual = (unsigned long)S3C_VA_UART,
140 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
141 .length = SZ_512K,
142 .type = MT_DEVICE,
143 },
144 };
145
146 static struct map_desc exynos4_iodesc[] __initdata = {
147 {
148 .virtual = (unsigned long)S5P_VA_CMU,
149 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
150 .length = SZ_128K,
151 .type = MT_DEVICE,
152 }, {
153 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
154 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
155 .length = SZ_8K,
156 .type = MT_DEVICE,
157 }, {
158 .virtual = (unsigned long)S5P_VA_L2CC,
159 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
160 .length = SZ_4K,
161 .type = MT_DEVICE,
162 }, {
163 .virtual = (unsigned long)S5P_VA_GPIO1,
164 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
165 .length = SZ_4K,
166 .type = MT_DEVICE,
167 }, {
168 .virtual = (unsigned long)S5P_VA_GPIO2,
169 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
170 .length = SZ_4K,
171 .type = MT_DEVICE,
172 }, {
173 .virtual = (unsigned long)S5P_VA_GPIO3,
174 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
175 .length = SZ_256,
176 .type = MT_DEVICE,
177 }, {
178 .virtual = (unsigned long)S5P_VA_DMC0,
179 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
180 .length = SZ_64K,
181 .type = MT_DEVICE,
182 }, {
183 .virtual = (unsigned long)S5P_VA_DMC1,
184 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
185 .length = SZ_64K,
186 .type = MT_DEVICE,
187 }, {
188 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
189 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
190 .length = SZ_4K,
191 .type = MT_DEVICE,
192 },
193 };
194
195 static struct map_desc exynos4_iodesc0[] __initdata = {
196 {
197 .virtual = (unsigned long)S5P_VA_SYSRAM,
198 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
199 .length = SZ_4K,
200 .type = MT_DEVICE,
201 },
202 };
203
204 static struct map_desc exynos4_iodesc1[] __initdata = {
205 {
206 .virtual = (unsigned long)S5P_VA_SYSRAM,
207 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
208 .length = SZ_4K,
209 .type = MT_DEVICE,
210 },
211 };
212
213 static void exynos_idle(void)
214 {
215 if (!need_resched())
216 cpu_do_idle();
217
218 local_irq_enable();
219 }
220
221 void exynos4_restart(char mode, const char *cmd)
222 {
223 __raw_writel(0x1, S5P_SWRESET);
224 }
225
226 /*
227 * exynos_map_io
228 *
229 * register the standard cpu IO areas
230 */
231
232 void __init exynos_init_io(struct map_desc *mach_desc, int size)
233 {
234 /* initialize the io descriptors we need for initialization */
235 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
236 if (mach_desc)
237 iotable_init(mach_desc, size);
238
239 /* detect cpu id and rev. */
240 s5p_init_cpu(S5P_VA_CHIPID);
241
242 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
243 }
244
245 void __init exynos4_map_io(void)
246 {
247 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
248
249 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
250 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
251 else
252 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
253
254 /* initialize device information early */
255 exynos4_default_sdhci0();
256 exynos4_default_sdhci1();
257 exynos4_default_sdhci2();
258 exynos4_default_sdhci3();
259
260 s3c_adc_setname("samsung-adc-v3");
261
262 s3c_fimc_setname(0, "exynos4-fimc");
263 s3c_fimc_setname(1, "exynos4-fimc");
264 s3c_fimc_setname(2, "exynos4-fimc");
265 s3c_fimc_setname(3, "exynos4-fimc");
266
267 /* The I2C bus controllers are directly compatible with s3c2440 */
268 s3c_i2c0_setname("s3c2440-i2c");
269 s3c_i2c1_setname("s3c2440-i2c");
270 s3c_i2c2_setname("s3c2440-i2c");
271
272 s5p_fb_setname(0, "exynos4-fb");
273 s5p_hdmi_setname("exynos4-hdmi");
274 }
275
276 void __init exynos4_init_clocks(int xtal)
277 {
278 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
279
280 s3c24xx_register_baseclocks(xtal);
281 s5p_register_clocks(xtal);
282
283 if (soc_is_exynos4210())
284 exynos4210_register_clocks();
285 else if (soc_is_exynos4212() || soc_is_exynos4412())
286 exynos4212_register_clocks();
287
288 exynos4_register_clocks();
289 exynos4_setup_clocks();
290 }
291
292 #define COMBINER_ENABLE_SET 0x0
293 #define COMBINER_ENABLE_CLEAR 0x4
294 #define COMBINER_INT_STATUS 0xC
295
296 static DEFINE_SPINLOCK(irq_controller_lock);
297
298 struct combiner_chip_data {
299 unsigned int irq_offset;
300 unsigned int irq_mask;
301 void __iomem *base;
302 };
303
304 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
305
306 static inline void __iomem *combiner_base(struct irq_data *data)
307 {
308 struct combiner_chip_data *combiner_data =
309 irq_data_get_irq_chip_data(data);
310
311 return combiner_data->base;
312 }
313
314 static void combiner_mask_irq(struct irq_data *data)
315 {
316 u32 mask = 1 << (data->irq % 32);
317
318 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
319 }
320
321 static void combiner_unmask_irq(struct irq_data *data)
322 {
323 u32 mask = 1 << (data->irq % 32);
324
325 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
326 }
327
328 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
329 {
330 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
331 struct irq_chip *chip = irq_get_chip(irq);
332 unsigned int cascade_irq, combiner_irq;
333 unsigned long status;
334
335 chained_irq_enter(chip, desc);
336
337 spin_lock(&irq_controller_lock);
338 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
339 spin_unlock(&irq_controller_lock);
340 status &= chip_data->irq_mask;
341
342 if (status == 0)
343 goto out;
344
345 combiner_irq = __ffs(status);
346
347 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
348 if (unlikely(cascade_irq >= NR_IRQS))
349 do_bad_IRQ(cascade_irq, desc);
350 else
351 generic_handle_irq(cascade_irq);
352
353 out:
354 chained_irq_exit(chip, desc);
355 }
356
357 static struct irq_chip combiner_chip = {
358 .name = "COMBINER",
359 .irq_mask = combiner_mask_irq,
360 .irq_unmask = combiner_unmask_irq,
361 };
362
363 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
364 {
365 if (combiner_nr >= MAX_COMBINER_NR)
366 BUG();
367 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
368 BUG();
369 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
370 }
371
372 static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
373 unsigned int irq_start)
374 {
375 unsigned int i;
376
377 if (combiner_nr >= MAX_COMBINER_NR)
378 BUG();
379
380 combiner_data[combiner_nr].base = base;
381 combiner_data[combiner_nr].irq_offset = irq_start;
382 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
383
384 /* Disable all interrupts */
385
386 __raw_writel(combiner_data[combiner_nr].irq_mask,
387 base + COMBINER_ENABLE_CLEAR);
388
389 /* Setup the Linux IRQ subsystem */
390
391 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
392 + MAX_IRQ_IN_COMBINER; i++) {
393 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
394 irq_set_chip_data(i, &combiner_data[combiner_nr]);
395 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
396 }
397 }
398
399 #ifdef CONFIG_OF
400 static const struct of_device_id exynos4_dt_irq_match[] = {
401 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
402 {},
403 };
404 #endif
405
406 void __init exynos4_init_irq(void)
407 {
408 int irq;
409 unsigned int gic_bank_offset;
410
411 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
412
413 if (!of_have_populated_dt())
414 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
415 #ifdef CONFIG_OF
416 else
417 of_irq_init(exynos4_dt_irq_match);
418 #endif
419
420 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
421
422 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
423 COMBINER_IRQ(irq, 0));
424 combiner_cascade_irq(irq, IRQ_SPI(irq));
425 }
426
427 /*
428 * The parameters of s5p_init_irq() are for VIC init.
429 * Theses parameters should be NULL and 0 because EXYNOS4
430 * uses GIC instead of VIC.
431 */
432 s5p_init_irq(NULL, 0);
433 }
434
435 struct bus_type exynos4_subsys = {
436 .name = "exynos4-core",
437 .dev_name = "exynos4-core",
438 };
439
440 static struct device exynos4_dev = {
441 .bus = &exynos4_subsys,
442 };
443
444 static int __init exynos4_core_init(void)
445 {
446 return subsys_system_register(&exynos4_subsys, NULL);
447 }
448 core_initcall(exynos4_core_init);
449
450 #ifdef CONFIG_CACHE_L2X0
451 static int __init exynos4_l2x0_cache_init(void)
452 {
453 int ret;
454 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
455 if (!ret) {
456 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
457 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
458 return 0;
459 }
460
461 if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
462 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
463 /* TAG, Data Latency Control: 2 cycles */
464 l2x0_saved_regs.tag_latency = 0x110;
465
466 if (soc_is_exynos4212() || soc_is_exynos4412())
467 l2x0_saved_regs.data_latency = 0x120;
468 else
469 l2x0_saved_regs.data_latency = 0x110;
470
471 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
472 l2x0_saved_regs.pwr_ctrl =
473 (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
474
475 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
476
477 __raw_writel(l2x0_saved_regs.tag_latency,
478 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
479 __raw_writel(l2x0_saved_regs.data_latency,
480 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
481
482 /* L2X0 Prefetch Control */
483 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
484 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
485
486 /* L2X0 Power Control */
487 __raw_writel(l2x0_saved_regs.pwr_ctrl,
488 S5P_VA_L2CC + L2X0_POWER_CTRL);
489
490 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
491 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
492 }
493
494 l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
495 return 0;
496 }
497
498 early_initcall(exynos4_l2x0_cache_init);
499 #endif
500
501 int __init exynos_init(void)
502 {
503 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
504
505 /* set idle function */
506 pm_idle = exynos_idle;
507
508 return device_register(&exynos4_dev);
509 }
510
511 /* uart registration process */
512
513 void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
514 {
515 struct s3c2410_uartcfg *tcfg = cfg;
516 u32 ucnt;
517
518 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
519 tcfg->has_fracval = 1;
520
521 s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
522 }
523
524 static DEFINE_SPINLOCK(eint_lock);
525
526 static unsigned int eint0_15_data[16];
527
528 static unsigned int exynos4_get_irq_nr(unsigned int number)
529 {
530 u32 ret = 0;
531
532 switch (number) {
533 case 0 ... 3:
534 ret = (number + IRQ_EINT0);
535 break;
536 case 4 ... 7:
537 ret = (number + (IRQ_EINT4 - 4));
538 break;
539 case 8 ... 15:
540 ret = (number + (IRQ_EINT8 - 8));
541 break;
542 default:
543 printk(KERN_ERR "number available : %d\n", number);
544 }
545
546 return ret;
547 }
548
549 static inline void exynos4_irq_eint_mask(struct irq_data *data)
550 {
551 u32 mask;
552
553 spin_lock(&eint_lock);
554 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
555 mask |= eint_irq_to_bit(data->irq);
556 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
557 spin_unlock(&eint_lock);
558 }
559
560 static void exynos4_irq_eint_unmask(struct irq_data *data)
561 {
562 u32 mask;
563
564 spin_lock(&eint_lock);
565 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
566 mask &= ~(eint_irq_to_bit(data->irq));
567 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
568 spin_unlock(&eint_lock);
569 }
570
571 static inline void exynos4_irq_eint_ack(struct irq_data *data)
572 {
573 __raw_writel(eint_irq_to_bit(data->irq),
574 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
575 }
576
577 static void exynos4_irq_eint_maskack(struct irq_data *data)
578 {
579 exynos4_irq_eint_mask(data);
580 exynos4_irq_eint_ack(data);
581 }
582
583 static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
584 {
585 int offs = EINT_OFFSET(data->irq);
586 int shift;
587 u32 ctrl, mask;
588 u32 newvalue = 0;
589
590 switch (type) {
591 case IRQ_TYPE_EDGE_RISING:
592 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
593 break;
594
595 case IRQ_TYPE_EDGE_FALLING:
596 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
597 break;
598
599 case IRQ_TYPE_EDGE_BOTH:
600 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
601 break;
602
603 case IRQ_TYPE_LEVEL_LOW:
604 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
605 break;
606
607 case IRQ_TYPE_LEVEL_HIGH:
608 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
609 break;
610
611 default:
612 printk(KERN_ERR "No such irq type %d", type);
613 return -EINVAL;
614 }
615
616 shift = (offs & 0x7) * 4;
617 mask = 0x7 << shift;
618
619 spin_lock(&eint_lock);
620 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
621 ctrl &= ~mask;
622 ctrl |= newvalue << shift;
623 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
624 spin_unlock(&eint_lock);
625
626 switch (offs) {
627 case 0 ... 7:
628 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
629 break;
630 case 8 ... 15:
631 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
632 break;
633 case 16 ... 23:
634 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
635 break;
636 case 24 ... 31:
637 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
638 break;
639 default:
640 printk(KERN_ERR "No such irq number %d", offs);
641 }
642
643 return 0;
644 }
645
646 static struct irq_chip exynos4_irq_eint = {
647 .name = "exynos4-eint",
648 .irq_mask = exynos4_irq_eint_mask,
649 .irq_unmask = exynos4_irq_eint_unmask,
650 .irq_mask_ack = exynos4_irq_eint_maskack,
651 .irq_ack = exynos4_irq_eint_ack,
652 .irq_set_type = exynos4_irq_eint_set_type,
653 #ifdef CONFIG_PM
654 .irq_set_wake = s3c_irqext_wake,
655 #endif
656 };
657
658 /*
659 * exynos4_irq_demux_eint
660 *
661 * This function demuxes the IRQ from from EINTs 16 to 31.
662 * It is designed to be inlined into the specific handler
663 * s5p_irq_demux_eintX_Y.
664 *
665 * Each EINT pend/mask registers handle eight of them.
666 */
667 static inline void exynos4_irq_demux_eint(unsigned int start)
668 {
669 unsigned int irq;
670
671 u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
672 u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
673
674 status &= ~mask;
675 status &= 0xff;
676
677 while (status) {
678 irq = fls(status) - 1;
679 generic_handle_irq(irq + start);
680 status &= ~(1 << irq);
681 }
682 }
683
684 static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
685 {
686 struct irq_chip *chip = irq_get_chip(irq);
687 chained_irq_enter(chip, desc);
688 exynos4_irq_demux_eint(IRQ_EINT(16));
689 exynos4_irq_demux_eint(IRQ_EINT(24));
690 chained_irq_exit(chip, desc);
691 }
692
693 static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
694 {
695 u32 *irq_data = irq_get_handler_data(irq);
696 struct irq_chip *chip = irq_get_chip(irq);
697
698 chained_irq_enter(chip, desc);
699 chip->irq_mask(&desc->irq_data);
700
701 if (chip->irq_ack)
702 chip->irq_ack(&desc->irq_data);
703
704 generic_handle_irq(*irq_data);
705
706 chip->irq_unmask(&desc->irq_data);
707 chained_irq_exit(chip, desc);
708 }
709
710 int __init exynos4_init_irq_eint(void)
711 {
712 int irq;
713
714 for (irq = 0 ; irq <= 31 ; irq++) {
715 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
716 handle_level_irq);
717 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
718 }
719
720 irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
721
722 for (irq = 0 ; irq <= 15 ; irq++) {
723 eint0_15_data[irq] = IRQ_EINT(irq);
724
725 irq_set_handler_data(exynos4_get_irq_nr(irq),
726 &eint0_15_data[irq]);
727 irq_set_chained_handler(exynos4_get_irq_nr(irq),
728 exynos4_irq_eint0_15);
729 }
730
731 return 0;
732 }
733 arch_initcall(exynos4_init_irq_eint);
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