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Merge tag 'fbdev-updates-for-3.5' of git://github.com/schandinat/linux-2.6
[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-exynos / mach-universal_c210.c
1 /* linux/arch/arm/mach-exynos4/mach-universal_c210.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10 #include <linux/platform_device.h>
11 #include <linux/serial_core.h>
12 #include <linux/input.h>
13 #include <linux/i2c.h>
14 #include <linux/gpio_keys.h>
15 #include <linux/gpio.h>
16 #include <linux/interrupt.h>
17 #include <linux/fb.h>
18 #include <linux/mfd/max8998.h>
19 #include <linux/regulator/machine.h>
20 #include <linux/regulator/fixed.h>
21 #include <linux/regulator/max8952.h>
22 #include <linux/mmc/host.h>
23 #include <linux/i2c-gpio.h>
24 #include <linux/i2c/mcs.h>
25 #include <linux/i2c/atmel_mxt_ts.h>
26 #include <linux/platform_data/s3c-hsotg.h>
27 #include <drm/exynos_drm.h>
28
29 #include <asm/mach/arch.h>
30 #include <asm/hardware/gic.h>
31 #include <asm/mach-types.h>
32
33 #include <plat/regs-serial.h>
34 #include <plat/clock.h>
35 #include <plat/cpu.h>
36 #include <plat/devs.h>
37 #include <plat/iic.h>
38 #include <plat/gpio-cfg.h>
39 #include <plat/fb.h>
40 #include <plat/mfc.h>
41 #include <plat/sdhci.h>
42 #include <plat/pd.h>
43 #include <plat/regs-fb-v4.h>
44 #include <plat/fimc-core.h>
45 #include <plat/s5p-time.h>
46 #include <plat/camport.h>
47 #include <plat/mipi_csis.h>
48
49 #include <mach/map.h>
50
51 #include <media/v4l2-mediabus.h>
52 #include <media/s5p_fimc.h>
53 #include <media/m5mols.h>
54 #include <media/s5k6aa.h>
55
56 #include "common.h"
57
58 /* Following are default values for UCON, ULCON and UFCON UART registers */
59 #define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
60 S3C2410_UCON_RXILEVEL | \
61 S3C2410_UCON_TXIRQMODE | \
62 S3C2410_UCON_RXIRQMODE | \
63 S3C2410_UCON_RXFIFO_TOI | \
64 S3C2443_UCON_RXERR_IRQEN)
65
66 #define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
67
68 #define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
69 S5PV210_UFCON_TXTRIG256 | \
70 S5PV210_UFCON_RXTRIG256)
71
72 static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
73 [0] = {
74 .hwport = 0,
75 .ucon = UNIVERSAL_UCON_DEFAULT,
76 .ulcon = UNIVERSAL_ULCON_DEFAULT,
77 .ufcon = UNIVERSAL_UFCON_DEFAULT,
78 },
79 [1] = {
80 .hwport = 1,
81 .ucon = UNIVERSAL_UCON_DEFAULT,
82 .ulcon = UNIVERSAL_ULCON_DEFAULT,
83 .ufcon = UNIVERSAL_UFCON_DEFAULT,
84 },
85 [2] = {
86 .hwport = 2,
87 .ucon = UNIVERSAL_UCON_DEFAULT,
88 .ulcon = UNIVERSAL_ULCON_DEFAULT,
89 .ufcon = UNIVERSAL_UFCON_DEFAULT,
90 },
91 [3] = {
92 .hwport = 3,
93 .ucon = UNIVERSAL_UCON_DEFAULT,
94 .ulcon = UNIVERSAL_ULCON_DEFAULT,
95 .ufcon = UNIVERSAL_UFCON_DEFAULT,
96 },
97 };
98
99 static struct regulator_consumer_supply max8952_consumer =
100 REGULATOR_SUPPLY("vdd_arm", NULL);
101
102 static struct max8952_platform_data universal_max8952_pdata __initdata = {
103 .gpio_vid0 = EXYNOS4_GPX0(3),
104 .gpio_vid1 = EXYNOS4_GPX0(4),
105 .gpio_en = -1, /* Not controllable, set "Always High" */
106 .default_mode = 0, /* vid0 = 0, vid1 = 0 */
107 .dvs_mode = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
108 .sync_freq = 0, /* default: fastest */
109 .ramp_speed = 0, /* default: fastest */
110
111 .reg_data = {
112 .constraints = {
113 .name = "VARM_1.2V",
114 .min_uV = 770000,
115 .max_uV = 1400000,
116 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
117 .always_on = 1,
118 .boot_on = 1,
119 },
120 .num_consumer_supplies = 1,
121 .consumer_supplies = &max8952_consumer,
122 },
123 };
124
125 static struct regulator_consumer_supply lp3974_buck1_consumer =
126 REGULATOR_SUPPLY("vdd_int", NULL);
127
128 static struct regulator_consumer_supply lp3974_buck2_consumer =
129 REGULATOR_SUPPLY("vddg3d", NULL);
130
131 static struct regulator_consumer_supply lp3974_buck3_consumer[] = {
132 REGULATOR_SUPPLY("vdet", "s5p-sdo"),
133 REGULATOR_SUPPLY("vdd_reg", "0-003c"),
134 };
135
136 static struct regulator_init_data lp3974_buck1_data = {
137 .constraints = {
138 .name = "VINT_1.1V",
139 .min_uV = 750000,
140 .max_uV = 1500000,
141 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
142 REGULATOR_CHANGE_STATUS,
143 .boot_on = 1,
144 .state_mem = {
145 .disabled = 1,
146 },
147 },
148 .num_consumer_supplies = 1,
149 .consumer_supplies = &lp3974_buck1_consumer,
150 };
151
152 static struct regulator_init_data lp3974_buck2_data = {
153 .constraints = {
154 .name = "VG3D_1.1V",
155 .min_uV = 750000,
156 .max_uV = 1500000,
157 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
158 REGULATOR_CHANGE_STATUS,
159 .boot_on = 1,
160 .state_mem = {
161 .disabled = 1,
162 },
163 },
164 .num_consumer_supplies = 1,
165 .consumer_supplies = &lp3974_buck2_consumer,
166 };
167
168 static struct regulator_init_data lp3974_buck3_data = {
169 .constraints = {
170 .name = "VCC_1.8V",
171 .min_uV = 1800000,
172 .max_uV = 1800000,
173 .apply_uV = 1,
174 .always_on = 1,
175 .state_mem = {
176 .enabled = 1,
177 },
178 },
179 .num_consumer_supplies = ARRAY_SIZE(lp3974_buck3_consumer),
180 .consumer_supplies = lp3974_buck3_consumer,
181 };
182
183 static struct regulator_init_data lp3974_buck4_data = {
184 .constraints = {
185 .name = "VMEM_1.2V",
186 .min_uV = 1200000,
187 .max_uV = 1200000,
188 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
189 .apply_uV = 1,
190 .state_mem = {
191 .disabled = 1,
192 },
193 },
194 };
195
196 static struct regulator_init_data lp3974_ldo2_data = {
197 .constraints = {
198 .name = "VALIVE_1.2V",
199 .min_uV = 1200000,
200 .max_uV = 1200000,
201 .apply_uV = 1,
202 .always_on = 1,
203 .state_mem = {
204 .enabled = 1,
205 },
206 },
207 };
208
209 static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
210 REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
211 REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
212 REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
213 REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"),
214 };
215
216 static struct regulator_init_data lp3974_ldo3_data = {
217 .constraints = {
218 .name = "VUSB+MIPI_1.1V",
219 .min_uV = 1100000,
220 .max_uV = 1100000,
221 .apply_uV = 1,
222 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
223 .state_mem = {
224 .disabled = 1,
225 },
226 },
227 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer),
228 .consumer_supplies = lp3974_ldo3_consumer,
229 };
230
231 static struct regulator_consumer_supply lp3974_ldo4_consumer[] = {
232 REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
233 };
234
235 static struct regulator_init_data lp3974_ldo4_data = {
236 .constraints = {
237 .name = "VADC_3.3V",
238 .min_uV = 3300000,
239 .max_uV = 3300000,
240 .apply_uV = 1,
241 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
242 .state_mem = {
243 .disabled = 1,
244 },
245 },
246 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer),
247 .consumer_supplies = lp3974_ldo4_consumer,
248 };
249
250 static struct regulator_init_data lp3974_ldo5_data = {
251 .constraints = {
252 .name = "VTF_2.8V",
253 .min_uV = 2800000,
254 .max_uV = 2800000,
255 .apply_uV = 1,
256 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
257 .state_mem = {
258 .disabled = 1,
259 },
260 },
261 };
262
263 static struct regulator_init_data lp3974_ldo6_data = {
264 .constraints = {
265 .name = "LDO6",
266 .min_uV = 2000000,
267 .max_uV = 2000000,
268 .apply_uV = 1,
269 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
270 .state_mem = {
271 .disabled = 1,
272 },
273 },
274 };
275
276 static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
277 REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"),
278 };
279
280 static struct regulator_init_data lp3974_ldo7_data = {
281 .constraints = {
282 .name = "VLCD+VMIPI_1.8V",
283 .min_uV = 1800000,
284 .max_uV = 1800000,
285 .apply_uV = 1,
286 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
287 .state_mem = {
288 .disabled = 1,
289 },
290 },
291 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo7_consumer),
292 .consumer_supplies = lp3974_ldo7_consumer,
293 };
294
295 static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
296 REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"),
297 REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
298 };
299
300 static struct regulator_init_data lp3974_ldo8_data = {
301 .constraints = {
302 .name = "VUSB+VDAC_3.3V",
303 .min_uV = 3300000,
304 .max_uV = 3300000,
305 .apply_uV = 1,
306 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
307 .state_mem = {
308 .disabled = 1,
309 },
310 },
311 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer),
312 .consumer_supplies = lp3974_ldo8_consumer,
313 };
314
315 static struct regulator_consumer_supply lp3974_ldo9_consumer =
316 REGULATOR_SUPPLY("vddio", "0-003c");
317
318 static struct regulator_init_data lp3974_ldo9_data = {
319 .constraints = {
320 .name = "VCC_2.8V",
321 .min_uV = 2800000,
322 .max_uV = 2800000,
323 .apply_uV = 1,
324 .always_on = 1,
325 .state_mem = {
326 .enabled = 1,
327 },
328 },
329 .num_consumer_supplies = 1,
330 .consumer_supplies = &lp3974_ldo9_consumer,
331 };
332
333 static struct regulator_init_data lp3974_ldo10_data = {
334 .constraints = {
335 .name = "VPLL_1.1V",
336 .min_uV = 1100000,
337 .max_uV = 1100000,
338 .boot_on = 1,
339 .apply_uV = 1,
340 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
341 .state_mem = {
342 .disabled = 1,
343 },
344 },
345 };
346
347 static struct regulator_consumer_supply lp3974_ldo11_consumer =
348 REGULATOR_SUPPLY("dig_28", "0-001f");
349
350 static struct regulator_init_data lp3974_ldo11_data = {
351 .constraints = {
352 .name = "CAM_AF_3.3V",
353 .min_uV = 3300000,
354 .max_uV = 3300000,
355 .apply_uV = 1,
356 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
357 .state_mem = {
358 .disabled = 1,
359 },
360 },
361 .num_consumer_supplies = 1,
362 .consumer_supplies = &lp3974_ldo11_consumer,
363 };
364
365 static struct regulator_init_data lp3974_ldo12_data = {
366 .constraints = {
367 .name = "PS_2.8V",
368 .min_uV = 2800000,
369 .max_uV = 2800000,
370 .apply_uV = 1,
371 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
372 .state_mem = {
373 .disabled = 1,
374 },
375 },
376 };
377
378 static struct regulator_init_data lp3974_ldo13_data = {
379 .constraints = {
380 .name = "VHIC_1.2V",
381 .min_uV = 1200000,
382 .max_uV = 1200000,
383 .apply_uV = 1,
384 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
385 .state_mem = {
386 .disabled = 1,
387 },
388 },
389 };
390
391 static struct regulator_consumer_supply lp3974_ldo14_consumer =
392 REGULATOR_SUPPLY("dig_18", "0-001f");
393
394 static struct regulator_init_data lp3974_ldo14_data = {
395 .constraints = {
396 .name = "CAM_I_HOST_1.8V",
397 .min_uV = 1800000,
398 .max_uV = 1800000,
399 .apply_uV = 1,
400 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
401 .state_mem = {
402 .disabled = 1,
403 },
404 },
405 .num_consumer_supplies = 1,
406 .consumer_supplies = &lp3974_ldo14_consumer,
407 };
408
409
410 static struct regulator_consumer_supply lp3974_ldo15_consumer =
411 REGULATOR_SUPPLY("dig_12", "0-001f");
412
413 static struct regulator_init_data lp3974_ldo15_data = {
414 .constraints = {
415 .name = "CAM_S_DIG+FM33_CORE_1.2V",
416 .min_uV = 1200000,
417 .max_uV = 1200000,
418 .apply_uV = 1,
419 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
420 .state_mem = {
421 .disabled = 1,
422 },
423 },
424 .num_consumer_supplies = 1,
425 .consumer_supplies = &lp3974_ldo15_consumer,
426 };
427
428 static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
429 REGULATOR_SUPPLY("vdda", "0-003c"),
430 REGULATOR_SUPPLY("a_sensor", "0-001f"),
431 };
432
433 static struct regulator_init_data lp3974_ldo16_data = {
434 .constraints = {
435 .name = "CAM_S_ANA_2.8V",
436 .min_uV = 2800000,
437 .max_uV = 2800000,
438 .apply_uV = 1,
439 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
440 .state_mem = {
441 .disabled = 1,
442 },
443 },
444 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo16_consumer),
445 .consumer_supplies = lp3974_ldo16_consumer,
446 };
447
448 static struct regulator_init_data lp3974_ldo17_data = {
449 .constraints = {
450 .name = "VCC_3.0V_LCD",
451 .min_uV = 3000000,
452 .max_uV = 3000000,
453 .apply_uV = 1,
454 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
455 .boot_on = 1,
456 .state_mem = {
457 .disabled = 1,
458 },
459 },
460 };
461
462 static struct regulator_init_data lp3974_32khz_ap_data = {
463 .constraints = {
464 .name = "32KHz AP",
465 .always_on = 1,
466 .state_mem = {
467 .enabled = 1,
468 },
469 },
470 };
471
472 static struct regulator_init_data lp3974_32khz_cp_data = {
473 .constraints = {
474 .name = "32KHz CP",
475 .state_mem = {
476 .disabled = 1,
477 },
478 },
479 };
480
481 static struct regulator_init_data lp3974_vichg_data = {
482 .constraints = {
483 .name = "VICHG",
484 .state_mem = {
485 .disabled = 1,
486 },
487 },
488 };
489
490 static struct regulator_init_data lp3974_esafeout1_data = {
491 .constraints = {
492 .name = "SAFEOUT1",
493 .min_uV = 4800000,
494 .max_uV = 4800000,
495 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
496 .always_on = 1,
497 .state_mem = {
498 .enabled = 1,
499 },
500 },
501 };
502
503 static struct regulator_init_data lp3974_esafeout2_data = {
504 .constraints = {
505 .name = "SAFEOUT2",
506 .boot_on = 1,
507 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
508 .state_mem = {
509 .enabled = 1,
510 },
511 },
512 };
513
514 static struct max8998_regulator_data lp3974_regulators[] = {
515 { MAX8998_LDO2, &lp3974_ldo2_data },
516 { MAX8998_LDO3, &lp3974_ldo3_data },
517 { MAX8998_LDO4, &lp3974_ldo4_data },
518 { MAX8998_LDO5, &lp3974_ldo5_data },
519 { MAX8998_LDO6, &lp3974_ldo6_data },
520 { MAX8998_LDO7, &lp3974_ldo7_data },
521 { MAX8998_LDO8, &lp3974_ldo8_data },
522 { MAX8998_LDO9, &lp3974_ldo9_data },
523 { MAX8998_LDO10, &lp3974_ldo10_data },
524 { MAX8998_LDO11, &lp3974_ldo11_data },
525 { MAX8998_LDO12, &lp3974_ldo12_data },
526 { MAX8998_LDO13, &lp3974_ldo13_data },
527 { MAX8998_LDO14, &lp3974_ldo14_data },
528 { MAX8998_LDO15, &lp3974_ldo15_data },
529 { MAX8998_LDO16, &lp3974_ldo16_data },
530 { MAX8998_LDO17, &lp3974_ldo17_data },
531 { MAX8998_BUCK1, &lp3974_buck1_data },
532 { MAX8998_BUCK2, &lp3974_buck2_data },
533 { MAX8998_BUCK3, &lp3974_buck3_data },
534 { MAX8998_BUCK4, &lp3974_buck4_data },
535 { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },
536 { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },
537 { MAX8998_ENVICHG, &lp3974_vichg_data },
538 { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },
539 { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },
540 };
541
542 static struct max8998_platform_data universal_lp3974_pdata = {
543 .num_regulators = ARRAY_SIZE(lp3974_regulators),
544 .regulators = lp3974_regulators,
545 .buck1_voltage1 = 1100000, /* INT */
546 .buck1_voltage2 = 1000000,
547 .buck1_voltage3 = 1100000,
548 .buck1_voltage4 = 1000000,
549 .buck1_set1 = EXYNOS4_GPX0(5),
550 .buck1_set2 = EXYNOS4_GPX0(6),
551 .buck2_voltage1 = 1200000, /* G3D */
552 .buck2_voltage2 = 1100000,
553 .buck1_default_idx = 0,
554 .buck2_set3 = EXYNOS4_GPE2(0),
555 .buck2_default_idx = 0,
556 .wakeup = true,
557 };
558
559
560 enum fixed_regulator_id {
561 FIXED_REG_ID_MMC0,
562 FIXED_REG_ID_HDMI_5V,
563 FIXED_REG_ID_CAM_S_IF,
564 FIXED_REG_ID_CAM_I_CORE,
565 FIXED_REG_ID_CAM_VT_DIO,
566 };
567
568 static struct regulator_consumer_supply hdmi_fixed_consumer =
569 REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi");
570
571 static struct regulator_init_data hdmi_fixed_voltage_init_data = {
572 .constraints = {
573 .name = "HDMI_5V",
574 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
575 },
576 .num_consumer_supplies = 1,
577 .consumer_supplies = &hdmi_fixed_consumer,
578 };
579
580 static struct fixed_voltage_config hdmi_fixed_voltage_config = {
581 .supply_name = "HDMI_EN1",
582 .microvolts = 5000000,
583 .gpio = EXYNOS4_GPE0(1),
584 .enable_high = true,
585 .init_data = &hdmi_fixed_voltage_init_data,
586 };
587
588 static struct platform_device hdmi_fixed_voltage = {
589 .name = "reg-fixed-voltage",
590 .id = FIXED_REG_ID_HDMI_5V,
591 .dev = {
592 .platform_data = &hdmi_fixed_voltage_config,
593 },
594 };
595
596 /* GPIO I2C 5 (PMIC) */
597 static struct i2c_board_info i2c5_devs[] __initdata = {
598 {
599 I2C_BOARD_INFO("max8952", 0xC0 >> 1),
600 .platform_data = &universal_max8952_pdata,
601 }, {
602 I2C_BOARD_INFO("lp3974", 0xCC >> 1),
603 .platform_data = &universal_lp3974_pdata,
604 },
605 };
606
607 /* I2C3 (TSP) */
608 static struct mxt_platform_data qt602240_platform_data = {
609 .x_line = 19,
610 .y_line = 11,
611 .x_size = 800,
612 .y_size = 480,
613 .blen = 0x11,
614 .threshold = 0x28,
615 .voltage = 2800000, /* 2.8V */
616 .orient = MXT_DIAGONAL,
617 .irqflags = IRQF_TRIGGER_FALLING,
618 };
619
620 static struct i2c_board_info i2c3_devs[] __initdata = {
621 {
622 I2C_BOARD_INFO("qt602240_ts", 0x4a),
623 .platform_data = &qt602240_platform_data,
624 },
625 };
626
627 static void __init universal_tsp_init(void)
628 {
629 int gpio;
630
631 /* TSP_LDO_ON: XMDMADDR_11 */
632 gpio = EXYNOS4_GPE2(3);
633 gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
634 gpio_export(gpio, 0);
635
636 /* TSP_INT: XMDMADDR_7 */
637 gpio = EXYNOS4_GPE1(7);
638 gpio_request(gpio, "TSP_INT");
639
640 s5p_register_gpio_interrupt(gpio);
641 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
642 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
643 i2c3_devs[0].irq = gpio_to_irq(gpio);
644 }
645
646
647 /* GPIO I2C 12 (3 Touchkey) */
648 static uint32_t touchkey_keymap[] = {
649 /* MCS_KEY_MAP(value, keycode) */
650 MCS_KEY_MAP(0, KEY_MENU), /* KEY_SEND */
651 MCS_KEY_MAP(1, KEY_BACK), /* KEY_END */
652 };
653
654 static struct mcs_platform_data touchkey_data = {
655 .keymap = touchkey_keymap,
656 .keymap_size = ARRAY_SIZE(touchkey_keymap),
657 .key_maxval = 2,
658 };
659
660 /* GPIO I2C 3_TOUCH 2.8V */
661 #define I2C_GPIO_BUS_12 12
662 static struct i2c_gpio_platform_data i2c_gpio12_data = {
663 .sda_pin = EXYNOS4_GPE4(0), /* XMDMDATA_8 */
664 .scl_pin = EXYNOS4_GPE4(1), /* XMDMDATA_9 */
665 };
666
667 static struct platform_device i2c_gpio12 = {
668 .name = "i2c-gpio",
669 .id = I2C_GPIO_BUS_12,
670 .dev = {
671 .platform_data = &i2c_gpio12_data,
672 },
673 };
674
675 static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
676 {
677 I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
678 .platform_data = &touchkey_data,
679 },
680 };
681
682 static void __init universal_touchkey_init(void)
683 {
684 int gpio;
685
686 gpio = EXYNOS4_GPE3(7); /* XMDMDATA_7 */
687 gpio_request(gpio, "3_TOUCH_INT");
688 s5p_register_gpio_interrupt(gpio);
689 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
690 i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
691
692 gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */
693 gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "3_TOUCH_EN");
694 }
695
696 static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
697 .frequency = 300 * 1000,
698 .sda_delay = 200,
699 };
700
701 /* GPIO KEYS */
702 static struct gpio_keys_button universal_gpio_keys_tables[] = {
703 {
704 .code = KEY_VOLUMEUP,
705 .gpio = EXYNOS4_GPX2(0), /* XEINT16 */
706 .desc = "gpio-keys: KEY_VOLUMEUP",
707 .type = EV_KEY,
708 .active_low = 1,
709 .debounce_interval = 1,
710 }, {
711 .code = KEY_VOLUMEDOWN,
712 .gpio = EXYNOS4_GPX2(1), /* XEINT17 */
713 .desc = "gpio-keys: KEY_VOLUMEDOWN",
714 .type = EV_KEY,
715 .active_low = 1,
716 .debounce_interval = 1,
717 }, {
718 .code = KEY_CONFIG,
719 .gpio = EXYNOS4_GPX2(2), /* XEINT18 */
720 .desc = "gpio-keys: KEY_CONFIG",
721 .type = EV_KEY,
722 .active_low = 1,
723 .debounce_interval = 1,
724 }, {
725 .code = KEY_CAMERA,
726 .gpio = EXYNOS4_GPX2(3), /* XEINT19 */
727 .desc = "gpio-keys: KEY_CAMERA",
728 .type = EV_KEY,
729 .active_low = 1,
730 .debounce_interval = 1,
731 }, {
732 .code = KEY_OK,
733 .gpio = EXYNOS4_GPX3(5), /* XEINT29 */
734 .desc = "gpio-keys: KEY_OK",
735 .type = EV_KEY,
736 .active_low = 1,
737 .debounce_interval = 1,
738 },
739 };
740
741 static struct gpio_keys_platform_data universal_gpio_keys_data = {
742 .buttons = universal_gpio_keys_tables,
743 .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
744 };
745
746 static struct platform_device universal_gpio_keys = {
747 .name = "gpio-keys",
748 .dev = {
749 .platform_data = &universal_gpio_keys_data,
750 },
751 };
752
753 /* eMMC */
754 static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
755 .max_width = 8,
756 .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
757 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
758 .host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
759 .cd_type = S3C_SDHCI_CD_PERMANENT,
760 };
761
762 static struct regulator_consumer_supply mmc0_supplies[] = {
763 REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
764 };
765
766 static struct regulator_init_data mmc0_fixed_voltage_init_data = {
767 .constraints = {
768 .name = "VMEM_VDD_2.8V",
769 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
770 },
771 .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
772 .consumer_supplies = mmc0_supplies,
773 };
774
775 static struct fixed_voltage_config mmc0_fixed_voltage_config = {
776 .supply_name = "MASSMEMORY_EN",
777 .microvolts = 2800000,
778 .gpio = EXYNOS4_GPE1(3),
779 .enable_high = true,
780 .init_data = &mmc0_fixed_voltage_init_data,
781 };
782
783 static struct platform_device mmc0_fixed_voltage = {
784 .name = "reg-fixed-voltage",
785 .id = FIXED_REG_ID_MMC0,
786 .dev = {
787 .platform_data = &mmc0_fixed_voltage_config,
788 },
789 };
790
791 /* SD */
792 static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
793 .max_width = 4,
794 .host_caps = MMC_CAP_4_BIT_DATA |
795 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
796 .ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */
797 .ext_cd_gpio_invert = 1,
798 .cd_type = S3C_SDHCI_CD_GPIO,
799 };
800
801 /* WiFi */
802 static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
803 .max_width = 4,
804 .host_caps = MMC_CAP_4_BIT_DATA |
805 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
806 .cd_type = S3C_SDHCI_CD_EXTERNAL,
807 };
808
809 static void __init universal_sdhci_init(void)
810 {
811 s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
812 s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
813 s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
814 }
815
816 /* I2C1 */
817 static struct i2c_board_info i2c1_devs[] __initdata = {
818 /* Gyro, To be updated */
819 };
820
821 #ifdef CONFIG_DRM_EXYNOS
822 static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
823 .panel = {
824 .timing = {
825 .left_margin = 16,
826 .right_margin = 16,
827 .upper_margin = 2,
828 .lower_margin = 28,
829 .hsync_len = 2,
830 .vsync_len = 1,
831 .xres = 480,
832 .yres = 800,
833 .refresh = 55,
834 },
835 },
836 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
837 VIDCON0_CLKSEL_LCD,
838 .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
839 | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
840 .default_win = 3,
841 .bpp = 32,
842 };
843 #else
844 /* Frame Buffer */
845 static struct s3c_fb_pd_win universal_fb_win0 = {
846 .max_bpp = 32,
847 .default_bpp = 16,
848 .xres = 480,
849 .yres = 800,
850 .virtual_x = 480,
851 .virtual_y = 2 * 800,
852 };
853
854 static struct fb_videomode universal_lcd_timing = {
855 .left_margin = 16,
856 .right_margin = 16,
857 .upper_margin = 2,
858 .lower_margin = 28,
859 .hsync_len = 2,
860 .vsync_len = 1,
861 .xres = 480,
862 .yres = 800,
863 .refresh = 55,
864 };
865
866 static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
867 .win[0] = &universal_fb_win0,
868 .vtiming = &universal_lcd_timing,
869 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
870 VIDCON0_CLKSEL_LCD,
871 .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
872 | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
873 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
874 };
875 #endif
876
877 static struct regulator_consumer_supply cam_vt_dio_supply =
878 REGULATOR_SUPPLY("vdd_core", "0-003c");
879
880 static struct regulator_init_data cam_vt_dio_reg_init_data = {
881 .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
882 .num_consumer_supplies = 1,
883 .consumer_supplies = &cam_vt_dio_supply,
884 };
885
886 static struct fixed_voltage_config cam_vt_dio_fixed_voltage_cfg = {
887 .supply_name = "CAM_VT_D_IO",
888 .microvolts = 2800000,
889 .gpio = EXYNOS4_GPE2(1), /* CAM_PWR_EN2 */
890 .enable_high = 1,
891 .init_data = &cam_vt_dio_reg_init_data,
892 };
893
894 static struct platform_device cam_vt_dio_fixed_reg_dev = {
895 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_DIO,
896 .dev = { .platform_data = &cam_vt_dio_fixed_voltage_cfg },
897 };
898
899 static struct regulator_consumer_supply cam_i_core_supply =
900 REGULATOR_SUPPLY("core", "0-001f");
901
902 static struct regulator_init_data cam_i_core_reg_init_data = {
903 .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
904 .num_consumer_supplies = 1,
905 .consumer_supplies = &cam_i_core_supply,
906 };
907
908 static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
909 .supply_name = "CAM_I_CORE_1.2V",
910 .microvolts = 1200000,
911 .gpio = EXYNOS4_GPE2(2), /* CAM_8M_CORE_EN */
912 .enable_high = 1,
913 .init_data = &cam_i_core_reg_init_data,
914 };
915
916 static struct platform_device cam_i_core_fixed_reg_dev = {
917 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE,
918 .dev = { .platform_data = &cam_i_core_fixed_voltage_cfg },
919 };
920
921 static struct regulator_consumer_supply cam_s_if_supply =
922 REGULATOR_SUPPLY("d_sensor", "0-001f");
923
924 static struct regulator_init_data cam_s_if_reg_init_data = {
925 .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
926 .num_consumer_supplies = 1,
927 .consumer_supplies = &cam_s_if_supply,
928 };
929
930 static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
931 .supply_name = "CAM_S_IF_1.8V",
932 .microvolts = 1800000,
933 .gpio = EXYNOS4_GPE3(0), /* CAM_PWR_EN1 */
934 .enable_high = 1,
935 .init_data = &cam_s_if_reg_init_data,
936 };
937
938 static struct platform_device cam_s_if_fixed_reg_dev = {
939 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF,
940 .dev = { .platform_data = &cam_s_if_fixed_voltage_cfg },
941 };
942
943 static struct s5p_platform_mipi_csis mipi_csis_platdata = {
944 .clk_rate = 166000000UL,
945 .lanes = 2,
946 .alignment = 32,
947 .hs_settle = 12,
948 .phy_enable = s5p_csis_phy_enable,
949 };
950
951 #define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3)
952 #define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5) /* XEINT_13 */
953 #define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5)
954 #define GPIO_CAM_VGA_NRST EXYNOS4_GPE4(7)
955 #define GPIO_CAM_VGA_NSTBY EXYNOS4_GPE4(6)
956
957 static int s5k6aa_set_power(int on)
958 {
959 gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
960 return 0;
961 }
962
963 static struct s5k6aa_platform_data s5k6aa_platdata = {
964 .mclk_frequency = 21600000UL,
965 .gpio_reset = { GPIO_CAM_VGA_NRST, 0 },
966 .gpio_stby = { GPIO_CAM_VGA_NSTBY, 0 },
967 .bus_type = V4L2_MBUS_PARALLEL,
968 .horiz_flip = 1,
969 .set_power = s5k6aa_set_power,
970 };
971
972 static struct i2c_board_info s5k6aa_board_info = {
973 I2C_BOARD_INFO("S5K6AA", 0x3C),
974 .platform_data = &s5k6aa_platdata,
975 };
976
977 static int m5mols_set_power(struct device *dev, int on)
978 {
979 gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on);
980 gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
981 return 0;
982 }
983
984 static struct m5mols_platform_data m5mols_platdata = {
985 .gpio_reset = GPIO_CAM_MEGA_nRST,
986 .reset_polarity = 0,
987 .set_power = m5mols_set_power,
988 };
989
990 static struct i2c_board_info m5mols_board_info = {
991 I2C_BOARD_INFO("M5MOLS", 0x1F),
992 .platform_data = &m5mols_platdata,
993 };
994
995 static struct s5p_fimc_isp_info universal_camera_sensors[] = {
996 {
997 .mux_id = 0,
998 .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
999 V4L2_MBUS_VSYNC_ACTIVE_LOW,
1000 .bus_type = FIMC_ITU_601,
1001 .board_info = &s5k6aa_board_info,
1002 .i2c_bus_num = 0,
1003 .clk_frequency = 24000000UL,
1004 }, {
1005 .mux_id = 0,
1006 .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
1007 V4L2_MBUS_VSYNC_ACTIVE_LOW,
1008 .bus_type = FIMC_MIPI_CSI2,
1009 .board_info = &m5mols_board_info,
1010 .i2c_bus_num = 0,
1011 .clk_frequency = 24000000UL,
1012 .csi_data_align = 32,
1013 },
1014 };
1015
1016 static struct s5p_platform_fimc fimc_md_platdata = {
1017 .isp_info = universal_camera_sensors,
1018 .num_clients = ARRAY_SIZE(universal_camera_sensors),
1019 };
1020
1021 static struct gpio universal_camera_gpios[] = {
1022 { GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" },
1023 { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW, "CAM_LVL_EN2" },
1024 { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" },
1025 { GPIO_CAM_MEGA_nRST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
1026 { GPIO_CAM_VGA_NRST, GPIOF_OUT_INIT_LOW, "CAM_VGA_NRST" },
1027 { GPIO_CAM_VGA_NSTBY, GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" },
1028 };
1029
1030 /* USB OTG */
1031 static struct s3c_hsotg_plat universal_hsotg_pdata;
1032
1033 static void __init universal_camera_init(void)
1034 {
1035 s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
1036 &s5p_device_mipi_csis0);
1037 s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata),
1038 &s5p_device_fimc_md);
1039
1040 if (gpio_request_array(universal_camera_gpios,
1041 ARRAY_SIZE(universal_camera_gpios))) {
1042 pr_err("%s: GPIO request failed\n", __func__);
1043 return;
1044 }
1045
1046 if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf)))
1047 m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT);
1048 else
1049 pr_err("Failed to configure 8M_ISP_INT GPIO\n");
1050
1051 /* Free GPIOs controlled directly by the sensor drivers. */
1052 gpio_free(GPIO_CAM_MEGA_nRST);
1053 gpio_free(GPIO_CAM_8M_ISP_INT);
1054 gpio_free(GPIO_CAM_VGA_NRST);
1055 gpio_free(GPIO_CAM_VGA_NSTBY);
1056
1057 if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
1058 pr_err("Camera port A setup failed\n");
1059 }
1060
1061 static struct platform_device *universal_devices[] __initdata = {
1062 /* Samsung Platform Devices */
1063 &s5p_device_mipi_csis0,
1064 &s5p_device_fimc0,
1065 &s5p_device_fimc1,
1066 &s5p_device_fimc2,
1067 &s5p_device_fimc3,
1068 &s5p_device_g2d,
1069 &mmc0_fixed_voltage,
1070 &s3c_device_hsmmc0,
1071 &s3c_device_hsmmc2,
1072 &s3c_device_hsmmc3,
1073 &s3c_device_i2c0,
1074 &s3c_device_i2c3,
1075 &s3c_device_i2c5,
1076 &s5p_device_i2c_hdmiphy,
1077 &hdmi_fixed_voltage,
1078 &s5p_device_hdmi,
1079 &s5p_device_sdo,
1080 &s5p_device_mixer,
1081
1082 /* Universal Devices */
1083 &i2c_gpio12,
1084 &universal_gpio_keys,
1085 &s5p_device_onenand,
1086 &s5p_device_fimd0,
1087 &s5p_device_jpeg,
1088 #ifdef CONFIG_DRM_EXYNOS
1089 &exynos_device_drm,
1090 #endif
1091 &s3c_device_usb_hsotg,
1092 &s5p_device_mfc,
1093 &s5p_device_mfc_l,
1094 &s5p_device_mfc_r,
1095 &cam_vt_dio_fixed_reg_dev,
1096 &cam_i_core_fixed_reg_dev,
1097 &cam_s_if_fixed_reg_dev,
1098 &s5p_device_fimc_md,
1099 };
1100
1101 static void __init universal_map_io(void)
1102 {
1103 clk_xusbxti.rate = 24000000;
1104 exynos_init_io(NULL, 0);
1105 s3c24xx_init_clocks(24000000);
1106 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
1107 s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
1108 }
1109
1110 static void s5p_tv_setup(void)
1111 {
1112 /* direct HPD to HDMI chip */
1113 gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
1114 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
1115 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
1116 }
1117
1118 static void __init universal_reserve(void)
1119 {
1120 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
1121 }
1122
1123 static void __init universal_machine_init(void)
1124 {
1125 universal_sdhci_init();
1126 s5p_tv_setup();
1127
1128 s3c_i2c0_set_platdata(&universal_i2c0_platdata);
1129 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
1130
1131 universal_tsp_init();
1132 s3c_i2c3_set_platdata(NULL);
1133 i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
1134
1135 s3c_i2c5_set_platdata(NULL);
1136 s5p_i2c_hdmiphy_set_platdata(NULL);
1137 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
1138
1139 #ifdef CONFIG_DRM_EXYNOS
1140 s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
1141 exynos4_fimd0_gpio_setup_24bpp();
1142 #else
1143 s5p_fimd0_set_platdata(&universal_lcd_pdata);
1144 #endif
1145
1146 universal_touchkey_init();
1147 i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
1148 ARRAY_SIZE(i2c_gpio12_devs));
1149
1150 s3c_hsotg_set_platdata(&universal_hsotg_pdata);
1151 universal_camera_init();
1152
1153 /* Last */
1154 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
1155 }
1156
1157 MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
1158 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
1159 .atag_offset = 0x100,
1160 .init_irq = exynos4_init_irq,
1161 .map_io = universal_map_io,
1162 .handle_irq = gic_handle_irq,
1163 .init_machine = universal_machine_init,
1164 .init_late = exynos_init_late,
1165 .timer = &s5p_timer,
1166 .reserve = &universal_reserve,
1167 .restart = exynos4_restart,
1168 MACHINE_END
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