arch/arm/mach-exynos/platsmp.c

   1  /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
   6  *
   7  *  Copyright (C) 2002 ARM Ltd.
   8  *  All Rights Reserved
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #include <linux/init.h>
  16 #include <linux/errno.h>
  17 #include <linux/delay.h>
  18 #include <linux/device.h>
  19 #include <linux/jiffies.h>
  20 #include <linux/smp.h>
  21 #include <linux/io.h>
  22 #include <linux/of_address.h>
  23
  24 #include <asm/cacheflush.h>
  25 #include <asm/smp_plat.h>
  26 #include <asm/smp_scu.h>
  27 #include <asm/firmware.h>
  28
  29 #include "common.h"
  30 #include "regs-pmu.h"
  31
  32 extern void exynos4_secondary_startup(void);
  33
  34 /**
  35  * exynos_core_power_down : power down the specified cpu
  36  * @cpu : the cpu to power down
  37  *
  38  * Power down the specified cpu. The sequence must be finished by a
  39  * call to cpu_do_idle()
  40  *
  41  */
  42 void exynos_cpu_power_down(int cpu)
  43 {
  44         __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
  45 }
  46
  47 /**
  48  * exynos_cpu_power_up : power up the specified cpu
  49  * @cpu : the cpu to power up
  50  *
  51  * Power up the specified cpu
  52  */
  53 void exynos_cpu_power_up(int cpu)
  54 {
  55         __raw_writel(S5P_CORE_LOCAL_PWR_EN,
  56                      EXYNOS_ARM_CORE_CONFIGURATION(cpu));
  57 }
  58
  59 /**
  60  * exynos_cpu_power_state : returns the power state of the cpu
  61  * @cpu : the cpu to retrieve the power state from
  62  *
  63  */
  64 int exynos_cpu_power_state(int cpu)
  65 {
  66         return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
  67                         S5P_CORE_LOCAL_PWR_EN);
  68 }
  69
  70 /**
  71  * exynos_cluster_power_down : power down the specified cluster
  72  * @cluster : the cluster to power down
  73  */
  74 void exynos_cluster_power_down(int cluster)
  75 {
  76         __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
  77 }
  78
  79 /**
  80  * exynos_cluster_power_up : power up the specified cluster
  81  * @cluster : the cluster to power up
  82  */
  83 void exynos_cluster_power_up(int cluster)
  84 {
  85         __raw_writel(S5P_CORE_LOCAL_PWR_EN,
  86                      EXYNOS_COMMON_CONFIGURATION(cluster));
  87 }
  88
  89 /**
  90  * exynos_cluster_power_state : returns the power state of the cluster
  91  * @cluster : the cluster to retrieve the power state from
  92  *
  93  */
  94 int exynos_cluster_power_state(int cluster)
  95 {
  96         return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
  97                         S5P_CORE_LOCAL_PWR_EN);
  98 }
  99
 100 static inline void __iomem *cpu_boot_reg_base(void)
 101 {
 102         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
 103                 return S5P_INFORM5;
 104         return sysram_base_addr;
 105 }
 106
 107 static inline void __iomem *cpu_boot_reg(int cpu)
 108 {
 109         void __iomem *boot_reg;
 110
 111         boot_reg = cpu_boot_reg_base();
 112         if (!boot_reg)
 113                 return ERR_PTR(-ENODEV);
 114         if (soc_is_exynos4412())
 115                 boot_reg += 4*cpu;
 116         else if (soc_is_exynos5420() || soc_is_exynos5800())
 117                 boot_reg += 4;
 118         return boot_reg;
 119 }
 120
 121 /*
 122  * Write pen_release in a way that is guaranteed to be visible to all
 123  * observers, irrespective of whether they're taking part in coherency
 124  * or not.  This is necessary for the hotplug code to work reliably.
 125  */
 126 static void write_pen_release(int val)
 127 {
 128         pen_release = val;
 129         smp_wmb();
 130         sync_cache_w(&pen_release);
 131 }
 132
 133 static void __iomem *scu_base_addr(void)
 134 {
 135         return (void __iomem *)(S5P_VA_SCU);
 136 }
 137
 138 static DEFINE_SPINLOCK(boot_lock);
 139
 140 static void exynos_secondary_init(unsigned int cpu)
 141 {
 142         /*
 143          * let the primary processor know we're out of the
 144          * pen, then head off into the C entry point
 145          */
 146         write_pen_release(-1);
 147
 148         /*
 149          * Synchronise with the boot thread.
 150          */
 151         spin_lock(&boot_lock);
 152         spin_unlock(&boot_lock);
 153 }
 154
 155 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
 156 {
 157         unsigned long timeout;
 158         u32 mpidr = cpu_logical_map(cpu);
 159         u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 160         int ret = -ENOSYS;
 161
 162         /*
 163          * Set synchronisation state between this boot processor
 164          * and the secondary one
 165          */
 166         spin_lock(&boot_lock);
 167
 168         /*
 169          * The secondary processor is waiting to be released from
 170          * the holding pen - release it, then wait for it to flag
 171          * that it has been released by resetting pen_release.
 172          *
 173          * Note that "pen_release" is the hardware CPU core ID, whereas
 174          * "cpu" is Linux's internal ID.
 175          */
 176         write_pen_release(core_id);
 177
 178         if (!exynos_cpu_power_state(core_id)) {
 179                 exynos_cpu_power_up(core_id);
 180                 timeout = 10;
 181
 182                 /* wait max 10 ms until cpu1 is on */
 183                 while (exynos_cpu_power_state(core_id)
 184                        != S5P_CORE_LOCAL_PWR_EN) {
 185                         if (timeout-- == 0)
 186                                 break;
 187
 188                         mdelay(1);
 189                 }
 190
 191                 if (timeout == 0) {
 192                         printk(KERN_ERR "cpu1 power enable failed");
 193                         spin_unlock(&boot_lock);
 194                         return -ETIMEDOUT;
 195                 }
 196         }
 197         /*
 198          * Send the secondary CPU a soft interrupt, thereby causing
 199          * the boot monitor to read the system wide flags register,
 200          * and branch to the address found there.
 201          */
 202
 203         timeout = jiffies + (1 * HZ);
 204         while (time_before(jiffies, timeout)) {
 205                 unsigned long boot_addr;
 206
 207                 smp_rmb();
 208
 209                 boot_addr = virt_to_phys(exynos4_secondary_startup);
 210
 211                 /*
 212                  * Try to set boot address using firmware first
 213                  * and fall back to boot register if it fails.
 214                  */
 215                 ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
 216                 if (ret && ret != -ENOSYS)
 217                         goto fail;
 218                 if (ret == -ENOSYS) {
 219                         void __iomem *boot_reg = cpu_boot_reg(core_id);
 220
 221                         if (IS_ERR(boot_reg)) {
 222                                 ret = PTR_ERR(boot_reg);
 223                                 goto fail;
 224                         }
 225                         __raw_writel(boot_addr, cpu_boot_reg(core_id));
 226                 }
 227
 228                 call_firmware_op(cpu_boot, core_id);
 229
 230                 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
 231
 232                 if (pen_release == -1)
 233                         break;
 234
 235                 udelay(10);
 236         }
 237
 238         /*
 239          * now the secondary core is starting up let it run its
 240          * calibrations, then wait for it to finish
 241          */
 242 fail:
 243         spin_unlock(&boot_lock);
 244
 245         return pen_release != -1 ? ret : 0;
 246 }
 247
 248 /*
 249  * Initialise the CPU possible map early - this describes the CPUs
 250  * which may be present or become present in the system.
 251  */
 252
 253 static void __init exynos_smp_init_cpus(void)
 254 {
 255         void __iomem *scu_base = scu_base_addr();
 256         unsigned int i, ncores;
 257
 258         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 259                 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 260         else
 261                 /*
 262                  * CPU Nodes are passed thru DT and set_cpu_possible
 263                  * is set by "arm_dt_init_cpu_maps".
 264                  */
 265                 return;
 266
 267         /* sanity check */
 268         if (ncores > nr_cpu_ids) {
 269                 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
 270                         ncores, nr_cpu_ids);
 271                 ncores = nr_cpu_ids;
 272         }
 273
 274         for (i = 0; i < ncores; i++)
 275                 set_cpu_possible(i, true);
 276 }
 277
 278 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 279 {
 280         int i;
 281
 282         exynos_sysram_init();
 283
 284         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 285                 scu_enable(scu_base_addr());
 286
 287         /*
 288          * Write the address of secondary startup into the
 289          * system-wide flags register. The boot monitor waits
 290          * until it receives a soft interrupt, and then the
 291          * secondary CPU branches to this address.
 292          *
 293          * Try using firmware operation first and fall back to
 294          * boot register if it fails.
 295          */
 296         for (i = 1; i < max_cpus; ++i) {
 297                 unsigned long boot_addr;
 298                 u32 mpidr;
 299                 u32 core_id;
 300                 int ret;
 301
 302                 mpidr = cpu_logical_map(i);
 303                 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 304                 boot_addr = virt_to_phys(exynos4_secondary_startup);
 305
 306                 ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
 307                 if (ret && ret != -ENOSYS)
 308                         break;
 309                 if (ret == -ENOSYS) {
 310                         void __iomem *boot_reg = cpu_boot_reg(core_id);
 311
 312                         if (IS_ERR(boot_reg))
 313                                 break;
 314                         __raw_writel(boot_addr, cpu_boot_reg(core_id));
 315                 }
 316         }
 317 }
 318
 319 struct smp_operations exynos_smp_ops __initdata = {
 320         .smp_init_cpus          = exynos_smp_init_cpus,
 321         .smp_prepare_cpus       = exynos_smp_prepare_cpus,
 322         .smp_secondary_init     = exynos_secondary_init,
 323         .smp_boot_secondary     = exynos_boot_secondary,
 324 #ifdef CONFIG_HOTPLUG_CPU
 325         .cpu_die                = exynos_cpu_die,
 326 #endif
 327 };