2 * linux/arch/arm/mach-footbridge/common.c
4 * Copyright (C) 1998-2000 Russell King, Dave Gilbert.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/types.h>
13 #include <linux/ioport.h>
14 #include <linux/list.h>
15 #include <linux/init.h>
17 #include <linux/spinlock.h>
19 #include <asm/pgtable.h>
22 #include <asm/mach-types.h>
23 #include <asm/setup.h>
24 #include <asm/system_misc.h>
25 #include <asm/hardware/dec21285.h>
27 #include <asm/mach/irq.h>
28 #include <asm/mach/map.h>
32 unsigned int mem_fclk_21285
= 50000000;
34 EXPORT_SYMBOL(mem_fclk_21285
);
36 static int __init
early_fclk(char *arg
)
38 mem_fclk_21285
= simple_strtoul(arg
, NULL
, 0);
42 early_param("mem_fclk_21285", early_fclk
);
44 static int __init
parse_tag_memclk(const struct tag
*tag
)
46 mem_fclk_21285
= tag
->u
.memclk
.fmemclk
;
50 __tagtable(ATAG_MEMCLK
, parse_tag_memclk
);
53 * Footbridge IRQ translation table
54 * Converts from our IRQ numbers into FootBridge masks
56 static const int fb_irq_mask
[] = {
57 IRQ_MASK_UART_RX
, /* 0 */
58 IRQ_MASK_UART_TX
, /* 1 */
59 IRQ_MASK_TIMER1
, /* 2 */
60 IRQ_MASK_TIMER2
, /* 3 */
61 IRQ_MASK_TIMER3
, /* 4 */
66 IRQ_MASK_DOORBELLHOST
, /* 9 */
67 IRQ_MASK_DMA1
, /* 10 */
68 IRQ_MASK_DMA2
, /* 11 */
69 IRQ_MASK_PCI
, /* 12 */
70 IRQ_MASK_SDRAMPARITY
, /* 13 */
71 IRQ_MASK_I2OINPOST
, /* 14 */
72 IRQ_MASK_PCI_ABORT
, /* 15 */
73 IRQ_MASK_PCI_SERR
, /* 16 */
74 IRQ_MASK_DISCARD_TIMER
, /* 17 */
75 IRQ_MASK_PCI_DPERR
, /* 18 */
76 IRQ_MASK_PCI_PERR
, /* 19 */
79 static void fb_mask_irq(struct irq_data
*d
)
81 *CSR_IRQ_DISABLE
= fb_irq_mask
[_DC21285_INR(d
->irq
)];
84 static void fb_unmask_irq(struct irq_data
*d
)
86 *CSR_IRQ_ENABLE
= fb_irq_mask
[_DC21285_INR(d
->irq
)];
89 static struct irq_chip fb_chip
= {
90 .irq_ack
= fb_mask_irq
,
91 .irq_mask
= fb_mask_irq
,
92 .irq_unmask
= fb_unmask_irq
,
95 static void __init
__fb_init_irq(void)
102 *CSR_IRQ_DISABLE
= -1;
103 *CSR_FIQ_DISABLE
= -1;
105 for (irq
= _DC21285_IRQ(0); irq
< _DC21285_IRQ(20); irq
++) {
106 irq_set_chip_and_handler(irq
, &fb_chip
, handle_level_irq
);
107 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
111 void __init
footbridge_init_irq(void)
115 if (!footbridge_cfn_mode())
118 if (machine_is_ebsa285())
119 /* The following is dependent on which slot
120 * you plug the Southbridge card into. We
121 * currently assume that you plug it into
122 * the right-hand most slot.
124 isa_init_irq(IRQ_PCI
);
126 if (machine_is_cats())
127 isa_init_irq(IRQ_IN2
);
129 if (machine_is_netwinder())
130 isa_init_irq(IRQ_IN3
);
134 * Common mapping for all systems. Note that the outbound write flush is
135 * commented out since there is a "No Fix" problem with it. Not mapping
136 * it means that we have extra bullet protection on our feet.
138 static struct map_desc fb_common_io_desc
[] __initdata
= {
140 .virtual = ARMCSR_BASE
,
141 .pfn
= __phys_to_pfn(DC21285_ARMCSR_BASE
),
142 .length
= ARMCSR_SIZE
,
145 .virtual = XBUS_BASE
,
146 .pfn
= __phys_to_pfn(0x40000000),
153 * The mapping when the footbridge is in host mode. We don't map any of
154 * this when we are in add-in mode.
156 static struct map_desc ebsa285_host_io_desc
[] __initdata
= {
157 #if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_FOOTBRIDGE_HOST)
159 .virtual = PCIMEM_BASE
,
160 .pfn
= __phys_to_pfn(DC21285_PCI_MEM
),
161 .length
= PCIMEM_SIZE
,
164 .virtual = PCICFG0_BASE
,
165 .pfn
= __phys_to_pfn(DC21285_PCI_TYPE_0_CONFIG
),
166 .length
= PCICFG0_SIZE
,
169 .virtual = PCICFG1_BASE
,
170 .pfn
= __phys_to_pfn(DC21285_PCI_TYPE_1_CONFIG
),
171 .length
= PCICFG1_SIZE
,
174 .virtual = PCIIACK_BASE
,
175 .pfn
= __phys_to_pfn(DC21285_PCI_IACK
),
176 .length
= PCIIACK_SIZE
,
179 .virtual = PCIO_BASE
,
180 .pfn
= __phys_to_pfn(DC21285_PCI_IO
),
187 void __init
footbridge_map_io(void)
190 * Set up the common mapping first; we need this to
191 * determine whether we're in host mode or not.
193 iotable_init(fb_common_io_desc
, ARRAY_SIZE(fb_common_io_desc
));
196 * Now, work out what we've got to map in addition on this
199 if (footbridge_cfn_mode())
200 iotable_init(ebsa285_host_io_desc
, ARRAY_SIZE(ebsa285_host_io_desc
));
203 void footbridge_restart(char mode
, const char *cmd
)
206 /* Jump into the ROM */
207 soft_restart(0x41000000);
210 * Force the watchdog to do a CPU reset.
212 * After making sure that the watchdog is disabled
213 * (so we can change the timer registers) we first
214 * enable the timer to autoreload itself. Next, the
215 * timer interval is set really short and any
216 * current interrupt request is cleared (so we can
217 * see an edge transition). Finally, TIMER4 is
218 * enabled as the watchdog.
220 *CSR_SA110_CNTL
&= ~(1 << 13);
221 *CSR_TIMER4_CNTL
= TIMER_CNTL_ENABLE
|
222 TIMER_CNTL_AUTORELOAD
|
224 *CSR_TIMER4_LOAD
= 0x2;
226 *CSR_SA110_CNTL
|= (1 << 13);
230 #ifdef CONFIG_FOOTBRIDGE_ADDIN
232 static inline unsigned long fb_bus_sdram_offset(void)
234 return *CSR_PCISDRAMBASE
& 0xfffffff0;
238 * These two functions convert virtual addresses to PCI addresses and PCI
239 * addresses to virtual addresses. Note that it is only legal to use these
240 * on memory obtained via get_zeroed_page or kmalloc.
242 unsigned long __virt_to_bus(unsigned long res
)
244 WARN_ON(res
< PAGE_OFFSET
|| res
>= (unsigned long)high_memory
);
246 return res
+ (fb_bus_sdram_offset() - PAGE_OFFSET
);
248 EXPORT_SYMBOL(__virt_to_bus
);
250 unsigned long __bus_to_virt(unsigned long res
)
252 res
= res
- (fb_bus_sdram_offset() - PAGE_OFFSET
);
254 WARN_ON(res
< PAGE_OFFSET
|| res
>= (unsigned long)high_memory
);
258 EXPORT_SYMBOL(__bus_to_virt
);
260 unsigned long __pfn_to_bus(unsigned long pfn
)
262 return __pfn_to_phys(pfn
) + (fb_bus_sdram_offset() - PHYS_OFFSET
);
264 EXPORT_SYMBOL(__pfn_to_bus
);
266 unsigned long __bus_to_pfn(unsigned long bus
)
268 return __phys_to_pfn(bus
- (fb_bus_sdram_offset() - PHYS_OFFSET
));
270 EXPORT_SYMBOL(__bus_to_pfn
);