arch/arm/mach-footbridge/include/mach/memory.h

   1 /*
   2  *  arch/arm/mach-footbridge/include/mach/memory.h
   3  *
   4  *  Copyright (C) 1996-1999 Russell King.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  Changelog:
  11  *   20-Oct-1996 RMK    Created
  12  *   31-Dec-1997 RMK    Fixed definitions to reduce warnings.
  13  *   17-May-1998 DAG    Added __virt_to_bus and __bus_to_virt functions.
  14  *   21-Nov-1998 RMK    Changed __virt_to_bus and __bus_to_virt to macros.
  15  *   21-Mar-1999 RMK    Added PAGE_OFFSET for co285 architecture.
  16  *                      Renamed to memory.h
  17  *                      Moved PAGE_OFFSET and TASK_SIZE here
  18  */
  19 #ifndef __ASM_ARCH_MEMORY_H
  20 #define __ASM_ARCH_MEMORY_H
  21
  22
  23 #if defined(CONFIG_FOOTBRIDGE_ADDIN)
  24 /*
  25  * If we may be using add-in footbridge mode, then we must
  26  * use the out-of-line translation that makes use of the
  27  * PCI BAR
  28  */
  29 #ifndef __ASSEMBLY__
  30 extern unsigned long __virt_to_bus(unsigned long);
  31 extern unsigned long __bus_to_virt(unsigned long);
  32 #endif
  33 #define __virt_to_bus   __virt_to_bus
  34 #define __bus_to_virt   __bus_to_virt
  35
  36 #elif defined(CONFIG_FOOTBRIDGE_HOST)
  37
  38 /*
  39  * The footbridge is programmed to expose the system RAM at the corresponding
  40  * address.  So, if PAGE_OFFSET is 0xc0000000, RAM appears at 0xe0000000.
  41  * If 0x80000000, then its exposed at 0xa0000000 on the bus. etc.
  42  * The only requirement is that the RAM isn't placed at bus address 0 which
  43  * would clash with VGA cards.
  44  */
  45 #define __virt_to_bus(x)        ((x) - 0xe0000000)
  46 #define __bus_to_virt(x)        ((x) + 0xe0000000)
  47
  48 #else
  49
  50 #error "Undefined footbridge mode"
  51
  52 #endif
  53
  54 /*
  55  * Cache flushing area.
  56  */
  57 #define FLUSH_BASE              0xf9000000
  58
  59 /*
  60  * Physical DRAM offset.
  61  */
  62 #define PHYS_OFFSET             UL(0x00000000)
  63
  64 #define FLUSH_BASE_PHYS         0x50000000
  65
  66 #endif