arch/arm/mach-imx/clk-pllv3.c

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2012 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/delay.h>
  16 #include <linux/io.h>
  17 #include <linux/slab.h>
  18 #include <linux/jiffies.h>
  19 #include <linux/err.h>
  20 #include "clk.h"
  21
  22 #define PLL_NUM_OFFSET          0x10
  23 #define PLL_DENOM_OFFSET        0x20
  24
  25 #define BM_PLL_POWER            (0x1 << 12)
  26 #define BM_PLL_LOCK             (0x1 << 31)
  27
  28 /**
  29  * struct clk_pllv3 - IMX PLL clock version 3
  30  * @clk_hw:      clock source
  31  * @base:        base address of PLL registers
  32  * @powerup_set: set POWER bit to power up the PLL
  33  * @div_mask:    mask of divider bits
  34  *
  35  * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
  36  * is actually a multiplier, and always sits at bit 0.
  37  */
  38 struct clk_pllv3 {
  39         struct clk_hw   hw;
  40         void __iomem    *base;
  41         bool            powerup_set;
  42         u32             div_mask;
  43 };
  44
  45 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
  46
  47 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
  48 {
  49         unsigned long timeout = jiffies + msecs_to_jiffies(10);
  50         u32 val = readl_relaxed(pll->base) & BM_PLL_POWER;
  51
  52         /* No need to wait for lock when pll is not powered up */
  53         if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
  54                 return 0;
  55
  56         /* Wait for PLL to lock */
  57         do {
  58                 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
  59                         break;
  60                 if (time_after(jiffies, timeout))
  61                         break;
  62                 usleep_range(50, 500);
  63         } while (1);
  64
  65         return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
  66 }
  67
  68 static int clk_pllv3_prepare(struct clk_hw *hw)
  69 {
  70         struct clk_pllv3 *pll = to_clk_pllv3(hw);
  71         u32 val;
  72
  73         val = readl_relaxed(pll->base);
  74         if (pll->powerup_set)
  75                 val |= BM_PLL_POWER;
  76         else
  77                 val &= ~BM_PLL_POWER;
  78         writel_relaxed(val, pll->base);
  79
  80         return clk_pllv3_wait_lock(pll);
  81 }
  82
  83 static void clk_pllv3_unprepare(struct clk_hw *hw)
  84 {
  85         struct clk_pllv3 *pll = to_clk_pllv3(hw);
  86         u32 val;
  87
  88         val = readl_relaxed(pll->base);
  89         if (pll->powerup_set)
  90                 val &= ~BM_PLL_POWER;
  91         else
  92                 val |= BM_PLL_POWER;
  93         writel_relaxed(val, pll->base);
  94 }
  95
  96 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
  97                                            unsigned long parent_rate)
  98 {
  99         struct clk_pllv3 *pll = to_clk_pllv3(hw);
 100         u32 div = readl_relaxed(pll->base)  & pll->div_mask;
 101
 102         return (div == 1) ? parent_rate * 22 : parent_rate * 20;
 103 }
 104
 105 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
 106                                  unsigned long *prate)
 107 {
 108         unsigned long parent_rate = *prate;
 109
 110         return (rate >= parent_rate * 22) ? parent_rate * 22 :
 111                                             parent_rate * 20;
 112 }
 113
 114 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
 115                 unsigned long parent_rate)
 116 {
 117         struct clk_pllv3 *pll = to_clk_pllv3(hw);
 118         u32 val, div;
 119
 120         if (rate == parent_rate * 22)
 121                 div = 1;
 122         else if (rate == parent_rate * 20)
 123                 div = 0;
 124         else
 125                 return -EINVAL;
 126
 127         val = readl_relaxed(pll->base);
 128         val &= ~pll->div_mask;
 129         val |= div;
 130         writel_relaxed(val, pll->base);
 131
 132         return clk_pllv3_wait_lock(pll);
 133 }
 134
 135 static const struct clk_ops clk_pllv3_ops = {
 136         .prepare        = clk_pllv3_prepare,
 137         .unprepare      = clk_pllv3_unprepare,
 138         .recalc_rate    = clk_pllv3_recalc_rate,
 139         .round_rate     = clk_pllv3_round_rate,
 140         .set_rate       = clk_pllv3_set_rate,
 141 };
 142
 143 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
 144                                                unsigned long parent_rate)
 145 {
 146         struct clk_pllv3 *pll = to_clk_pllv3(hw);
 147         u32 div = readl_relaxed(pll->base) & pll->div_mask;
 148
 149         return parent_rate * div / 2;
 150 }
 151
 152 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
 153                                      unsigned long *prate)
 154 {
 155         unsigned long parent_rate = *prate;
 156         unsigned long min_rate = parent_rate * 54 / 2;
 157         unsigned long max_rate = parent_rate * 108 / 2;
 158         u32 div;
 159
 160         if (rate > max_rate)
 161                 rate = max_rate;
 162         else if (rate < min_rate)
 163                 rate = min_rate;
 164         div = rate * 2 / parent_rate;
 165
 166         return parent_rate * div / 2;
 167 }
 168
 169 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
 170                 unsigned long parent_rate)
 171 {
 172         struct clk_pllv3 *pll = to_clk_pllv3(hw);
 173         unsigned long min_rate = parent_rate * 54 / 2;
 174         unsigned long max_rate = parent_rate * 108 / 2;
 175         u32 val, div;
 176
 177         if (rate < min_rate || rate > max_rate)
 178                 return -EINVAL;
 179
 180         div = rate * 2 / parent_rate;
 181         val = readl_relaxed(pll->base);
 182         val &= ~pll->div_mask;
 183         val |= div;
 184         writel_relaxed(val, pll->base);
 185
 186         return clk_pllv3_wait_lock(pll);
 187 }
 188
 189 static const struct clk_ops clk_pllv3_sys_ops = {
 190         .prepare        = clk_pllv3_prepare,
 191         .unprepare      = clk_pllv3_unprepare,
 192         .recalc_rate    = clk_pllv3_sys_recalc_rate,
 193         .round_rate     = clk_pllv3_sys_round_rate,
 194         .set_rate       = clk_pllv3_sys_set_rate,
 195 };
 196
 197 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
 198                                               unsigned long parent_rate)
 199 {
 200         struct clk_pllv3 *pll = to_clk_pllv3(hw);
 201         u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
 202         u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
 203         u32 div = readl_relaxed(pll->base) & pll->div_mask;
 204
 205         return (parent_rate * div) + ((parent_rate / mfd) * mfn);
 206 }
 207
 208 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
 209                                     unsigned long *prate)
 210 {
 211         unsigned long parent_rate = *prate;
 212         unsigned long min_rate = parent_rate * 27;
 213         unsigned long max_rate = parent_rate * 54;
 214         u32 div;
 215         u32 mfn, mfd = 1000000;
 216         s64 temp64;
 217
 218         if (rate > max_rate)
 219                 rate = max_rate;
 220         else if (rate < min_rate)
 221                 rate = min_rate;
 222
 223         div = rate / parent_rate;
 224         temp64 = (u64) (rate - div * parent_rate);
 225         temp64 *= mfd;
 226         do_div(temp64, parent_rate);
 227         mfn = temp64;
 228
 229         return parent_rate * div + parent_rate / mfd * mfn;
 230 }
 231
 232 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
 233                 unsigned long parent_rate)
 234 {
 235         struct clk_pllv3 *pll = to_clk_pllv3(hw);
 236         unsigned long min_rate = parent_rate * 27;
 237         unsigned long max_rate = parent_rate * 54;
 238         u32 val, div;
 239         u32 mfn, mfd = 1000000;
 240         s64 temp64;
 241
 242         if (rate < min_rate || rate > max_rate)
 243                 return -EINVAL;
 244
 245         div = rate / parent_rate;
 246         temp64 = (u64) (rate - div * parent_rate);
 247         temp64 *= mfd;
 248         do_div(temp64, parent_rate);
 249         mfn = temp64;
 250
 251         val = readl_relaxed(pll->base);
 252         val &= ~pll->div_mask;
 253         val |= div;
 254         writel_relaxed(val, pll->base);
 255         writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
 256         writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
 257
 258         return clk_pllv3_wait_lock(pll);
 259 }
 260
 261 static const struct clk_ops clk_pllv3_av_ops = {
 262         .prepare        = clk_pllv3_prepare,
 263         .unprepare      = clk_pllv3_unprepare,
 264         .recalc_rate    = clk_pllv3_av_recalc_rate,
 265         .round_rate     = clk_pllv3_av_round_rate,
 266         .set_rate       = clk_pllv3_av_set_rate,
 267 };
 268
 269 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
 270                                                 unsigned long parent_rate)
 271 {
 272         return 500000000;
 273 }
 274
 275 static const struct clk_ops clk_pllv3_enet_ops = {
 276         .prepare        = clk_pllv3_prepare,
 277         .unprepare      = clk_pllv3_unprepare,
 278         .recalc_rate    = clk_pllv3_enet_recalc_rate,
 279 };
 280
 281 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 282                           const char *parent_name, void __iomem *base,
 283                           u32 div_mask)
 284 {
 285         struct clk_pllv3 *pll;
 286         const struct clk_ops *ops;
 287         struct clk *clk;
 288         struct clk_init_data init;
 289
 290         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 291         if (!pll)
 292                 return ERR_PTR(-ENOMEM);
 293
 294         switch (type) {
 295         case IMX_PLLV3_SYS:
 296                 ops = &clk_pllv3_sys_ops;
 297                 break;
 298         case IMX_PLLV3_USB:
 299                 ops = &clk_pllv3_ops;
 300                 pll->powerup_set = true;
 301                 break;
 302         case IMX_PLLV3_AV:
 303                 ops = &clk_pllv3_av_ops;
 304                 break;
 305         case IMX_PLLV3_ENET:
 306                 ops = &clk_pllv3_enet_ops;
 307                 break;
 308         default:
 309                 ops = &clk_pllv3_ops;
 310         }
 311         pll->base = base;
 312         pll->div_mask = div_mask;
 313
 314         init.name = name;
 315         init.ops = ops;
 316         init.flags = 0;
 317         init.parent_names = &parent_name;
 318         init.num_parents = 1;
 319
 320         pll->hw.init = &init;
 321
 322         clk = clk_register(NULL, &pll->hw);
 323         if (IS_ERR(clk))
 324                 kfree(pll);
 325
 326         return clk;
 327 }