3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
5 * based on board-mx51_babbage.c which is
6 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c.h>
20 #include <linux/i2c/tsc2007.h>
21 #include <linux/gpio.h>
22 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/i2c-gpio.h>
26 #include <linux/spi/spi.h>
27 #include <linux/can/platform/mcp251x.h>
29 #include <mach/eukrea-baseboards.h>
30 #include <mach/common.h>
31 #include <mach/hardware.h>
32 #include <mach/iomux-mx51.h>
34 #include <asm/setup.h>
35 #include <asm/mach-types.h>
36 #include <asm/mach/arch.h>
37 #include <asm/mach/time.h>
39 #include "devices-imx51.h"
40 #include "cpu_op-mx51.h"
42 #define USBH1_RST IMX_GPIO_NR(2, 28)
43 #define ETH_RST IMX_GPIO_NR(2, 31)
44 #define TSC2007_IRQGPIO IMX_GPIO_NR(3, 12)
45 #define CAN_IRQGPIO IMX_GPIO_NR(1, 1)
46 #define CAN_RST IMX_GPIO_NR(4, 15)
47 #define CAN_NCS IMX_GPIO_NR(4, 24)
48 #define CAN_RXOBF IMX_GPIO_NR(1, 4)
49 #define CAN_RX1BF IMX_GPIO_NR(1, 6)
50 #define CAN_TXORTS IMX_GPIO_NR(1, 7)
51 #define CAN_TX1RTS IMX_GPIO_NR(1, 8)
52 #define CAN_TX2RTS IMX_GPIO_NR(1, 9)
53 #define I2C_SCL IMX_GPIO_NR(4, 16)
54 #define I2C_SDA IMX_GPIO_NR(4, 17)
57 #define MX51_USB_CTRL_1_OFFSET 0x10
58 #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
60 #define MX51_USB_PLLDIV_12_MHZ 0x00
61 #define MX51_USB_PLL_DIV_19_2_MHZ 0x01
62 #define MX51_USB_PLL_DIV_24_MHZ 0x02
64 static iomux_v3_cfg_t eukrea_cpuimx51sd_pads
[] = {
66 MX51_PAD_UART1_RXD__UART1_RXD
,
67 MX51_PAD_UART1_TXD__UART1_TXD
,
68 MX51_PAD_UART1_RTS__UART1_RTS
,
69 MX51_PAD_UART1_CTS__UART1_CTS
,
72 MX51_PAD_USBH1_CLK__USBH1_CLK
,
73 MX51_PAD_USBH1_DIR__USBH1_DIR
,
74 MX51_PAD_USBH1_NXT__USBH1_NXT
,
75 MX51_PAD_USBH1_DATA0__USBH1_DATA0
,
76 MX51_PAD_USBH1_DATA1__USBH1_DATA1
,
77 MX51_PAD_USBH1_DATA2__USBH1_DATA2
,
78 MX51_PAD_USBH1_DATA3__USBH1_DATA3
,
79 MX51_PAD_USBH1_DATA4__USBH1_DATA4
,
80 MX51_PAD_USBH1_DATA5__USBH1_DATA5
,
81 MX51_PAD_USBH1_DATA6__USBH1_DATA6
,
82 MX51_PAD_USBH1_DATA7__USBH1_DATA7
,
83 MX51_PAD_USBH1_STP__USBH1_STP
,
84 MX51_PAD_EIM_CS3__GPIO2_28
, /* PHY nRESET */
87 MX51_PAD_EIM_DTACK__GPIO2_31
, /* PHY nRESET */
90 MX51_PAD_I2C1_CLK__GPIO4_16
,
91 MX51_PAD_I2C1_DAT__GPIO4_17
,
94 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI
,
95 MX51_PAD_CSPI1_MISO__ECSPI1_MISO
,
96 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK
,
97 MX51_PAD_CSPI1_SS0__GPIO4_24
, /* nCS */
98 MX51_PAD_CSI2_PIXCLK__GPIO4_15
, /* nReset */
99 MX51_PAD_GPIO1_1__GPIO1_1
, /* IRQ */
100 MX51_PAD_GPIO1_4__GPIO1_4
, /* Control signals */
101 MX51_PAD_GPIO1_6__GPIO1_6
,
102 MX51_PAD_GPIO1_7__GPIO1_7
,
103 MX51_PAD_GPIO1_8__GPIO1_8
,
104 MX51_PAD_GPIO1_9__GPIO1_9
,
108 NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND
, PAD_CTL_PUS_22K_UP
|
109 PAD_CTL_PKE
| PAD_CTL_SRE_FAST
|
110 PAD_CTL_DSE_HIGH
| PAD_CTL_PUE
| PAD_CTL_HYS
),
113 static const struct imxuart_platform_data uart_pdata __initconst
= {
114 .flags
= IMXUART_HAVE_RTSCTS
,
117 static struct tsc2007_platform_data tsc2007_info
= {
122 static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices
[] = {
124 I2C_BOARD_INFO("pcf8563", 0x51),
126 I2C_BOARD_INFO("tsc2007", 0x49),
127 .platform_data
= &tsc2007_info
,
128 .irq
= IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO
),
132 static const struct mxc_nand_platform_data
133 eukrea_cpuimx51sd_nand_board_info __initconst
= {
139 /* This function is board specific as the bit mask for the plldiv will also
140 be different for other Freescale SoCs, thus a common bitmask is not
141 possible and cannot get place in /plat-mxc/ehci.c.*/
142 static int initialize_otg_port(struct platform_device
*pdev
)
145 void __iomem
*usb_base
;
146 void __iomem
*usbother_base
;
148 usb_base
= ioremap(MX51_USB_OTG_BASE_ADDR
, SZ_4K
);
151 usbother_base
= usb_base
+ MX5_USBOTHER_REGS_OFFSET
;
153 /* Set the PHY clock to 19.2MHz */
154 v
= __raw_readl(usbother_base
+ MXC_USB_PHY_CTR_FUNC2_OFFSET
);
155 v
&= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK
;
156 v
|= MX51_USB_PLL_DIV_19_2_MHZ
;
157 __raw_writel(v
, usbother_base
+ MXC_USB_PHY_CTR_FUNC2_OFFSET
);
162 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY
);
165 static int initialize_usbh1_port(struct platform_device
*pdev
)
168 void __iomem
*usb_base
;
169 void __iomem
*usbother_base
;
171 usb_base
= ioremap(MX51_USB_OTG_BASE_ADDR
, SZ_4K
);
174 usbother_base
= usb_base
+ MX5_USBOTHER_REGS_OFFSET
;
176 /* The clock for the USBH1 ULPI port will come from the PHY. */
177 v
= __raw_readl(usbother_base
+ MX51_USB_CTRL_1_OFFSET
);
178 __raw_writel(v
| MX51_USB_CTRL_UH1_EXT_CLK_EN
,
179 usbother_base
+ MX51_USB_CTRL_1_OFFSET
);
184 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED
|
185 MXC_EHCI_ITC_NO_THRESHOLD
);
188 static const struct mxc_usbh_platform_data dr_utmi_config __initconst
= {
189 .init
= initialize_otg_port
,
190 .portsc
= MXC_EHCI_UTMI_16BIT
,
193 static const struct fsl_usb2_platform_data usb_pdata __initconst
= {
194 .operating_mode
= FSL_USB2_DR_DEVICE
,
195 .phy_mode
= FSL_USB2_PHY_UTMI_WIDE
,
198 static const struct mxc_usbh_platform_data usbh1_config __initconst
= {
199 .init
= initialize_usbh1_port
,
200 .portsc
= MXC_EHCI_MODE_ULPI
,
203 static int otg_mode_host
;
205 static int __init
eukrea_cpuimx51sd_otg_mode(char *options
)
207 if (!strcmp(options
, "host"))
209 else if (!strcmp(options
, "device"))
212 pr_info("otg_mode neither \"host\" nor \"device\". "
213 "Defaulting to device\n");
216 __setup("otg_mode=", eukrea_cpuimx51sd_otg_mode
);
218 static struct i2c_gpio_platform_data pdata
= {
220 .sda_is_open_drain
= 0,
222 .scl_is_open_drain
= 0,
226 static struct platform_device hsi2c_gpio_device
= {
229 .dev
.platform_data
= &pdata
,
232 static struct mcp251x_platform_data mcp251x_info
= {
233 .oscillator_frequency
= 24E6
,
236 static struct spi_board_info cpuimx51sd_spi_device
[] = {
238 .modalias
= "mcp2515",
239 .max_speed_hz
= 10000000,
243 .platform_data
= &mcp251x_info
,
244 .irq
= IMX_GPIO_TO_IRQ(CAN_IRQGPIO
)
248 static int cpuimx51sd_spi1_cs
[] = {
252 static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst
= {
253 .chipselect
= cpuimx51sd_spi1_cs
,
254 .num_chipselect
= ARRAY_SIZE(cpuimx51sd_spi1_cs
),
257 static struct platform_device
*platform_devices
[] __initdata
= {
261 static void __init
eukrea_cpuimx51sd_init(void)
265 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads
,
266 ARRAY_SIZE(eukrea_cpuimx51sd_pads
));
268 #if defined(CONFIG_CPU_FREQ_IMX)
269 get_cpu_op
= mx51_get_cpu_op
;
272 imx51_add_imx_uart(0, &uart_pdata
);
273 imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info
);
275 gpio_request(ETH_RST
, "eth_rst");
276 gpio_set_value(ETH_RST
, 1);
279 gpio_request(CAN_IRQGPIO
, "can_irq");
280 gpio_direction_input(CAN_IRQGPIO
);
281 gpio_free(CAN_IRQGPIO
);
282 gpio_request(CAN_NCS
, "can_ncs");
283 gpio_direction_output(CAN_NCS
, 1);
285 gpio_request(CAN_RST
, "can_rst");
286 gpio_direction_output(CAN_RST
, 0);
288 gpio_set_value(CAN_RST
, 1);
289 imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata
);
290 spi_register_board_info(cpuimx51sd_spi_device
,
291 ARRAY_SIZE(cpuimx51sd_spi_device
));
293 gpio_request(TSC2007_IRQGPIO
, "tsc2007_irq");
294 gpio_direction_input(TSC2007_IRQGPIO
);
295 gpio_free(TSC2007_IRQGPIO
);
297 i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices
,
298 ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices
));
299 platform_add_devices(platform_devices
, ARRAY_SIZE(platform_devices
));
302 imx51_add_mxc_ehci_otg(&dr_utmi_config
);
304 initialize_otg_port(NULL
);
305 imx51_add_fsl_usb2_udc(&usb_pdata
);
308 gpio_request(USBH1_RST
, "usb_rst");
309 gpio_direction_output(USBH1_RST
, 0);
311 gpio_set_value(USBH1_RST
, 1);
312 imx51_add_mxc_ehci_hs(1, &usbh1_config
);
314 #ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
315 eukrea_mbimxsd51_baseboard_init();
319 static void __init
eukrea_cpuimx51sd_timer_init(void)
321 mx51_clocks_init(32768, 24000000, 22579200, 0);
324 static struct sys_timer mxc_timer
= {
325 .init
= eukrea_cpuimx51sd_timer_init
,
328 MACHINE_START(EUKREA_CPUIMX51SD
, "Eukrea CPUIMX51SD")
329 /* Maintainer: Eric Bénard <eric@eukrea.com> */
330 .atag_offset
= 0x100,
331 .map_io
= mx51_map_io
,
332 .init_early
= imx51_init_early
,
333 .init_irq
= mx51_init_irq
,
334 .handle_irq
= imx51_handle_irq
,
336 .init_machine
= eukrea_cpuimx51sd_init
,
337 .restart
= mxc_restart
,