2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/err.h>
23 #include <asm/pgtable.h>
24 #include <asm/hardware/cache-l2x0.h>
25 #include <asm/mach/map.h>
27 #include <mach/common.h>
28 #include <mach/devices-common.h>
29 #include <mach/hardware.h>
30 #include <mach/iomux-v3.h>
31 #include <mach/irqs.h>
33 static void imx3_idle(void)
35 unsigned long reg
= 0;
39 /* disable I and D cache */
40 "mrc p15, 0, %0, c1, c0, 0\n"
41 "bic %0, %0, #0x00001000\n"
42 "bic %0, %0, #0x00000004\n"
43 "mcr p15, 0, %0, c1, c0, 0\n"
44 /* invalidate I cache */
46 "mcr p15, 0, %0, c7, c5, 0\n"
47 /* clear and invalidate D cache */
49 "mcr p15, 0, %0, c7, c14, 0\n"
52 "mcr p15, 0, %0, c7, c0, 4\n"
53 "nop\n" "nop\n" "nop\n" "nop\n"
54 "nop\n" "nop\n" "nop\n"
55 /* enable I and D cache */
56 "mrc p15, 0, %0, c1, c0, 0\n"
57 "orr %0, %0, #0x00001000\n"
58 "orr %0, %0, #0x00000004\n"
59 "mcr p15, 0, %0, c1, c0, 0\n"
64 static void __iomem
*imx3_ioremap(unsigned long phys_addr
, size_t size
,
67 if (mtype
== MT_DEVICE
) {
69 * Access all peripherals below 0x80000000 as nonshared device
70 * on mx3, but leave l2cc alone. Otherwise cache corruptions
73 if (phys_addr
< 0x80000000 &&
74 !addr_in_module(phys_addr
, MX3x_L2CC
))
75 mtype
= MT_DEVICE_NONSHARED
;
78 return __arm_ioremap(phys_addr
, size
, mtype
);
81 void imx3_init_l2x0(void)
83 void __iomem
*l2x0_base
;
84 void __iomem
*clkctl_base
;
87 * First of all, we must repair broken chip settings. There are some
88 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
89 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
90 * Workaraound is to setup the correct register setting prior enabling the
91 * L2 cache. This should not hurt already working CPUs, as they are using the
94 #define L2_MEM_VAL 0x10
96 clkctl_base
= ioremap(MX35_CLKCTL_BASE_ADDR
, 4096);
97 if (clkctl_base
!= NULL
) {
98 writel(0x00000515, clkctl_base
+ L2_MEM_VAL
);
101 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
104 l2x0_base
= ioremap(MX3x_L2CC_BASE_ADDR
, 4096);
105 if (IS_ERR(l2x0_base
)) {
106 printk(KERN_ERR
"remapping L2 cache area failed with %ld\n",
111 l2x0_init(l2x0_base
, 0x00030024, 0x00000000);
114 #ifdef CONFIG_SOC_IMX31
115 static struct map_desc mx31_io_desc
[] __initdata
= {
116 imx_map_entry(MX31
, X_MEMC
, MT_DEVICE
),
117 imx_map_entry(MX31
, AVIC
, MT_DEVICE_NONSHARED
),
118 imx_map_entry(MX31
, AIPS1
, MT_DEVICE_NONSHARED
),
119 imx_map_entry(MX31
, AIPS2
, MT_DEVICE_NONSHARED
),
120 imx_map_entry(MX31
, SPBA0
, MT_DEVICE_NONSHARED
),
124 * This function initializes the memory map. It is called during the
125 * system startup to create static physical to virtual memory mappings
126 * for the IO modules.
128 void __init
mx31_map_io(void)
130 iotable_init(mx31_io_desc
, ARRAY_SIZE(mx31_io_desc
));
133 void __init
imx31_init_early(void)
135 mxc_set_cpu_type(MXC_CPU_MX31
);
136 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR
));
138 imx_ioremap
= imx3_ioremap
;
141 void __init
mx31_init_irq(void)
143 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR
));
146 static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata
= {
147 .per_2_per_addr
= 1677,
150 static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata
= {
153 .bp_2_ap_addr
= 1029,
156 static struct sdma_platform_data imx31_sdma_pdata __initdata
= {
157 .fw_name
= "sdma-imx31-to2.bin",
158 .script_addrs
= &imx31_to2_sdma_script
,
161 static const struct resource imx31_audmux_res
[] __initconst
= {
162 DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR
, SZ_16K
),
165 void __init
imx31_soc_init(void)
167 int to_version
= mx31_revision() >> 4;
171 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR
, SZ_16K
, MX31_INT_GPIO1
, 0);
172 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR
, SZ_16K
, MX31_INT_GPIO2
, 0);
173 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR
, SZ_16K
, MX31_INT_GPIO3
, 0);
175 if (to_version
== 1) {
176 strncpy(imx31_sdma_pdata
.fw_name
, "sdma-imx31-to1.bin",
177 strlen(imx31_sdma_pdata
.fw_name
));
178 imx31_sdma_pdata
.script_addrs
= &imx31_to1_sdma_script
;
181 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR
, MX31_INT_SDMA
, &imx31_sdma_pdata
);
182 platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res
,
183 ARRAY_SIZE(imx31_audmux_res
));
185 #endif /* ifdef CONFIG_SOC_IMX31 */
187 #ifdef CONFIG_SOC_IMX35
188 static struct map_desc mx35_io_desc
[] __initdata
= {
189 imx_map_entry(MX35
, X_MEMC
, MT_DEVICE
),
190 imx_map_entry(MX35
, AVIC
, MT_DEVICE_NONSHARED
),
191 imx_map_entry(MX35
, AIPS1
, MT_DEVICE_NONSHARED
),
192 imx_map_entry(MX35
, AIPS2
, MT_DEVICE_NONSHARED
),
193 imx_map_entry(MX35
, SPBA0
, MT_DEVICE_NONSHARED
),
196 void __init
mx35_map_io(void)
198 iotable_init(mx35_io_desc
, ARRAY_SIZE(mx35_io_desc
));
201 void __init
imx35_init_early(void)
203 mxc_set_cpu_type(MXC_CPU_MX35
);
204 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR
));
205 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR
));
207 imx_ioremap
= imx3_ioremap
;
210 void __init
mx35_init_irq(void)
212 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR
));
215 static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata
= {
217 .uart_2_mcu_addr
= 817,
218 .mcu_2_app_addr
= 747,
219 .uartsh_2_mcu_addr
= 1183,
220 .per_2_shp_addr
= 1033,
221 .mcu_2_shp_addr
= 961,
222 .ata_2_mcu_addr
= 1333,
223 .mcu_2_ata_addr
= 1252,
224 .app_2_mcu_addr
= 683,
225 .shp_2_per_addr
= 1111,
226 .shp_2_mcu_addr
= 892,
229 static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata
= {
231 .uart_2_mcu_addr
= 904,
232 .per_2_app_addr
= 1597,
233 .mcu_2_app_addr
= 834,
234 .uartsh_2_mcu_addr
= 1270,
235 .per_2_shp_addr
= 1120,
236 .mcu_2_shp_addr
= 1048,
237 .ata_2_mcu_addr
= 1429,
238 .mcu_2_ata_addr
= 1339,
239 .app_2_per_addr
= 1531,
240 .app_2_mcu_addr
= 770,
241 .shp_2_per_addr
= 1198,
242 .shp_2_mcu_addr
= 979,
245 static struct sdma_platform_data imx35_sdma_pdata __initdata
= {
246 .fw_name
= "sdma-imx35-to2.bin",
247 .script_addrs
= &imx35_to2_sdma_script
,
250 static const struct resource imx35_audmux_res
[] __initconst
= {
251 DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR
, SZ_16K
),
254 void __init
imx35_soc_init(void)
256 int to_version
= mx35_revision() >> 4;
260 /* i.mx35 has the i.mx31 type gpio */
261 mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR
, SZ_16K
, MX35_INT_GPIO1
, 0);
262 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR
, SZ_16K
, MX35_INT_GPIO2
, 0);
263 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR
, SZ_16K
, MX35_INT_GPIO3
, 0);
265 if (to_version
== 1) {
266 strncpy(imx35_sdma_pdata
.fw_name
, "sdma-imx35-to1.bin",
267 strlen(imx35_sdma_pdata
.fw_name
));
268 imx35_sdma_pdata
.script_addrs
= &imx35_to1_sdma_script
;
271 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR
, MX35_INT_SDMA
, &imx35_sdma_pdata
);
272 /* i.mx35 has the i.mx31 type audmux */
273 platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res
,
274 ARRAY_SIZE(imx35_audmux_res
));
276 #endif /* ifdef CONFIG_SOC_IMX35 */