arch/arm/mach-imx/time.c

   1 /*
   2  *  linux/arch/arm/plat-mxc/time.c
   3  *
   4  *  Copyright (C) 2000-2001 Deep Blue Solutions
   5  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   6  *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
   7  *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version 2
  12  * of the License, or (at your option) any later version.
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  21  * MA 02110-1301, USA.
  22  */
  23
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/clockchips.h>
  27 #include <linux/clk.h>
  28 #include <linux/delay.h>
  29 #include <linux/err.h>
  30 #include <linux/sched_clock.h>
  31 #include <linux/of.h>
  32 #include <linux/of_address.h>
  33 #include <linux/of_irq.h>
  34
  35 #include <asm/mach/time.h>
  36
  37 #include "common.h"
  38 #include "hardware.h"
  39
  40 /*
  41  * There are 2 versions of the timer hardware on Freescale MXC hardware.
  42  * Version 1: MX1/MXL, MX21, MX27.
  43  * Version 2: MX25, MX31, MX35, MX37, MX51
  44  */
  45
  46 /* defines common for all i.MX */
  47 #define MXC_TCTL                0x00
  48 #define MXC_TCTL_TEN            (1 << 0) /* Enable module */
  49 #define MXC_TPRER               0x04
  50
  51 /* MX1, MX21, MX27 */
  52 #define MX1_2_TCTL_CLK_PCLK1    (1 << 1)
  53 #define MX1_2_TCTL_IRQEN        (1 << 4)
  54 #define MX1_2_TCTL_FRR          (1 << 8)
  55 #define MX1_2_TCMP              0x08
  56 #define MX1_2_TCN               0x10
  57 #define MX1_2_TSTAT             0x14
  58
  59 /* MX21, MX27 */
  60 #define MX2_TSTAT_CAPT          (1 << 1)
  61 #define MX2_TSTAT_COMP          (1 << 0)
  62
  63 /* MX31, MX35, MX25, MX5 */
  64 #define V2_TCTL_WAITEN          (1 << 3) /* Wait enable mode */
  65 #define V2_TCTL_CLK_IPG         (1 << 6)
  66 #define V2_TCTL_CLK_PER         (2 << 6)
  67 #define V2_TCTL_FRR             (1 << 9)
  68 #define V2_IR                   0x0c
  69 #define V2_TSTAT                0x08
  70 #define V2_TSTAT_OF1            (1 << 0)
  71 #define V2_TCN                  0x24
  72 #define V2_TCMP                 0x10
  73
  74 #define timer_is_v1()   (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
  75 #define timer_is_v2()   (!timer_is_v1())
  76
  77 static struct clock_event_device clockevent_mxc;
  78 static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
  79
  80 static void __iomem *timer_base;
  81
  82 static inline void gpt_irq_disable(void)
  83 {
  84         unsigned int tmp;
  85
  86         if (timer_is_v2())
  87                 __raw_writel(0, timer_base + V2_IR);
  88         else {
  89                 tmp = __raw_readl(timer_base + MXC_TCTL);
  90                 __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL);
  91         }
  92 }
  93
  94 static inline void gpt_irq_enable(void)
  95 {
  96         if (timer_is_v2())
  97                 __raw_writel(1<<0, timer_base + V2_IR);
  98         else {
  99                 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
 100                         timer_base + MXC_TCTL);
 101         }
 102 }
 103
 104 static void gpt_irq_acknowledge(void)
 105 {
 106         if (timer_is_v1()) {
 107                 if (cpu_is_mx1())
 108                         __raw_writel(0, timer_base + MX1_2_TSTAT);
 109                 else
 110                         __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
 111                                 timer_base + MX1_2_TSTAT);
 112         } else if (timer_is_v2())
 113                 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
 114 }
 115
 116 static void __iomem *sched_clock_reg;
 117
 118 static u64 notrace mxc_read_sched_clock(void)
 119 {
 120         return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
 121 }
 122
 123 static struct delay_timer imx_delay_timer;
 124
 125 static unsigned long imx_read_current_timer(void)
 126 {
 127         return __raw_readl(sched_clock_reg);
 128 }
 129
 130 static int __init mxc_clocksource_init(struct clk *timer_clk)
 131 {
 132         unsigned int c = clk_get_rate(timer_clk);
 133         void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
 134
 135         imx_delay_timer.read_current_timer = &imx_read_current_timer;
 136         imx_delay_timer.freq = c;
 137         register_current_timer_delay(&imx_delay_timer);
 138
 139         sched_clock_reg = reg;
 140
 141         sched_clock_register(mxc_read_sched_clock, 32, c);
 142         return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
 143                         clocksource_mmio_readl_up);
 144 }
 145
 146 /* clock event */
 147
 148 static int mx1_2_set_next_event(unsigned long evt,
 149                               struct clock_event_device *unused)
 150 {
 151         unsigned long tcmp;
 152
 153         tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt;
 154
 155         __raw_writel(tcmp, timer_base + MX1_2_TCMP);
 156
 157         return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ?
 158                                 -ETIME : 0;
 159 }
 160
 161 static int v2_set_next_event(unsigned long evt,
 162                               struct clock_event_device *unused)
 163 {
 164         unsigned long tcmp;
 165
 166         tcmp = __raw_readl(timer_base + V2_TCN) + evt;
 167
 168         __raw_writel(tcmp, timer_base + V2_TCMP);
 169
 170         return evt < 0x7fffffff &&
 171                 (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ?
 172                                 -ETIME : 0;
 173 }
 174
 175 #ifdef DEBUG
 176 static const char *clock_event_mode_label[] = {
 177         [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
 178         [CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
 179         [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
 180         [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED",
 181         [CLOCK_EVT_MODE_RESUME]   = "CLOCK_EVT_MODE_RESUME",
 182 };
 183 #endif /* DEBUG */
 184
 185 static void mxc_set_mode(enum clock_event_mode mode,
 186                                 struct clock_event_device *evt)
 187 {
 188         unsigned long flags;
 189
 190         /*
 191          * The timer interrupt generation is disabled at least
 192          * for enough time to call mxc_set_next_event()
 193          */
 194         local_irq_save(flags);
 195
 196         /* Disable interrupt in GPT module */
 197         gpt_irq_disable();
 198
 199         if (mode != clockevent_mode) {
 200                 /* Set event time into far-far future */
 201                 if (timer_is_v2())
 202                         __raw_writel(__raw_readl(timer_base + V2_TCN) - 3,
 203                                         timer_base + V2_TCMP);
 204                 else
 205                         __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3,
 206                                         timer_base + MX1_2_TCMP);
 207
 208                 /* Clear pending interrupt */
 209                 gpt_irq_acknowledge();
 210         }
 211
 212 #ifdef DEBUG
 213         printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
 214                 clock_event_mode_label[clockevent_mode],
 215                 clock_event_mode_label[mode]);
 216 #endif /* DEBUG */
 217
 218         /* Remember timer mode */
 219         clockevent_mode = mode;
 220         local_irq_restore(flags);
 221
 222         switch (mode) {
 223         case CLOCK_EVT_MODE_PERIODIC:
 224                 printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
 225                                 "supported for i.MX\n");
 226                 break;
 227         case CLOCK_EVT_MODE_ONESHOT:
 228         /*
 229          * Do not put overhead of interrupt enable/disable into
 230          * mxc_set_next_event(), the core has about 4 minutes
 231          * to call mxc_set_next_event() or shutdown clock after
 232          * mode switching
 233          */
 234                 local_irq_save(flags);
 235                 gpt_irq_enable();
 236                 local_irq_restore(flags);
 237                 break;
 238         case CLOCK_EVT_MODE_SHUTDOWN:
 239         case CLOCK_EVT_MODE_UNUSED:
 240         case CLOCK_EVT_MODE_RESUME:
 241                 /* Left event sources disabled, no more interrupts appear */
 242                 break;
 243         }
 244 }
 245
 246 /*
 247  * IRQ handler for the timer
 248  */
 249 static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
 250 {
 251         struct clock_event_device *evt = &clockevent_mxc;
 252         uint32_t tstat;
 253
 254         if (timer_is_v2())
 255                 tstat = __raw_readl(timer_base + V2_TSTAT);
 256         else
 257                 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
 258
 259         gpt_irq_acknowledge();
 260
 261         evt->event_handler(evt);
 262
 263         return IRQ_HANDLED;
 264 }
 265
 266 static struct irqaction mxc_timer_irq = {
 267         .name           = "i.MX Timer Tick",
 268         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
 269         .handler        = mxc_timer_interrupt,
 270 };
 271
 272 static struct clock_event_device clockevent_mxc = {
 273         .name           = "mxc_timer1",
 274         .features       = CLOCK_EVT_FEAT_ONESHOT,
 275         .set_mode       = mxc_set_mode,
 276         .set_next_event = mx1_2_set_next_event,
 277         .rating         = 200,
 278 };
 279
 280 static int __init mxc_clockevent_init(struct clk *timer_clk)
 281 {
 282         if (timer_is_v2())
 283                 clockevent_mxc.set_next_event = v2_set_next_event;
 284
 285         clockevent_mxc.cpumask = cpumask_of(0);
 286         clockevents_config_and_register(&clockevent_mxc,
 287                                         clk_get_rate(timer_clk),
 288                                         0xff, 0xfffffffe);
 289
 290         return 0;
 291 }
 292
 293 static void __init _mxc_timer_init(int irq,
 294                                    struct clk *clk_per, struct clk *clk_ipg)
 295 {
 296         uint32_t tctl_val;
 297
 298         if (IS_ERR(clk_per)) {
 299                 pr_err("i.MX timer: unable to get clk\n");
 300                 return;
 301         }
 302
 303         if (!IS_ERR(clk_ipg))
 304                 clk_prepare_enable(clk_ipg);
 305
 306         clk_prepare_enable(clk_per);
 307
 308         /*
 309          * Initialise to a known state (all timers off, and timing reset)
 310          */
 311
 312         __raw_writel(0, timer_base + MXC_TCTL);
 313         __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
 314
 315         if (timer_is_v2())
 316                 tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
 317         else
 318                 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
 319
 320         __raw_writel(tctl_val, timer_base + MXC_TCTL);
 321
 322         /* init and register the timer to the framework */
 323         mxc_clocksource_init(clk_per);
 324         mxc_clockevent_init(clk_per);
 325
 326         /* Make irqs happen */
 327         setup_irq(irq, &mxc_timer_irq);
 328 }
 329
 330 void __init mxc_timer_init(void __iomem *base, int irq)
 331 {
 332         struct clk *clk_per = clk_get_sys("imx-gpt.0", "per");
 333         struct clk *clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
 334
 335         timer_base = base;
 336
 337         _mxc_timer_init(irq, clk_per, clk_ipg);
 338 }
 339
 340 static void __init mxc_timer_init_dt(struct device_node *np)
 341 {
 342         struct clk *clk_per, *clk_ipg;
 343         int irq;
 344
 345         if (timer_base)
 346                 return;
 347
 348         timer_base = of_iomap(np, 0);
 349         WARN_ON(!timer_base);
 350         irq = irq_of_parse_and_map(np, 0);
 351
 352         clk_per = of_clk_get_by_name(np, "per");
 353         clk_ipg = of_clk_get_by_name(np, "ipg");
 354
 355         _mxc_timer_init(irq, clk_per, clk_ipg);
 356 }
 357 CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt);
 358 CLOCKSOURCE_OF_DECLARE(mx25_timer, "fsl,imx25-gpt", mxc_timer_init_dt);
 359 CLOCKSOURCE_OF_DECLARE(mx50_timer, "fsl,imx50-gpt", mxc_timer_init_dt);
 360 CLOCKSOURCE_OF_DECLARE(mx51_timer, "fsl,imx51-gpt", mxc_timer_init_dt);
 361 CLOCKSOURCE_OF_DECLARE(mx53_timer, "fsl,imx53-gpt", mxc_timer_init_dt);
 362 CLOCKSOURCE_OF_DECLARE(mx6q_timer, "fsl,imx6q-gpt", mxc_timer_init_dt);
 363 CLOCKSOURCE_OF_DECLARE(mx6sl_timer, "fsl,imx6sl-gpt", mxc_timer_init_dt);
 364 CLOCKSOURCE_OF_DECLARE(mx6sx_timer, "fsl,imx6sx-gpt", mxc_timer_init_dt);