arch/arm/mach-integrator/integrator_ap.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_ap.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/syscore_ops.h>
  23 #include <linux/amba/bus.h>
  24 #include <linux/io.h>
  25 #include <linux/irqchip.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/termios.h>
  30 #include <linux/mfd/syscon.h>
  31 #include <linux/regmap.h>
  32
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/map.h>
  35
  36 #include "hardware.h"
  37 #include "cm.h"
  38 #include "common.h"
  39 #include "lm.h"
  40
  41 /* Regmap to the AP system controller */
  42 static struct regmap *ap_syscon_map;
  43
  44 /*
  45  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  46  * is the (PA >> 12).
  47  *
  48  * Setup a VA for the Integrator interrupt controller (for header #0,
  49  * just for now).
  50  */
  51 #define VA_IC_BASE      __io_address(INTEGRATOR_IC_BASE)
  52
  53 /*
  54  * Logical      Physical
  55  * f1400000     14000000        Interrupt controller
  56  * f1600000     16000000        UART 0
  57  */
  58
  59 static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
  60         {
  61                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
  62                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
  63                 .length         = SZ_4K,
  64                 .type           = MT_DEVICE
  65         }, {
  66                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
  67                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
  68                 .length         = SZ_4K,
  69                 .type           = MT_DEVICE
  70         }
  71 };
  72
  73 static void __init ap_map_io(void)
  74 {
  75         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
  76 }
  77
  78 #ifdef CONFIG_PM
  79 static unsigned long ic_irq_enable;
  80
  81 static int irq_suspend(void)
  82 {
  83         ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
  84         return 0;
  85 }
  86
  87 static void irq_resume(void)
  88 {
  89         /* disable all irq sources */
  90         cm_clear_irqs();
  91         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
  92         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
  93
  94         writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
  95 }
  96 #else
  97 #define irq_suspend NULL
  98 #define irq_resume NULL
  99 #endif
 100
 101 static struct syscore_ops irq_syscore_ops = {
 102         .suspend        = irq_suspend,
 103         .resume         = irq_resume,
 104 };
 105
 106 static int __init irq_syscore_init(void)
 107 {
 108         register_syscore_ops(&irq_syscore_ops);
 109
 110         return 0;
 111 }
 112
 113 device_initcall(irq_syscore_init);
 114
 115 /*
 116  * For the PL010 found in the Integrator/AP some of the UART control is
 117  * implemented in the system controller and accessed using a callback
 118  * from the driver.
 119  */
 120 static void integrator_uart_set_mctrl(struct amba_device *dev,
 121                                 void __iomem *base, unsigned int mctrl)
 122 {
 123         unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
 124         u32 phybase = dev->res.start;
 125         int ret;
 126
 127         if (phybase == INTEGRATOR_UART0_BASE) {
 128                 /* UART0 */
 129                 rts_mask = 1 << 4;
 130                 dtr_mask = 1 << 5;
 131         } else {
 132                 /* UART1 */
 133                 rts_mask = 1 << 6;
 134                 dtr_mask = 1 << 7;
 135         }
 136
 137         if (mctrl & TIOCM_RTS)
 138                 ctrlc |= rts_mask;
 139         else
 140                 ctrls |= rts_mask;
 141
 142         if (mctrl & TIOCM_DTR)
 143                 ctrlc |= dtr_mask;
 144         else
 145                 ctrls |= dtr_mask;
 146
 147         ret = regmap_write(ap_syscon_map,
 148                            INTEGRATOR_SC_CTRLS_OFFSET,
 149                            ctrls);
 150         if (ret)
 151                 pr_err("MODEM: unable to write PL010 UART CTRLS\n");
 152
 153         ret = regmap_write(ap_syscon_map,
 154                            INTEGRATOR_SC_CTRLC_OFFSET,
 155                            ctrlc);
 156         if (ret)
 157                 pr_err("MODEM: unable to write PL010 UART CRTLC\n");
 158 }
 159
 160 struct amba_pl010_data ap_uart_data = {
 161         .set_mctrl = integrator_uart_set_mctrl,
 162 };
 163
 164 void __init ap_init_early(void)
 165 {
 166 }
 167
 168 static void __init ap_init_irq_of(void)
 169 {
 170         cm_init();
 171         irqchip_init();
 172 }
 173
 174 /* For the Device Tree, add in the UART callbacks as AUXDATA */
 175 static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
 176         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
 177                 "uart0", &ap_uart_data),
 178         OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
 179                 "uart1", &ap_uart_data),
 180         { /* sentinel */ },
 181 };
 182
 183 static const struct of_device_id ap_syscon_match[] = {
 184         { .compatible = "arm,integrator-ap-syscon"},
 185         { },
 186 };
 187
 188 static void __init ap_init_of(void)
 189 {
 190         u32 sc_dec;
 191         struct device_node *syscon;
 192         int ret;
 193         int i;
 194
 195         of_platform_default_populate(NULL, ap_auxdata_lookup, NULL);
 196
 197         syscon = of_find_matching_node(NULL, ap_syscon_match);
 198         if (!syscon)
 199                 return;
 200         ap_syscon_map = syscon_node_to_regmap(syscon);
 201         if (IS_ERR(ap_syscon_map)) {
 202                 pr_crit("could not find Integrator/AP system controller\n");
 203                 return;
 204         }
 205
 206         ret = regmap_read(ap_syscon_map,
 207                           INTEGRATOR_SC_DEC_OFFSET,
 208                           &sc_dec);
 209         if (ret) {
 210                 pr_crit("could not read from Integrator/AP syscon\n");
 211                 return;
 212         }
 213
 214         for (i = 0; i < 4; i++) {
 215                 struct lm_device *lmdev;
 216
 217                 if ((sc_dec & (16 << i)) == 0)
 218                         continue;
 219
 220                 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
 221                 if (!lmdev)
 222                         continue;
 223
 224                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
 225                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
 226                 lmdev->resource.flags = IORESOURCE_MEM;
 227                 lmdev->irq = irq_of_parse_and_map(syscon, i);
 228                 lmdev->id = i;
 229
 230                 lm_device_register(lmdev);
 231         }
 232 }
 233
 234 static const char * ap_dt_board_compat[] = {
 235         "arm,integrator-ap",
 236         NULL,
 237 };
 238
 239 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
 240         .reserve        = integrator_reserve,
 241         .map_io         = ap_map_io,
 242         .init_early     = ap_init_early,
 243         .init_irq       = ap_init_irq_of,
 244         .init_machine   = ap_init_of,
 245         .dt_compat      = ap_dt_board_compat,
 246 MACHINE_END