arch/arm/mach-iop13xx/msi.c

   1 /*
   2  * arch/arm/mach-iop13xx/msi.c
   3  *
   4  * PCI MSI support for the iop13xx processor
   5  *
   6  * Copyright (c) 2006, Intel Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  19  * Place - Suite 330, Boston, MA 02111-1307 USA.
  20  *
  21  */
  22 #include <linux/pci.h>
  23 #include <linux/msi.h>
  24 #include <asm/mach/irq.h>
  25 #include <asm/irq.h>
  26 #include <mach/irqs.h>
  27
  28 /* IMIPR0 CP6 R8 Page 1
  29  */
  30 static u32 read_imipr_0(void)
  31 {
  32         u32 val;
  33         asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
  34         return val;
  35 }
  36 static void write_imipr_0(u32 val)
  37 {
  38         asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
  39 }
  40
  41 /* IMIPR1 CP6 R9 Page 1
  42  */
  43 static u32 read_imipr_1(void)
  44 {
  45         u32 val;
  46         asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
  47         return val;
  48 }
  49 static void write_imipr_1(u32 val)
  50 {
  51         asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
  52 }
  53
  54 /* IMIPR2 CP6 R10 Page 1
  55  */
  56 static u32 read_imipr_2(void)
  57 {
  58         u32 val;
  59         asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
  60         return val;
  61 }
  62 static void write_imipr_2(u32 val)
  63 {
  64         asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
  65 }
  66
  67 /* IMIPR3 CP6 R11 Page 1
  68  */
  69 static u32 read_imipr_3(void)
  70 {
  71         u32 val;
  72         asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
  73         return val;
  74 }
  75 static void write_imipr_3(u32 val)
  76 {
  77         asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
  78 }
  79
  80 static u32 (*read_imipr[])(void) = {
  81         read_imipr_0,
  82         read_imipr_1,
  83         read_imipr_2,
  84         read_imipr_3,
  85 };
  86
  87 static void (*write_imipr[])(u32) = {
  88         write_imipr_0,
  89         write_imipr_1,
  90         write_imipr_2,
  91         write_imipr_3,
  92 };
  93
  94 static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc)
  95 {
  96         int i, j;
  97         unsigned long status;
  98
  99         /* read IMIPR registers and find any active interrupts,
 100          * then call ISR for each active interrupt
 101          */
 102         for (i = 0; i < ARRAY_SIZE(read_imipr); i++) {
 103                 status = (read_imipr[i])();
 104                 if (!status)
 105                         continue;
 106
 107                 do {
 108                         j = find_first_bit(&status, 32);
 109                         (write_imipr[i])(1 << j); /* write back to clear bit */
 110                         generic_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i));
 111                         status = (read_imipr[i])();
 112                 } while (status);
 113         }
 114 }
 115
 116 void __init iop13xx_msi_init(void)
 117 {
 118         irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
 119 }
 120
 121 static void iop13xx_msi_nop(struct irq_data *d)
 122 {
 123         return;
 124 }
 125
 126 static struct irq_chip iop13xx_msi_chip = {
 127         .name = "PCI-MSI",
 128         .irq_ack = iop13xx_msi_nop,
 129         .irq_enable = pci_msi_unmask_irq,
 130         .irq_disable = pci_msi_mask_irq,
 131         .irq_mask = pci_msi_mask_irq,
 132         .irq_unmask = pci_msi_unmask_irq,
 133 };
 134
 135 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
 136 {
 137         int id, irq = irq_alloc_desc_from(IRQ_IOP13XX_MSI_0, -1);
 138         struct msi_msg msg;
 139
 140         if (irq < 0)
 141                 return irq;
 142
 143         if (irq >= NR_IOP13XX_IRQS) {
 144                 irq_free_desc(irq);
 145                 return -ENOSPC;
 146         }
 147
 148         irq_set_msi_desc(irq, desc);
 149
 150         msg.address_hi = 0x0;
 151         msg.address_lo = IOP13XX_MU_MIMR_PCI;
 152
 153         id = iop13xx_cpu_id();
 154         msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f);
 155
 156         pci_write_msi_msg(irq, &msg);
 157         irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
 158
 159         return 0;
 160 }
 161
 162 void arch_teardown_msi_irq(unsigned int irq)
 163 {
 164         irq_free_desc(irq);
 165 }