1 /* arch/arm/mach-lh7a40x/arch-lpd7a40x.c
3 * Copyright (C) 2004 Logic Product Development
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
11 #include <linux/tty.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
17 #include <asm/hardware.h>
18 #include <asm/setup.h>
19 #include <asm/mach-types.h>
20 #include <asm/mach/arch.h>
22 #include <asm/mach/irq.h>
23 #include <asm/mach/map.h>
27 #define CPLD_INT_NETHERNET (1<<0)
28 #define CPLD_INTMASK_ETHERNET (1<<2)
29 #if defined (CONFIG_MACH_LPD7A400)
30 # define CPLD_INT_NTOUCH (1<<1)
31 # define CPLD_INTMASK_TOUCH (1<<3)
32 # define CPLD_INT_PEN (1<<4)
33 # define CPLD_INTMASK_PEN (1<<4)
34 # define CPLD_INT_PIRQ (1<<4)
36 #define CPLD_INTMASK_CPLD (1<<7)
37 #define CPLD_INT_CPLD (1<<6)
39 #define CPLD_CONTROL_SWINT (1<<7) /* Disable all CPLD IRQs */
40 #define CPLD_CONTROL_OCMSK (1<<6) /* Mask USB1 connect IRQ */
41 #define CPLD_CONTROL_PDRV (1<<5) /* PCC_nDRV high */
42 #define CPLD_CONTROL_USB1C (1<<4) /* USB1 connect IRQ active */
43 #define CPLD_CONTROL_USB1P (1<<3) /* USB1 power disable */
44 #define CPLD_CONTROL_AWKP (1<<2) /* Auto-wakeup disabled */
45 #define CPLD_CONTROL_LCD_ENABLE (1<<1) /* LCD Vee enable */
46 #define CPLD_CONTROL_WRLAN_NENABLE (1<<0) /* SMC91x power disable */
49 static struct resource smc91x_resources
[] = {
52 .end
= CPLD00_PHYS
+ CPLD00_SIZE
- 1, /* Only needs 16B */
53 .flags
= IORESOURCE_MEM
,
57 .start
= IRQ_LPD7A40X_ETH_INT
,
58 .end
= IRQ_LPD7A40X_ETH_INT
,
59 .flags
= IORESOURCE_IRQ
,
64 static struct platform_device smc91x_device
= {
67 .num_resources
= ARRAY_SIZE(smc91x_resources
),
68 .resource
= smc91x_resources
,
71 static struct resource lh7a40x_usbclient_resources
[] = {
74 .end
= (USB_PHYS
+ PAGE_SIZE
),
75 .flags
= IORESOURCE_MEM
,
80 .flags
= IORESOURCE_IRQ
,
84 static u64 lh7a40x_usbclient_dma_mask
= 0xffffffffUL
;
86 static struct platform_device lh7a40x_usbclient_device
= {
87 // .name = "lh7a40x_udc",
91 .dma_mask
= &lh7a40x_usbclient_dma_mask
,
92 .coherent_dma_mask
= 0xffffffffUL
,
94 .num_resources
= ARRAY_SIZE (lh7a40x_usbclient_resources
),
95 .resource
= lh7a40x_usbclient_resources
,
98 #if defined (CONFIG_ARCH_LH7A404)
100 static struct resource lh7a404_usbhost_resources
[] = {
103 .end
= (USBH_PHYS
+ 0xFF),
104 .flags
= IORESOURCE_MEM
,
107 .start
= IRQ_USHINTR
,
109 .flags
= IORESOURCE_IRQ
,
113 static u64 lh7a404_usbhost_dma_mask
= 0xffffffffUL
;
115 static struct platform_device lh7a404_usbhost_device
= {
116 .name
= "lh7a404-ohci",
119 .dma_mask
= &lh7a404_usbhost_dma_mask
,
120 .coherent_dma_mask
= 0xffffffffUL
,
122 .num_resources
= ARRAY_SIZE (lh7a404_usbhost_resources
),
123 .resource
= lh7a404_usbhost_resources
,
128 static struct platform_device
* lpd7a40x_devs
[] __initdata
= {
130 &lh7a40x_usbclient_device
,
131 #if defined (CONFIG_ARCH_LH7A404)
132 &lh7a404_usbhost_device
,
136 extern void lpd7a400_map_io (void);
138 static void __init
lpd7a40x_init (void)
140 #if defined (CONFIG_MACH_LPD7A400)
142 | CPLD_CONTROL_SWINT
/* Disable software interrupt */
143 | CPLD_CONTROL_OCMSK
; /* Mask USB1 connection IRQ */
145 | CPLD_CONTROL_LCD_ENABLE
/* Disable LCD */
146 | CPLD_CONTROL_WRLAN_NENABLE
/* Enable SMC91x */
150 #if defined (CONFIG_MACH_LPD7A404)
152 | CPLD_CONTROL_WRLAN_NENABLE
/* Enable SMC91x */
156 platform_add_devices (lpd7a40x_devs
, ARRAY_SIZE (lpd7a40x_devs
));
157 #if defined (CONFIG_FB_ARMCLCD)
158 lh7a40x_clcd_init ();
162 static void lh7a40x_ack_cpld_irq (u32 irq
)
164 /* CPLD doesn't have ack capability, but some devices may */
166 #if defined (CPLD_INTMASK_TOUCH)
167 /* The touch control *must* mask the the interrupt because the
168 * interrupt bit is read by the driver to determine if the pen
170 if (irq
== IRQ_TOUCH
)
171 CPLD_INTERRUPTS
|= CPLD_INTMASK_TOUCH
;
175 static void lh7a40x_mask_cpld_irq (u32 irq
)
178 case IRQ_LPD7A40X_ETH_INT
:
179 CPLD_INTERRUPTS
|= CPLD_INTMASK_ETHERNET
;
181 #if defined (IRQ_TOUCH)
183 CPLD_INTERRUPTS
|= CPLD_INTMASK_TOUCH
;
189 static void lh7a40x_unmask_cpld_irq (u32 irq
)
192 case IRQ_LPD7A40X_ETH_INT
:
193 CPLD_INTERRUPTS
&= ~CPLD_INTMASK_ETHERNET
;
195 #if defined (IRQ_TOUCH)
197 CPLD_INTERRUPTS
&= ~CPLD_INTMASK_TOUCH
;
203 static struct irq_chip lpd7a40x_cpld_chip
= {
205 .ack
= lh7a40x_ack_cpld_irq
,
206 .mask
= lh7a40x_mask_cpld_irq
,
207 .unmask
= lh7a40x_unmask_cpld_irq
,
210 static void lpd7a40x_cpld_handler (unsigned int irq
, struct irqdesc
*desc
,
211 struct pt_regs
*regs
)
213 unsigned int mask
= CPLD_INTERRUPTS
;
215 desc
->chip
->ack (irq
);
217 if ((mask
& (1<<0)) == 0) /* WLAN */
218 IRQ_DISPATCH (IRQ_LPD7A40X_ETH_INT
);
220 #if defined (IRQ_TOUCH)
221 if ((mask
& (1<<1)) == 0) /* Touch */
222 IRQ_DISPATCH (IRQ_TOUCH
);
225 desc
->chip
->unmask (irq
); /* Level-triggered need this */
229 void __init
lh7a40x_init_board_irq (void)
233 /* Rev A (v2.8): PF0, PF1, PF2, and PF3 are available IRQs.
234 PF7 supports the CPLD.
235 Rev B (v3.4): PF0, PF1, and PF2 are available IRQs.
236 PF3 supports the CPLD.
237 (Some) LPD7A404 prerelease boards report a version
238 number of 0x16, but we force an override since the
239 hardware is of the newer variety.
242 unsigned char cpld_version
= CPLD_REVISION
;
243 int pinCPLD
= (cpld_version
== 0x28) ? 7 : 3;
245 #if defined CONFIG_MACH_LPD7A404
246 cpld_version
= 0x34; /* Coerce LPD7A404 to RevB */
249 /* First, configure user controlled GPIOF interrupts */
251 GPIO_PFDD
&= ~0x0f; /* PF0-3 are inputs */
252 GPIO_INTTYPE1
&= ~0x0f; /* PF0-3 are level triggered */
253 GPIO_INTTYPE2
&= ~0x0f; /* PF0-3 are active low */
255 GPIO_GPIOFINTEN
|= 0x0f; /* Enable PF0, PF1, PF2, and PF3 IRQs */
257 /* Then, configure CPLD interrupt */
259 /* Disable all CPLD interrupts */
260 #if defined (CONFIG_MACH_LPD7A400)
261 CPLD_INTERRUPTS
= CPLD_INTMASK_TOUCH
| CPLD_INTMASK_PEN
262 | CPLD_INTMASK_ETHERNET
;
263 /* *** FIXME: don't know why we need 7 and 4. 7 is way wrong
264 and 4 is uncefined. */
265 // (1<<7)|(1<<4)|(1<<3)|(1<<2);
267 #if defined (CONFIG_MACH_LPD7A404)
268 CPLD_INTERRUPTS
= CPLD_INTMASK_ETHERNET
;
269 /* *** FIXME: don't know why we need 6 and 5, neither is defined. */
270 // (1<<6)|(1<<5)|(1<<3);
272 GPIO_PFDD
&= ~(1 << pinCPLD
); /* Make input */
273 GPIO_INTTYPE1
&= ~(1 << pinCPLD
); /* Level triggered */
274 GPIO_INTTYPE2
&= ~(1 << pinCPLD
); /* Active low */
276 GPIO_GPIOFINTEN
|= (1 << pinCPLD
); /* Enable */
278 /* Cascade CPLD interrupts */
280 for (irq
= IRQ_BOARD_START
;
281 irq
< IRQ_BOARD_START
+ NR_IRQ_BOARD
; ++irq
) {
282 set_irq_chip (irq
, &lpd7a40x_cpld_chip
);
283 set_irq_handler (irq
, do_level_IRQ
);
284 set_irq_flags (irq
, IRQF_VALID
);
287 set_irq_chained_handler ((cpld_version
== 0x28)
290 lpd7a40x_cpld_handler
);
293 static struct map_desc lpd7a40x_io_desc
[] __initdata
= {
296 .pfn
= __phys_to_pfn(IO_PHYS
),
300 { /* Mapping added to work around chip select problems */
301 .virtual = IOBARRIER_VIRT
,
302 .pfn
= __phys_to_pfn(IOBARRIER_PHYS
),
303 .length
= IOBARRIER_SIZE
,
308 .pfn
= __phys_to_pfn(CF_PHYS
),
313 .virtual = CPLD02_VIRT
,
314 .pfn
= __phys_to_pfn(CPLD02_PHYS
),
315 .length
= CPLD02_SIZE
,
319 .virtual = CPLD06_VIRT
,
320 .pfn
= __phys_to_pfn(CPLD06_PHYS
),
321 .length
= CPLD06_SIZE
,
325 .virtual = CPLD08_VIRT
,
326 .pfn
= __phys_to_pfn(CPLD08_PHYS
),
327 .length
= CPLD08_SIZE
,
331 .virtual = CPLD08_VIRT
,
332 .pfn
= __phys_to_pfn(CPLD08_PHYS
),
333 .length
= CPLD08_SIZE
,
337 .virtual = CPLD0A_VIRT
,
338 .pfn
= __phys_to_pfn(CPLD0A_PHYS
),
339 .length
= CPLD0A_SIZE
,
343 .virtual = CPLD0C_VIRT
,
344 .pfn
= __phys_to_pfn(CPLD0C_PHYS
),
345 .length
= CPLD0C_SIZE
,
349 .virtual = CPLD0E_VIRT
,
350 .pfn
= __phys_to_pfn(CPLD0E_PHYS
),
351 .length
= CPLD0E_SIZE
,
355 .virtual = CPLD10_VIRT
,
356 .pfn
= __phys_to_pfn(CPLD10_PHYS
),
357 .length
= CPLD10_SIZE
,
361 .virtual = CPLD12_VIRT
,
362 .pfn
= __phys_to_pfn(CPLD12_PHYS
),
363 .length
= CPLD12_SIZE
,
367 .virtual = CPLD14_VIRT
,
368 .pfn
= __phys_to_pfn(CPLD14_PHYS
),
369 .length
= CPLD14_SIZE
,
373 .virtual = CPLD16_VIRT
,
374 .pfn
= __phys_to_pfn(CPLD16_PHYS
),
375 .length
= CPLD16_SIZE
,
379 .virtual = CPLD18_VIRT
,
380 .pfn
= __phys_to_pfn(CPLD18_PHYS
),
381 .length
= CPLD18_SIZE
,
385 .virtual = CPLD1A_VIRT
,
386 .pfn
= __phys_to_pfn(CPLD1A_PHYS
),
387 .length
= CPLD1A_SIZE
,
393 lpd7a40x_map_io(void)
395 iotable_init (lpd7a40x_io_desc
, ARRAY_SIZE (lpd7a40x_io_desc
));
398 #ifdef CONFIG_MACH_LPD7A400
400 MACHINE_START (LPD7A400
, "Logic Product Development LPD7A400-10")
401 /* Maintainer: Marc Singer */
402 .phys_io
= 0x80000000,
403 .io_pg_offst
= ((io_p2v (0x80000000))>>18) & 0xfffc,
404 .boot_params
= 0xc0000100,
405 .map_io
= lpd7a40x_map_io
,
406 .init_irq
= lh7a400_init_irq
,
407 .timer
= &lh7a40x_timer
,
408 .init_machine
= lpd7a40x_init
,
413 #ifdef CONFIG_MACH_LPD7A404
415 MACHINE_START (LPD7A404
, "Logic Product Development LPD7A404-10")
416 /* Maintainer: Marc Singer */
417 .phys_io
= 0x80000000,
418 .io_pg_offst
= ((io_p2v (0x80000000))>>18) & 0xfffc,
419 .boot_params
= 0xc0000100,
420 .map_io
= lpd7a40x_map_io
,
421 .init_irq
= lh7a404_init_irq
,
422 .timer
= &lh7a40x_timer
,
423 .init_machine
= lpd7a40x_init
,