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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - arch/arm/mach-mmp/clock-mmp2.c
1 #include <linux/module.h>
2 #include <linux/kernel.h>
3 #include <linux/init.h>
4 #include <linux/list.h>
8 #include <mach/addr-map.h>
14 * APB Clock register offsets for MMP2
16 #define APBC_RTC APBC_REG(0x000)
17 #define APBC_TWSI1 APBC_REG(0x004)
18 #define APBC_TWSI2 APBC_REG(0x008)
19 #define APBC_TWSI3 APBC_REG(0x00c)
20 #define APBC_TWSI4 APBC_REG(0x010)
21 #define APBC_KPC APBC_REG(0x018)
22 #define APBC_UART1 APBC_REG(0x02c)
23 #define APBC_UART2 APBC_REG(0x030)
24 #define APBC_UART3 APBC_REG(0x034)
25 #define APBC_GPIO APBC_REG(0x038)
26 #define APBC_PWM0 APBC_REG(0x03c)
27 #define APBC_PWM1 APBC_REG(0x040)
28 #define APBC_PWM2 APBC_REG(0x044)
29 #define APBC_PWM3 APBC_REG(0x048)
30 #define APBC_SSP0 APBC_REG(0x04c)
31 #define APBC_SSP1 APBC_REG(0x050)
32 #define APBC_SSP2 APBC_REG(0x054)
33 #define APBC_SSP3 APBC_REG(0x058)
34 #define APBC_SSP4 APBC_REG(0x05c)
35 #define APBC_SSP5 APBC_REG(0x060)
36 #define APBC_TWSI5 APBC_REG(0x07c)
37 #define APBC_TWSI6 APBC_REG(0x080)
38 #define APBC_UART4 APBC_REG(0x088)
40 #define APMU_USB APMU_REG(0x05c)
41 #define APMU_NAND APMU_REG(0x060)
42 #define APMU_SDH0 APMU_REG(0x054)
43 #define APMU_SDH1 APMU_REG(0x058)
44 #define APMU_SDH2 APMU_REG(0x0e8)
45 #define APMU_SDH3 APMU_REG(0x0ec)
47 static void sdhc_clk_enable(struct clk
*clk
)
51 clk_rst
= __raw_readl(clk
->clk_rst
);
52 clk_rst
|= clk
->enable_val
;
53 __raw_writel(clk_rst
, clk
->clk_rst
);
56 static void sdhc_clk_disable(struct clk
*clk
)
60 clk_rst
= __raw_readl(clk
->clk_rst
);
61 clk_rst
&= ~clk
->enable_val
;
62 __raw_writel(clk_rst
, clk
->clk_rst
);
65 struct clkops sdhc_clk_ops
= {
66 .enable
= sdhc_clk_enable
,
67 .disable
= sdhc_clk_disable
,
70 /* APB peripheral clocks */
71 static APBC_CLK(uart1
, UART1
, 1, 26000000);
72 static APBC_CLK(uart2
, UART2
, 1, 26000000);
73 static APBC_CLK(uart3
, UART3
, 1, 26000000);
74 static APBC_CLK(uart4
, UART4
, 1, 26000000);
75 static APBC_CLK(twsi1
, TWSI1
, 0, 26000000);
76 static APBC_CLK(twsi2
, TWSI2
, 0, 26000000);
77 static APBC_CLK(twsi3
, TWSI3
, 0, 26000000);
78 static APBC_CLK(twsi4
, TWSI4
, 0, 26000000);
79 static APBC_CLK(twsi5
, TWSI5
, 0, 26000000);
80 static APBC_CLK(twsi6
, TWSI6
, 0, 26000000);
81 static APBC_CLK(gpio
, GPIO
, 0, 26000000);
83 static APMU_CLK(nand
, NAND
, 0xbf, 100000000);
84 static APMU_CLK_OPS(sdh0
, SDH0
, 0x1b, 200000000, &sdhc_clk_ops
);
85 static APMU_CLK_OPS(sdh1
, SDH1
, 0x1b, 200000000, &sdhc_clk_ops
);
86 static APMU_CLK_OPS(sdh2
, SDH2
, 0x1b, 200000000, &sdhc_clk_ops
);
87 static APMU_CLK_OPS(sdh3
, SDH3
, 0x1b, 200000000, &sdhc_clk_ops
);
89 static struct clk_lookup mmp2_clkregs
[] = {
90 INIT_CLKREG(&clk_uart1
, "pxa2xx-uart.0", NULL
),
91 INIT_CLKREG(&clk_uart2
, "pxa2xx-uart.1", NULL
),
92 INIT_CLKREG(&clk_uart3
, "pxa2xx-uart.2", NULL
),
93 INIT_CLKREG(&clk_uart4
, "pxa2xx-uart.3", NULL
),
94 INIT_CLKREG(&clk_twsi1
, "pxa2xx-i2c.0", NULL
),
95 INIT_CLKREG(&clk_twsi2
, "pxa2xx-i2c.1", NULL
),
96 INIT_CLKREG(&clk_twsi3
, "pxa2xx-i2c.2", NULL
),
97 INIT_CLKREG(&clk_twsi4
, "pxa2xx-i2c.3", NULL
),
98 INIT_CLKREG(&clk_twsi5
, "pxa2xx-i2c.4", NULL
),
99 INIT_CLKREG(&clk_twsi6
, "pxa2xx-i2c.5", NULL
),
100 INIT_CLKREG(&clk_nand
, "pxa3xx-nand", NULL
),
101 INIT_CLKREG(&clk_gpio
, "mmp2-gpio", NULL
),
102 INIT_CLKREG(&clk_sdh0
, "sdhci-pxav3.0", "PXA-SDHCLK"),
103 INIT_CLKREG(&clk_sdh1
, "sdhci-pxav3.1", "PXA-SDHCLK"),
104 INIT_CLKREG(&clk_sdh2
, "sdhci-pxav3.2", "PXA-SDHCLK"),
105 INIT_CLKREG(&clk_sdh3
, "sdhci-pxav3.3", "PXA-SDHCLK"),
108 void __init
mmp2_clk_init(void)
110 clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs
));