2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
14 #include <linux/delay.h>
15 #include <linux/clk.h>
17 #include <linux/clkdev.h>
19 #include <asm/div64.h>
21 #include <mach/hardware.h>
22 #include <mach/common.h>
23 #include <mach/clock.h>
27 /* External clock values passed-in by the board code */
28 static unsigned long external_high_reference
, external_low_reference
;
29 static unsigned long oscillator_reference
, ckih2_reference
;
31 static struct clk osc_clk
;
32 static struct clk pll1_main_clk
;
33 static struct clk pll1_sw_clk
;
34 static struct clk pll2_sw_clk
;
35 static struct clk pll3_sw_clk
;
36 static struct clk lp_apm_clk
;
37 static struct clk periph_apm_clk
;
38 static struct clk ahb_clk
;
39 static struct clk ipg_clk
;
40 static struct clk usboh3_clk
;
42 #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
44 /* calculate best pre and post dividers to get the required divider */
45 static void __calc_pre_post_dividers(u32 div
, u32
*pre
, u32
*post
,
46 u32 max_pre
, u32 max_post
)
48 if (div
>= max_pre
* max_post
) {
51 } else if (div
>= max_pre
) {
52 u32 min_pre
, temp_pre
, old_err
, err
;
53 min_pre
= DIV_ROUND_UP(div
, max_post
);
55 for (temp_pre
= max_pre
; temp_pre
>= min_pre
; temp_pre
--) {
67 *post
= DIV_ROUND_UP(div
, *pre
);
74 static void _clk_ccgr_setclk(struct clk
*clk
, unsigned mode
)
76 u32 reg
= __raw_readl(clk
->enable_reg
);
78 reg
&= ~(MXC_CCM_CCGRx_CG_MASK
<< clk
->enable_shift
);
79 reg
|= mode
<< clk
->enable_shift
;
81 __raw_writel(reg
, clk
->enable_reg
);
84 static int _clk_ccgr_enable(struct clk
*clk
)
86 _clk_ccgr_setclk(clk
, MXC_CCM_CCGRx_MOD_ON
);
90 static void _clk_ccgr_disable(struct clk
*clk
)
92 _clk_ccgr_setclk(clk
, MXC_CCM_CCGRx_MOD_OFF
);
95 static int _clk_ccgr_enable_inrun(struct clk
*clk
)
97 _clk_ccgr_setclk(clk
, MXC_CCM_CCGRx_MOD_IDLE
);
101 static void _clk_ccgr_disable_inwait(struct clk
*clk
)
103 _clk_ccgr_setclk(clk
, MXC_CCM_CCGRx_MOD_IDLE
);
107 * For the 4-to-1 muxed input clock
109 static inline u32
_get_mux(struct clk
*parent
, struct clk
*m0
,
110 struct clk
*m1
, struct clk
*m2
, struct clk
*m3
)
114 else if (parent
== m1
)
116 else if (parent
== m2
)
118 else if (parent
== m3
)
126 static inline void __iomem
*_get_pll_base(struct clk
*pll
)
128 if (pll
== &pll1_main_clk
)
129 return MX51_DPLL1_BASE
;
130 else if (pll
== &pll2_sw_clk
)
131 return MX51_DPLL2_BASE
;
132 else if (pll
== &pll3_sw_clk
)
133 return MX51_DPLL3_BASE
;
140 static unsigned long clk_pll_get_rate(struct clk
*clk
)
142 long mfi
, mfn
, mfd
, pdf
, ref_clk
, mfn_abs
;
143 unsigned long dp_op
, dp_mfd
, dp_mfn
, dp_ctl
, pll_hfsm
, dbl
;
144 void __iomem
*pllbase
;
146 unsigned long parent_rate
;
148 parent_rate
= clk_get_rate(clk
->parent
);
150 pllbase
= _get_pll_base(clk
);
152 dp_ctl
= __raw_readl(pllbase
+ MXC_PLL_DP_CTL
);
153 pll_hfsm
= dp_ctl
& MXC_PLL_DP_CTL_HFSM
;
154 dbl
= dp_ctl
& MXC_PLL_DP_CTL_DPDCK0_2_EN
;
157 dp_op
= __raw_readl(pllbase
+ MXC_PLL_DP_OP
);
158 dp_mfd
= __raw_readl(pllbase
+ MXC_PLL_DP_MFD
);
159 dp_mfn
= __raw_readl(pllbase
+ MXC_PLL_DP_MFN
);
161 dp_op
= __raw_readl(pllbase
+ MXC_PLL_DP_HFS_OP
);
162 dp_mfd
= __raw_readl(pllbase
+ MXC_PLL_DP_HFS_MFD
);
163 dp_mfn
= __raw_readl(pllbase
+ MXC_PLL_DP_HFS_MFN
);
165 pdf
= dp_op
& MXC_PLL_DP_OP_PDF_MASK
;
166 mfi
= (dp_op
& MXC_PLL_DP_OP_MFI_MASK
) >> MXC_PLL_DP_OP_MFI_OFFSET
;
167 mfi
= (mfi
<= 5) ? 5 : mfi
;
168 mfd
= dp_mfd
& MXC_PLL_DP_MFD_MASK
;
169 mfn
= mfn_abs
= dp_mfn
& MXC_PLL_DP_MFN_MASK
;
170 /* Sign extend to 32-bits */
171 if (mfn
>= 0x04000000) {
176 ref_clk
= 2 * parent_rate
;
180 ref_clk
/= (pdf
+ 1);
181 temp
= (u64
) ref_clk
* mfn_abs
;
182 do_div(temp
, mfd
+ 1);
185 temp
= (ref_clk
* mfi
) + temp
;
190 static int _clk_pll_set_rate(struct clk
*clk
, unsigned long rate
)
193 void __iomem
*pllbase
;
195 long mfi
, pdf
, mfn
, mfd
= 999999;
197 unsigned long quad_parent_rate
;
198 unsigned long pll_hfsm
, dp_ctl
;
199 unsigned long parent_rate
;
201 parent_rate
= clk_get_rate(clk
->parent
);
203 pllbase
= _get_pll_base(clk
);
205 quad_parent_rate
= 4 * parent_rate
;
207 while (++pdf
< 16 && mfi
< 5)
208 mfi
= rate
* (pdf
+1) / quad_parent_rate
;
213 temp64
= rate
* (pdf
+1) - quad_parent_rate
* mfi
;
214 do_div(temp64
, quad_parent_rate
/1000000);
217 dp_ctl
= __raw_readl(pllbase
+ MXC_PLL_DP_CTL
);
219 __raw_writel(dp_ctl
| 0x1000L
, pllbase
+ MXC_PLL_DP_CTL
);
220 pll_hfsm
= dp_ctl
& MXC_PLL_DP_CTL_HFSM
;
222 reg
= mfi
<< 4 | pdf
;
223 __raw_writel(reg
, pllbase
+ MXC_PLL_DP_OP
);
224 __raw_writel(mfd
, pllbase
+ MXC_PLL_DP_MFD
);
225 __raw_writel(mfn
, pllbase
+ MXC_PLL_DP_MFN
);
227 reg
= mfi
<< 4 | pdf
;
228 __raw_writel(reg
, pllbase
+ MXC_PLL_DP_HFS_OP
);
229 __raw_writel(mfd
, pllbase
+ MXC_PLL_DP_HFS_MFD
);
230 __raw_writel(mfn
, pllbase
+ MXC_PLL_DP_HFS_MFN
);
236 static int _clk_pll_enable(struct clk
*clk
)
239 void __iomem
*pllbase
;
242 pllbase
= _get_pll_base(clk
);
243 reg
= __raw_readl(pllbase
+ MXC_PLL_DP_CTL
) | MXC_PLL_DP_CTL_UPEN
;
244 __raw_writel(reg
, pllbase
+ MXC_PLL_DP_CTL
);
248 reg
= __raw_readl(pllbase
+ MXC_PLL_DP_CTL
);
249 if (reg
& MXC_PLL_DP_CTL_LRF
)
253 } while (++i
< MAX_DPLL_WAIT_TRIES
);
255 if (i
== MAX_DPLL_WAIT_TRIES
) {
256 pr_err("MX5: pll locking failed\n");
263 static void _clk_pll_disable(struct clk
*clk
)
266 void __iomem
*pllbase
;
268 pllbase
= _get_pll_base(clk
);
269 reg
= __raw_readl(pllbase
+ MXC_PLL_DP_CTL
) & ~MXC_PLL_DP_CTL_UPEN
;
270 __raw_writel(reg
, pllbase
+ MXC_PLL_DP_CTL
);
273 static int _clk_pll1_sw_set_parent(struct clk
*clk
, struct clk
*parent
)
277 reg
= __raw_readl(MXC_CCM_CCSR
);
279 /* When switching from pll_main_clk to a bypass clock, first select a
280 * multiplexed clock in 'step_sel', then shift the glitchless mux
283 * When switching back, do it in reverse order
285 if (parent
== &pll1_main_clk
) {
286 /* Switch to pll1_main_clk */
287 reg
&= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL
;
288 __raw_writel(reg
, MXC_CCM_CCSR
);
289 /* step_clk mux switched to lp_apm, to save power. */
290 reg
= __raw_readl(MXC_CCM_CCSR
);
291 reg
&= ~MXC_CCM_CCSR_STEP_SEL_MASK
;
292 reg
|= (MXC_CCM_CCSR_STEP_SEL_LP_APM
<<
293 MXC_CCM_CCSR_STEP_SEL_OFFSET
);
295 if (parent
== &lp_apm_clk
) {
296 step
= MXC_CCM_CCSR_STEP_SEL_LP_APM
;
297 } else if (parent
== &pll2_sw_clk
) {
298 step
= MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED
;
299 } else if (parent
== &pll3_sw_clk
) {
300 step
= MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED
;
304 reg
&= ~MXC_CCM_CCSR_STEP_SEL_MASK
;
305 reg
|= (step
<< MXC_CCM_CCSR_STEP_SEL_OFFSET
);
307 __raw_writel(reg
, MXC_CCM_CCSR
);
308 /* Switch to step_clk */
309 reg
= __raw_readl(MXC_CCM_CCSR
);
310 reg
|= MXC_CCM_CCSR_PLL1_SW_CLK_SEL
;
312 __raw_writel(reg
, MXC_CCM_CCSR
);
316 static unsigned long clk_pll1_sw_get_rate(struct clk
*clk
)
319 unsigned long parent_rate
;
321 parent_rate
= clk_get_rate(clk
->parent
);
323 reg
= __raw_readl(MXC_CCM_CCSR
);
325 if (clk
->parent
== &pll2_sw_clk
) {
326 div
= ((reg
& MXC_CCM_CCSR_PLL2_PODF_MASK
) >>
327 MXC_CCM_CCSR_PLL2_PODF_OFFSET
) + 1;
328 } else if (clk
->parent
== &pll3_sw_clk
) {
329 div
= ((reg
& MXC_CCM_CCSR_PLL3_PODF_MASK
) >>
330 MXC_CCM_CCSR_PLL3_PODF_OFFSET
) + 1;
333 return parent_rate
/ div
;
336 static int _clk_pll2_sw_set_parent(struct clk
*clk
, struct clk
*parent
)
340 reg
= __raw_readl(MXC_CCM_CCSR
);
342 if (parent
== &pll2_sw_clk
)
343 reg
&= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL
;
345 reg
|= MXC_CCM_CCSR_PLL2_SW_CLK_SEL
;
347 __raw_writel(reg
, MXC_CCM_CCSR
);
351 static int _clk_lp_apm_set_parent(struct clk
*clk
, struct clk
*parent
)
355 if (parent
== &osc_clk
)
356 reg
= __raw_readl(MXC_CCM_CCSR
) & ~MXC_CCM_CCSR_LP_APM_SEL
;
360 __raw_writel(reg
, MXC_CCM_CCSR
);
365 static unsigned long clk_cpu_get_rate(struct clk
*clk
)
368 unsigned long parent_rate
;
370 parent_rate
= clk_get_rate(clk
->parent
);
371 cacrr
= __raw_readl(MXC_CCM_CACRR
);
372 div
= (cacrr
& MXC_CCM_CACRR_ARM_PODF_MASK
) + 1;
374 return parent_rate
/ div
;
377 static int clk_cpu_set_rate(struct clk
*clk
, unsigned long rate
)
380 unsigned long parent_rate
;
382 parent_rate
= clk_get_rate(clk
->parent
);
383 cpu_podf
= parent_rate
/ rate
- 1;
384 /* use post divider to change freq */
385 reg
= __raw_readl(MXC_CCM_CACRR
);
386 reg
&= ~MXC_CCM_CACRR_ARM_PODF_MASK
;
387 reg
|= cpu_podf
<< MXC_CCM_CACRR_ARM_PODF_OFFSET
;
388 __raw_writel(reg
, MXC_CCM_CACRR
);
393 static int _clk_periph_apm_set_parent(struct clk
*clk
, struct clk
*parent
)
398 mux
= _get_mux(parent
, &pll1_sw_clk
, &pll3_sw_clk
, &lp_apm_clk
, NULL
);
400 reg
= __raw_readl(MXC_CCM_CBCMR
) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK
;
401 reg
|= mux
<< MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET
;
402 __raw_writel(reg
, MXC_CCM_CBCMR
);
406 reg
= __raw_readl(MXC_CCM_CDHIPR
);
407 if (!(reg
& MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY
))
411 } while (++i
< MAX_DPLL_WAIT_TRIES
);
413 if (i
== MAX_DPLL_WAIT_TRIES
) {
414 pr_err("MX5: Set parent for periph_apm clock failed\n");
421 static int _clk_main_bus_set_parent(struct clk
*clk
, struct clk
*parent
)
425 reg
= __raw_readl(MXC_CCM_CBCDR
);
427 if (parent
== &pll2_sw_clk
)
428 reg
&= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL
;
429 else if (parent
== &periph_apm_clk
)
430 reg
|= MXC_CCM_CBCDR_PERIPH_CLK_SEL
;
434 __raw_writel(reg
, MXC_CCM_CBCDR
);
439 static struct clk main_bus_clk
= {
440 .parent
= &pll2_sw_clk
,
441 .set_parent
= _clk_main_bus_set_parent
,
444 static unsigned long clk_ahb_get_rate(struct clk
*clk
)
447 unsigned long parent_rate
;
449 parent_rate
= clk_get_rate(clk
->parent
);
451 reg
= __raw_readl(MXC_CCM_CBCDR
);
452 div
= ((reg
& MXC_CCM_CBCDR_AHB_PODF_MASK
) >>
453 MXC_CCM_CBCDR_AHB_PODF_OFFSET
) + 1;
454 return parent_rate
/ div
;
458 static int _clk_ahb_set_rate(struct clk
*clk
, unsigned long rate
)
461 unsigned long parent_rate
;
464 parent_rate
= clk_get_rate(clk
->parent
);
466 div
= parent_rate
/ rate
;
467 if (div
> 8 || div
< 1 || ((parent_rate
/ div
) != rate
))
470 reg
= __raw_readl(MXC_CCM_CBCDR
);
471 reg
&= ~MXC_CCM_CBCDR_AHB_PODF_MASK
;
472 reg
|= (div
- 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET
;
473 __raw_writel(reg
, MXC_CCM_CBCDR
);
477 reg
= __raw_readl(MXC_CCM_CDHIPR
);
478 if (!(reg
& MXC_CCM_CDHIPR_AHB_PODF_BUSY
))
482 } while (++i
< MAX_DPLL_WAIT_TRIES
);
484 if (i
== MAX_DPLL_WAIT_TRIES
) {
485 pr_err("MX5: clk_ahb_set_rate failed\n");
492 static unsigned long _clk_ahb_round_rate(struct clk
*clk
,
496 unsigned long parent_rate
;
498 parent_rate
= clk_get_rate(clk
->parent
);
500 div
= parent_rate
/ rate
;
505 return parent_rate
/ div
;
509 static int _clk_max_enable(struct clk
*clk
)
513 _clk_ccgr_enable(clk
);
515 /* Handshake with MAX when LPM is entered. */
516 reg
= __raw_readl(MXC_CCM_CLPCR
);
517 reg
&= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS
;
518 __raw_writel(reg
, MXC_CCM_CLPCR
);
523 static void _clk_max_disable(struct clk
*clk
)
527 _clk_ccgr_disable_inwait(clk
);
529 /* No Handshake with MAX when LPM is entered as its disabled. */
530 reg
= __raw_readl(MXC_CCM_CLPCR
);
531 reg
|= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS
;
532 __raw_writel(reg
, MXC_CCM_CLPCR
);
535 static unsigned long clk_ipg_get_rate(struct clk
*clk
)
538 unsigned long parent_rate
;
540 parent_rate
= clk_get_rate(clk
->parent
);
542 reg
= __raw_readl(MXC_CCM_CBCDR
);
543 div
= ((reg
& MXC_CCM_CBCDR_IPG_PODF_MASK
) >>
544 MXC_CCM_CBCDR_IPG_PODF_OFFSET
) + 1;
546 return parent_rate
/ div
;
549 static unsigned long clk_ipg_per_get_rate(struct clk
*clk
)
551 u32 reg
, prediv1
, prediv2
, podf
;
552 unsigned long parent_rate
;
554 parent_rate
= clk_get_rate(clk
->parent
);
556 if (clk
->parent
== &main_bus_clk
|| clk
->parent
== &lp_apm_clk
) {
557 /* the main_bus_clk is the one before the DVFS engine */
558 reg
= __raw_readl(MXC_CCM_CBCDR
);
559 prediv1
= ((reg
& MXC_CCM_CBCDR_PERCLK_PRED1_MASK
) >>
560 MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET
) + 1;
561 prediv2
= ((reg
& MXC_CCM_CBCDR_PERCLK_PRED2_MASK
) >>
562 MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET
) + 1;
563 podf
= ((reg
& MXC_CCM_CBCDR_PERCLK_PODF_MASK
) >>
564 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET
) + 1;
565 return parent_rate
/ (prediv1
* prediv2
* podf
);
566 } else if (clk
->parent
== &ipg_clk
)
572 static int _clk_ipg_per_set_parent(struct clk
*clk
, struct clk
*parent
)
576 reg
= __raw_readl(MXC_CCM_CBCMR
);
578 reg
&= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL
;
579 reg
&= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL
;
581 if (parent
== &ipg_clk
)
582 reg
|= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL
;
583 else if (parent
== &lp_apm_clk
)
584 reg
|= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL
;
585 else if (parent
!= &main_bus_clk
)
588 __raw_writel(reg
, MXC_CCM_CBCMR
);
593 #define clk_nfc_set_parent NULL
595 static unsigned long clk_nfc_get_rate(struct clk
*clk
)
600 reg
= __raw_readl(MXC_CCM_CBCDR
);
601 div
= ((reg
& MXC_CCM_CBCDR_NFC_PODF_MASK
) >>
602 MXC_CCM_CBCDR_NFC_PODF_OFFSET
) + 1;
603 rate
= clk_get_rate(clk
->parent
) / div
;
608 static unsigned long clk_nfc_round_rate(struct clk
*clk
,
612 unsigned long parent_rate
= clk_get_rate(clk
->parent
);
617 div
= parent_rate
/ rate
;
619 if (parent_rate
% rate
)
625 return parent_rate
/ div
;
629 static int clk_nfc_set_rate(struct clk
*clk
, unsigned long rate
)
633 div
= clk_get_rate(clk
->parent
) / rate
;
636 if (((clk_get_rate(clk
->parent
) / div
) != rate
) || (div
> 8))
639 reg
= __raw_readl(MXC_CCM_CBCDR
);
640 reg
&= ~MXC_CCM_CBCDR_NFC_PODF_MASK
;
641 reg
|= (div
- 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET
;
642 __raw_writel(reg
, MXC_CCM_CBCDR
);
644 while (__raw_readl(MXC_CCM_CDHIPR
) &
645 MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY
){
651 static unsigned long get_high_reference_clock_rate(struct clk
*clk
)
653 return external_high_reference
;
656 static unsigned long get_low_reference_clock_rate(struct clk
*clk
)
658 return external_low_reference
;
661 static unsigned long get_oscillator_reference_clock_rate(struct clk
*clk
)
663 return oscillator_reference
;
666 static unsigned long get_ckih2_reference_clock_rate(struct clk
*clk
)
668 return ckih2_reference
;
671 static unsigned long clk_emi_slow_get_rate(struct clk
*clk
)
675 reg
= __raw_readl(MXC_CCM_CBCDR
);
676 div
= ((reg
& MXC_CCM_CBCDR_EMI_PODF_MASK
) >>
677 MXC_CCM_CBCDR_EMI_PODF_OFFSET
) + 1;
679 return clk_get_rate(clk
->parent
) / div
;
682 /* External high frequency clock */
683 static struct clk ckih_clk
= {
684 .get_rate
= get_high_reference_clock_rate
,
687 static struct clk ckih2_clk
= {
688 .get_rate
= get_ckih2_reference_clock_rate
,
691 static struct clk osc_clk
= {
692 .get_rate
= get_oscillator_reference_clock_rate
,
695 /* External low frequency (32kHz) clock */
696 static struct clk ckil_clk
= {
697 .get_rate
= get_low_reference_clock_rate
,
700 static struct clk pll1_main_clk
= {
702 .get_rate
= clk_pll_get_rate
,
703 .enable
= _clk_pll_enable
,
704 .disable
= _clk_pll_disable
,
707 /* Clock tree block diagram (WIP):
708 * CCM: Clock Controller Module
711 * | CCM Switcher -> CCM_CLK_ROOT_GEN ->
716 /* PLL1 SW supplies to ARM core */
717 static struct clk pll1_sw_clk
= {
718 .parent
= &pll1_main_clk
,
719 .set_parent
= _clk_pll1_sw_set_parent
,
720 .get_rate
= clk_pll1_sw_get_rate
,
723 /* PLL2 SW supplies to AXI/AHB/IP buses */
724 static struct clk pll2_sw_clk
= {
726 .get_rate
= clk_pll_get_rate
,
727 .set_rate
= _clk_pll_set_rate
,
728 .set_parent
= _clk_pll2_sw_set_parent
,
729 .enable
= _clk_pll_enable
,
730 .disable
= _clk_pll_disable
,
733 /* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
734 static struct clk pll3_sw_clk
= {
736 .set_rate
= _clk_pll_set_rate
,
737 .get_rate
= clk_pll_get_rate
,
738 .enable
= _clk_pll_enable
,
739 .disable
= _clk_pll_disable
,
742 /* Low-power Audio Playback Mode clock */
743 static struct clk lp_apm_clk
= {
745 .set_parent
= _clk_lp_apm_set_parent
,
748 static struct clk periph_apm_clk
= {
749 .parent
= &pll1_sw_clk
,
750 .set_parent
= _clk_periph_apm_set_parent
,
753 static struct clk cpu_clk
= {
754 .parent
= &pll1_sw_clk
,
755 .get_rate
= clk_cpu_get_rate
,
756 .set_rate
= clk_cpu_set_rate
,
759 static struct clk ahb_clk
= {
760 .parent
= &main_bus_clk
,
761 .get_rate
= clk_ahb_get_rate
,
762 .set_rate
= _clk_ahb_set_rate
,
763 .round_rate
= _clk_ahb_round_rate
,
766 /* Main IP interface clock for access to registers */
767 static struct clk ipg_clk
= {
769 .get_rate
= clk_ipg_get_rate
,
772 static struct clk ipg_perclk
= {
773 .parent
= &lp_apm_clk
,
774 .get_rate
= clk_ipg_per_get_rate
,
775 .set_parent
= _clk_ipg_per_set_parent
,
778 static struct clk ahb_max_clk
= {
780 .enable_reg
= MXC_CCM_CCGR0
,
781 .enable_shift
= MXC_CCM_CCGRx_CG14_OFFSET
,
782 .enable
= _clk_max_enable
,
783 .disable
= _clk_max_disable
,
786 static struct clk aips_tz1_clk
= {
788 .secondary
= &ahb_max_clk
,
789 .enable_reg
= MXC_CCM_CCGR0
,
790 .enable_shift
= MXC_CCM_CCGRx_CG12_OFFSET
,
791 .enable
= _clk_ccgr_enable
,
792 .disable
= _clk_ccgr_disable_inwait
,
795 static struct clk aips_tz2_clk
= {
797 .secondary
= &ahb_max_clk
,
798 .enable_reg
= MXC_CCM_CCGR0
,
799 .enable_shift
= MXC_CCM_CCGRx_CG13_OFFSET
,
800 .enable
= _clk_ccgr_enable
,
801 .disable
= _clk_ccgr_disable_inwait
,
804 static struct clk gpt_32k_clk
= {
809 static struct clk kpp_clk
= {
813 static struct clk emi_slow_clk
= {
814 .parent
= &pll2_sw_clk
,
815 .enable_reg
= MXC_CCM_CCGR5
,
816 .enable_shift
= MXC_CCM_CCGRx_CG8_OFFSET
,
817 .enable
= _clk_ccgr_enable
,
818 .disable
= _clk_ccgr_disable_inwait
,
819 .get_rate
= clk_emi_slow_get_rate
,
822 #define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \
823 static struct clk name = { \
826 .enable_shift = es, \
827 .get_rate = pfx##_get_rate, \
828 .set_rate = pfx##_set_rate, \
829 .round_rate = pfx##_round_rate, \
830 .set_parent = pfx##_set_parent, \
831 .enable = _clk_ccgr_enable, \
832 .disable = _clk_ccgr_disable, \
837 #define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s) \
838 static struct clk name = { \
841 .enable_shift = es, \
842 .get_rate = pfx##_get_rate, \
843 .set_rate = pfx##_set_rate, \
844 .set_parent = pfx##_set_parent, \
845 .enable = _clk_max_enable, \
846 .disable = _clk_max_disable, \
851 #define CLK_GET_RATE(name, nr, bitsname) \
852 static unsigned long clk_##name##_get_rate(struct clk *clk) \
854 u32 reg, pred, podf; \
856 reg = __raw_readl(MXC_CCM_CSCDR##nr); \
857 pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK) \
858 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
859 podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK) \
860 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
862 return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), \
863 (pred + 1) * (podf + 1)); \
866 #define CLK_SET_PARENT(name, nr, bitsname) \
867 static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \
871 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, \
872 &pll3_sw_clk, &lp_apm_clk); \
873 reg = __raw_readl(MXC_CCM_CSCMR##nr) & \
874 ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK; \
875 reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET; \
876 __raw_writel(reg, MXC_CCM_CSCMR##nr); \
881 #define CLK_SET_RATE(name, nr, bitsname) \
882 static int clk_##name##_set_rate(struct clk *clk, unsigned long rate) \
884 u32 reg, div, parent_rate; \
885 u32 pre = 0, post = 0; \
887 parent_rate = clk_get_rate(clk->parent); \
888 div = parent_rate / rate; \
890 if ((parent_rate / div) != rate) \
893 __calc_pre_post_dividers(div, &pre, &post, \
894 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >> \
895 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1, \
896 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >> \
897 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
899 /* Set sdhc1 clock divider */ \
900 reg = __raw_readl(MXC_CCM_CSCDR##nr) & \
901 ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK \
902 | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK); \
903 reg |= (post - 1) << \
904 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
905 reg |= (pre - 1) << \
906 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
907 __raw_writel(reg, MXC_CCM_CSCDR##nr); \
913 CLK_GET_RATE(uart
, 1, UART
)
914 CLK_SET_PARENT(uart
, 1, UART
)
916 static struct clk uart_root_clk
= {
917 .parent
= &pll2_sw_clk
,
918 .get_rate
= clk_uart_get_rate
,
919 .set_parent
= clk_uart_set_parent
,
923 CLK_GET_RATE(usboh3
, 1, USBOH3
)
924 CLK_SET_PARENT(usboh3
, 1, USBOH3
)
926 static struct clk usboh3_clk
= {
927 .parent
= &pll2_sw_clk
,
928 .get_rate
= clk_usboh3_get_rate
,
929 .set_parent
= clk_usboh3_set_parent
,
933 CLK_GET_RATE(ecspi
, 2, CSPI
)
934 CLK_SET_PARENT(ecspi
, 1, CSPI
)
936 static struct clk ecspi_main_clk
= {
937 .parent
= &pll3_sw_clk
,
938 .get_rate
= clk_ecspi_get_rate
,
939 .set_parent
= clk_ecspi_set_parent
,
943 CLK_GET_RATE(esdhc1
, 1, ESDHC1_MSHC1
)
944 CLK_SET_PARENT(esdhc1
, 1, ESDHC1_MSHC1
)
945 CLK_SET_RATE(esdhc1
, 1, ESDHC1_MSHC1
)
947 CLK_GET_RATE(esdhc2
, 1, ESDHC2_MSHC2
)
948 CLK_SET_PARENT(esdhc2
, 1, ESDHC2_MSHC2
)
949 CLK_SET_RATE(esdhc2
, 1, ESDHC2_MSHC2
)
951 #define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \
952 static struct clk name = { \
955 .enable_shift = es, \
964 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \
965 DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
967 /* Shared peripheral bus arbiter */
968 DEFINE_CLOCK(spba_clk
, 0, MXC_CCM_CCGR5
, MXC_CCM_CCGRx_CG0_OFFSET
,
969 NULL
, NULL
, &ipg_clk
, NULL
);
972 DEFINE_CLOCK(uart1_ipg_clk
, 0, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG3_OFFSET
,
973 NULL
, NULL
, &ipg_clk
, &aips_tz1_clk
);
974 DEFINE_CLOCK(uart2_ipg_clk
, 1, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG5_OFFSET
,
975 NULL
, NULL
, &ipg_clk
, &aips_tz1_clk
);
976 DEFINE_CLOCK(uart3_ipg_clk
, 2, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG7_OFFSET
,
977 NULL
, NULL
, &ipg_clk
, &spba_clk
);
978 DEFINE_CLOCK(uart1_clk
, 0, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG4_OFFSET
,
979 NULL
, NULL
, &uart_root_clk
, &uart1_ipg_clk
);
980 DEFINE_CLOCK(uart2_clk
, 1, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG6_OFFSET
,
981 NULL
, NULL
, &uart_root_clk
, &uart2_ipg_clk
);
982 DEFINE_CLOCK(uart3_clk
, 2, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG8_OFFSET
,
983 NULL
, NULL
, &uart_root_clk
, &uart3_ipg_clk
);
986 DEFINE_CLOCK(gpt_ipg_clk
, 0, MXC_CCM_CCGR2
, MXC_CCM_CCGRx_CG10_OFFSET
,
987 NULL
, NULL
, &ipg_clk
, NULL
);
988 DEFINE_CLOCK(gpt_clk
, 0, MXC_CCM_CCGR2
, MXC_CCM_CCGRx_CG9_OFFSET
,
989 NULL
, NULL
, &ipg_clk
, &gpt_ipg_clk
);
992 DEFINE_CLOCK(i2c1_clk
, 0, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG9_OFFSET
,
993 NULL
, NULL
, &ipg_clk
, NULL
);
994 DEFINE_CLOCK(i2c2_clk
, 1, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG10_OFFSET
,
995 NULL
, NULL
, &ipg_clk
, NULL
);
996 DEFINE_CLOCK(hsi2c_clk
, 0, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG11_OFFSET
,
997 NULL
, NULL
, &ipg_clk
, NULL
);
1000 DEFINE_CLOCK(fec_clk
, 0, MXC_CCM_CCGR2
, MXC_CCM_CCGRx_CG12_OFFSET
,
1001 NULL
, NULL
, &ipg_clk
, NULL
);
1004 DEFINE_CLOCK_CCGR(nfc_clk
, 0, MXC_CCM_CCGR5
, MXC_CCM_CCGRx_CG10_OFFSET
,
1005 clk_nfc
, &emi_slow_clk
, NULL
);
1008 DEFINE_CLOCK(ssi1_ipg_clk
, 0, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG8_OFFSET
,
1009 NULL
, NULL
, &ipg_clk
, NULL
);
1010 DEFINE_CLOCK(ssi1_clk
, 0, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG9_OFFSET
,
1011 NULL
, NULL
, &pll3_sw_clk
, &ssi1_ipg_clk
);
1012 DEFINE_CLOCK(ssi2_ipg_clk
, 1, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG10_OFFSET
,
1013 NULL
, NULL
, &ipg_clk
, NULL
);
1014 DEFINE_CLOCK(ssi2_clk
, 1, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG11_OFFSET
,
1015 NULL
, NULL
, &pll3_sw_clk
, &ssi2_ipg_clk
);
1018 DEFINE_CLOCK_FULL(ecspi1_ipg_clk
, 0, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG9_OFFSET
,
1019 NULL
, NULL
, _clk_ccgr_enable_inrun
, _clk_ccgr_disable
,
1020 &ipg_clk
, &spba_clk
);
1021 DEFINE_CLOCK(ecspi1_clk
, 0, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG10_OFFSET
,
1022 NULL
, NULL
, &ecspi_main_clk
, &ecspi1_ipg_clk
);
1023 DEFINE_CLOCK_FULL(ecspi2_ipg_clk
, 0, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG11_OFFSET
,
1024 NULL
, NULL
, _clk_ccgr_enable_inrun
, _clk_ccgr_disable
,
1025 &ipg_clk
, &aips_tz2_clk
);
1026 DEFINE_CLOCK(ecspi2_clk
, 0, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG12_OFFSET
,
1027 NULL
, NULL
, &ecspi_main_clk
, &ecspi2_ipg_clk
);
1030 DEFINE_CLOCK(cspi_ipg_clk
, 0, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG9_OFFSET
,
1031 NULL
, NULL
, &ipg_clk
, &aips_tz2_clk
);
1032 DEFINE_CLOCK(cspi_clk
, 0, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG13_OFFSET
,
1033 NULL
, NULL
, &ipg_clk
, &cspi_ipg_clk
);
1036 DEFINE_CLOCK(sdma_clk
, 1, MXC_CCM_CCGR4
, MXC_CCM_CCGRx_CG15_OFFSET
,
1037 NULL
, NULL
, &ahb_clk
, NULL
);
1040 DEFINE_CLOCK_FULL(esdhc1_ipg_clk
, 0, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG0_OFFSET
,
1041 NULL
, NULL
, _clk_max_enable
, _clk_max_disable
, &ipg_clk
, NULL
);
1042 DEFINE_CLOCK_MAX(esdhc1_clk
, 0, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG1_OFFSET
,
1043 clk_esdhc1
, &pll2_sw_clk
, &esdhc1_ipg_clk
);
1044 DEFINE_CLOCK_FULL(esdhc2_ipg_clk
, 1, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG2_OFFSET
,
1045 NULL
, NULL
, _clk_max_enable
, _clk_max_disable
, &ipg_clk
, NULL
);
1046 DEFINE_CLOCK_MAX(esdhc2_clk
, 1, MXC_CCM_CCGR3
, MXC_CCM_CCGRx_CG3_OFFSET
,
1047 clk_esdhc2
, &pll2_sw_clk
, &esdhc2_ipg_clk
);
1049 #define _REGISTER_CLOCK(d, n, c) \
1056 static struct clk_lookup lookups
[] = {
1057 _REGISTER_CLOCK("imx-uart.0", NULL
, uart1_clk
)
1058 _REGISTER_CLOCK("imx-uart.1", NULL
, uart2_clk
)
1059 _REGISTER_CLOCK("imx-uart.2", NULL
, uart3_clk
)
1060 _REGISTER_CLOCK(NULL
, "gpt", gpt_clk
)
1061 _REGISTER_CLOCK("fec.0", NULL
, fec_clk
)
1062 _REGISTER_CLOCK("imx-i2c.0", NULL
, i2c1_clk
)
1063 _REGISTER_CLOCK("imx-i2c.1", NULL
, i2c2_clk
)
1064 _REGISTER_CLOCK("imx-i2c.2", NULL
, hsi2c_clk
)
1065 _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk
)
1066 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk
)
1067 _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk
)
1068 _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk
)
1069 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk
)
1070 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk
)
1071 _REGISTER_CLOCK("imx-keypad.0", NULL
, kpp_clk
)
1072 _REGISTER_CLOCK("mxc_nand", NULL
, nfc_clk
)
1073 _REGISTER_CLOCK("imx-ssi.0", NULL
, ssi1_clk
)
1074 _REGISTER_CLOCK("imx-ssi.1", NULL
, ssi2_clk
)
1075 _REGISTER_CLOCK("imx-sdma", NULL
, sdma_clk
)
1076 _REGISTER_CLOCK(NULL
, "ckih", ckih_clk
)
1077 _REGISTER_CLOCK(NULL
, "ckih2", ckih2_clk
)
1078 _REGISTER_CLOCK(NULL
, "gpt_32k", gpt_32k_clk
)
1079 _REGISTER_CLOCK("imx51-ecspi.0", NULL
, ecspi1_clk
)
1080 _REGISTER_CLOCK("imx51-ecspi.1", NULL
, ecspi2_clk
)
1081 _REGISTER_CLOCK("imx51-cspi.0", NULL
, cspi_clk
)
1082 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL
, esdhc1_clk
)
1083 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL
, esdhc2_clk
)
1084 _REGISTER_CLOCK(NULL
, "cpu_clk", cpu_clk
)
1087 static void clk_tree_init(void)
1091 ipg_perclk
.set_parent(&ipg_perclk
, &lp_apm_clk
);
1094 * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
1095 * 8MHz, its derived from lp_apm.
1097 * FIXME: Verify if true for all boards
1099 reg
= __raw_readl(MXC_CCM_CBCDR
);
1100 reg
&= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK
;
1101 reg
&= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK
;
1102 reg
&= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK
;
1103 reg
|= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET
);
1104 __raw_writel(reg
, MXC_CCM_CBCDR
);
1107 int __init
mx51_clocks_init(unsigned long ckil
, unsigned long osc
,
1108 unsigned long ckih1
, unsigned long ckih2
)
1112 external_low_reference
= ckil
;
1113 external_high_reference
= ckih1
;
1114 ckih2_reference
= ckih2
;
1115 oscillator_reference
= osc
;
1117 for (i
= 0; i
< ARRAY_SIZE(lookups
); i
++)
1118 clkdev_add(&lookups
[i
]);
1122 clk_enable(&cpu_clk
);
1123 clk_enable(&main_bus_clk
);
1125 /* set the usboh3_clk parent to pll2_sw_clk */
1126 clk_set_parent(&usboh3_clk
, &pll2_sw_clk
);
1128 /* Set SDHC parents to be PLL2 */
1129 clk_set_parent(&esdhc1_clk
, &pll2_sw_clk
);
1130 clk_set_parent(&esdhc2_clk
, &pll2_sw_clk
);
1132 /* set SDHC root clock as 166.25MHZ*/
1133 clk_set_rate(&esdhc1_clk
, 166250000);
1134 clk_set_rate(&esdhc2_clk
, 166250000);
1137 mxc_timer_init(&gpt_clk
, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR
),