arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h

   1 /*
   2  * arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h
   3  *
   4  * Copyright (C) 2006,2007 by Digi International Inc.
   5  * All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  */
  11 #ifndef __ASM_ARCH_REGSSYSNS9360_H
  12 #define __ASM_ARCH_REGSSYSNS9360_H
  13
  14 #include <mach/hardware.h>
  15
  16 /* System Control Module */
  17
  18 /* AHB Arbiter Gen Configuration */
  19 #define SYS_AHBAGENCONF __REG(0xa0900000)
  20
  21 /* BRC */
  22 #define SYS_BRC(x)      __REG2(0xa0900004, (x))
  23
  24 /* Timer x Reload Count register */
  25 #define SYS_TRC(x)      __REG2(0xa0900044, (x))
  26
  27 /* Timer x Read register */
  28 #define SYS_TR(x)       __REG2(0xa0900084, (x))
  29
  30 /* Timer Interrupt Status register */
  31 #define SYS_TIS         __REG(0xa0900170)
  32
  33 /* PLL Configuration register */
  34 #define SYS_PLL         __REG(0xa0900188)
  35
  36 /* PLL FS status */
  37 #define SYS_PLL_FS              __REGBITS(24, 23)
  38
  39 /* PLL ND status */
  40 #define SYS_PLL_ND              __REGBITS(20, 16)
  41
  42 /* PLL Configuration register: PLL SW change */
  43 #define SYS_PLL_SWC             __REGBIT(15)
  44 #define SYS_PLL_SWC_NO                  __REGVAL(SYS_PLL_SWC, 0)
  45 #define SYS_PLL_SWC_YES                 __REGVAL(SYS_PLL_SWC, 1)
  46
  47 /* Timer x Control register */
  48 #define SYS_TC(x)       __REG2(0xa0900190, (x))
  49
  50 /* Timer x Control register: Timer enable */
  51 #define SYS_TCx_TEN             __REGBIT(15)
  52 #define SYS_TCx_TEN_DIS                 __REGVAL(SYS_TCx_TEN, 0)
  53 #define SYS_TCx_TEN_EN                  __REGVAL(SYS_TCx_TEN, 1)
  54
  55 /* Timer x Control register: CPU debug mode */
  56 #define SYS_TCx_TDBG            __REGBIT(10)
  57 #define SYS_TCx_TDBG_CONT               __REGVAL(SYS_TCx_TDBG, 0)
  58 #define SYS_TCx_TDBG_STOP               __REGVAL(SYS_TCx_TDBG, 1)
  59
  60 /* Timer x Control register: Interrupt clear */
  61 #define SYS_TCx_INTC            __REGBIT(9)
  62 #define SYS_TCx_INTC_UNSET              __REGVAL(SYS_TCx_INTC, 0)
  63 #define SYS_TCx_INTC_SET                __REGVAL(SYS_TCx_INTC, 1)
  64
  65 /* Timer x Control register: Timer clock select */
  66 #define SYS_TCx_TLCS            __REGBITS(8, 6)
  67 #define SYS_TCx_TLCS_CPU                __REGVAL(SYS_TCx_TLCS, 0)       /* CPU clock */
  68 #define SYS_TCx_TLCS_DIV2               __REGVAL(SYS_TCx_TLCS, 1)       /* CPU clock / 2 */
  69 #define SYS_TCx_TLCS_DIV4               __REGVAL(SYS_TCx_TLCS, 2)       /* CPU clock / 4 */
  70 #define SYS_TCx_TLCS_DIV8               __REGVAL(SYS_TCx_TLCS, 3)       /* CPU clock / 8 */
  71 #define SYS_TCx_TLCS_DIV16              __REGVAL(SYS_TCx_TLCS, 4)       /* CPU clock / 16 */
  72 #define SYS_TCx_TLCS_DIV32              __REGVAL(SYS_TCx_TLCS, 5)       /* CPU clock / 32 */
  73 #define SYS_TCx_TLCS_DIV64              __REGVAL(SYS_TCx_TLCS, 6)       /* CPU clock / 64 */
  74 #define SYS_TCx_TLCS_EXT                __REGVAL(SYS_TCx_TLCS, 7)
  75
  76 /* Timer x Control register: Timer mode */
  77 #define SYS_TCx_TM              __REGBITS(5, 4)
  78 #define SYS_TCx_TM_IEE                  __REGVAL(SYS_TCx_TM, 0)         /* Internal timer or external event */
  79 #define SYS_TCx_TM_ELL                  __REGVAL(SYS_TCx_TM, 1)         /* External low-level, gated timer */
  80 #define SYS_TCx_TM_EHL                  __REGVAL(SYS_TCx_TM, 2)         /* External high-level, gated timer */
  81 #define SYS_TCx_TM_CONCAT               __REGVAL(SYS_TCx_TM, 3)         /* Concatenate the lower timer. */
  82
  83 /* Timer x Control register: Interrupt select */
  84 #define SYS_TCx_INTS            __REGBIT(3)
  85 #define SYS_TCx_INTS_DIS                __REGVAL(SYS_TCx_INTS, 0)
  86 #define SYS_TCx_INTS_EN                 __REGVAL(SYS_TCx_INTS, 1)
  87
  88 /* Timer x Control register: Up/down select */
  89 #define SYS_TCx_UDS             __REGBIT(2)
  90 #define SYS_TCx_UDS_UP                  __REGVAL(SYS_TCx_UDS, 0)
  91 #define SYS_TCx_UDS_DOWN                __REGVAL(SYS_TCx_UDS, 1)
  92
  93 /* Timer x Control register: 32- or 16-bit timer */
  94 #define SYS_TCx_TSZ             __REGBIT(1)
  95 #define SYS_TCx_TSZ_16                  __REGVAL(SYS_TCx_TSZ, 0)
  96 #define SYS_TCx_TSZ_32                  __REGVAL(SYS_TCx_TSZ, 1)
  97
  98 /* Timer x Control register: Reload enable */
  99 #define SYS_TCx_REN             __REGBIT(0)
 100 #define SYS_TCx_REN_DIS                 __REGVAL(SYS_TCx_REN, 0)
 101 #define SYS_TCx_REN_EN                  __REGVAL(SYS_TCx_REN, 1)
 102
 103 /* System Memory Chip Select x Dynamic Memory Base */
 104 #define SYS_SMCSDMB(x)  __REG2(0xa09001d0, (x) << 1)
 105
 106 /* System Memory Chip Select x Dynamic Memory Mask */
 107 #define SYS_SMCSDMM(x)  __REG2(0xa09001d4, (x) << 1)
 108
 109 /* System Memory Chip Select x Static Memory Base */
 110 #define SYS_SMCSSMB(x)  __REG2(0xa09001f0, (x) << 1)
 111
 112 /* System Memory Chip Select x Static Memory Base: Chip select x base */
 113 #define SYS_SMCSSMB_CSxB        __REGBITS(31, 12)
 114
 115 /* System Memory Chip Select x Static Memory Mask */
 116 #define SYS_SMCSSMM(x)  __REG2(0xa09001f4, (x) << 1)
 117
 118 /* System Memory Chip Select x Static Memory Mask: Chip select x mask */
 119 #define SYS_SMCSSMM_CSxM        __REGBITS(31, 12)
 120
 121 /* System Memory Chip Select x Static Memory Mask: Chip select x enable */
 122 #define SYS_SMCSSMM_CSEx        __REGBIT(0)
 123 #define SYS_SMCSSMM_CSEx_DIS            __REGVAL(SYS_SMCSSMM_CSEx, 0)
 124 #define SYS_SMCSSMM_CSEx_EN             __REGVAL(SYS_SMCSSMM_CSEx, 1)
 125
 126 /* General purpose, user-defined ID register */
 127 #define SYS_GENID       __REG(0xa0900210)
 128
 129 /* External Interrupt x Control register */
 130 #define SYS_EIC(x)      __REG2(0xa0900214, (x))
 131
 132 /* External Interrupt x Control register: Status */
 133 #define SYS_EIC_STS             __REGBIT(3)
 134
 135 /* External Interrupt x Control register: Clear */
 136 #define SYS_EIC_CLR             __REGBIT(2)
 137
 138 /* External Interrupt x Control register: Polarity */
 139 #define SYS_EIC_PLTY            __REGBIT(1)
 140 #define SYS_EIC_PLTY_AH                 __REGVAL(SYS_EIC_PLTY, 0)
 141 #define SYS_EIC_PLTY_AL                 __REGVAL(SYS_EIC_PLTY, 1)
 142
 143 /* External Interrupt x Control register: Level edge */
 144 #define SYS_EIC_LVEDG           __REGBIT(0)
 145 #define SYS_EIC_LVEDG_LEVEL             __REGVAL(SYS_EIC_LVEDG, 0)
 146 #define SYS_EIC_LVEDG_EDGE              __REGVAL(SYS_EIC_LVEDG, 1)
 147
 148 #endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */