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[ARM] omap: add support for bypassing DPLLs
[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / clock34xx.c
1 /*
2 * OMAP3-specific clock framework functions
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
9 *
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17 #undef DEBUG
18
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h>
22 #include <linux/list.h>
23 #include <linux/errno.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
26 #include <linux/io.h>
27 #include <linux/limits.h>
28 #include <linux/bitops.h>
29
30 #include <mach/clock.h>
31 #include <mach/sram.h>
32 #include <asm/div64.h>
33 #include <asm/clkdev.h>
34
35 #include <mach/sdrc.h>
36 #include "clock.h"
37 #include "prm.h"
38 #include "prm-regbits-34xx.h"
39 #include "cm.h"
40 #include "cm-regbits-34xx.h"
41
42 static const struct clkops clkops_noncore_dpll_ops;
43
44 #include "clock34xx.h"
45
46 struct omap_clk {
47 u32 cpu;
48 struct clk_lookup lk;
49 };
50
51 #define CLK(dev, con, ck, cp) \
52 { \
53 .cpu = cp, \
54 .lk = { \
55 .dev_id = dev, \
56 .con_id = con, \
57 .clk = ck, \
58 }, \
59 }
60
61 #define CK_343X (1 << 0)
62 #define CK_3430ES1 (1 << 1)
63 #define CK_3430ES2 (1 << 2)
64
65 static struct omap_clk omap34xx_clks[] = {
66 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
67 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
68 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
69 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
70 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
71 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
72 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
73 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
74 CLK(NULL, "sys_ck", &sys_ck, CK_343X),
75 CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
76 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
77 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
78 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
79 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
80 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
81 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
82 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
83 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
84 CLK(NULL, "core_ck", &core_ck, CK_343X),
85 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
86 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
87 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
88 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
89 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
90 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
91 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
92 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
93 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
94 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
95 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
96 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
97 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
98 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
99 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
100 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
101 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
102 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
103 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
104 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
105 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
106 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
107 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
108 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
109 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
110 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
111 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
112 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
113 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
114 CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
115 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
116 CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
117 CLK(NULL, "arm_fck", &arm_fck, CK_343X),
118 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
119 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
120 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
121 CLK(NULL, "l3_ick", &l3_ick, CK_343X),
122 CLK(NULL, "l4_ick", &l4_ick, CK_343X),
123 CLK(NULL, "rm_ick", &rm_ick, CK_343X),
124 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
125 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
126 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
127 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
128 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
129 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
130 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
131 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
132 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
133 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
134 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
135 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
136 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
137 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
138 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2),
139 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X),
140 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
141 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X),
142 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X),
143 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X),
144 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X),
145 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X),
146 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X),
147 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
148 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X),
149 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X),
150 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X),
151 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X),
152 CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
153 CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
154 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
155 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
156 CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
157 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
158 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
159 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
160 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X),
161 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
162 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
163 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
164 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
165 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
166 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
167 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2),
168 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
169 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
170 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
171 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
172 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X),
173 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X),
174 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
175 CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X),
176 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X),
177 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X),
178 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X),
179 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X),
180 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X),
181 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X),
182 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X),
183 CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
184 CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
185 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
186 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
187 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X),
188 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X),
189 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
190 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
191 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
192 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
193 CLK(NULL, "ssi_ick", &ssi_ick, CK_343X),
194 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
195 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
196 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
197 CLK("omap_rng", "ick", &rng_ick, CK_343X),
198 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
199 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
200 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X),
201 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X),
202 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X),
203 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X),
204 CLK(NULL, "dss_ick", &dss_ick, CK_343X),
205 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
206 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
207 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
208 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
209 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
210 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
211 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
212 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
213 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
214 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
215 CLK("omap_wdt", "fck", &wdt2_fck, CK_343X),
216 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
217 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
218 CLK("omap_wdt", "ick", &wdt2_ick, CK_343X),
219 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
220 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
221 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
222 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
223 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
224 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
225 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
226 CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
227 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
228 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
229 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
230 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
231 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
232 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
233 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
234 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
235 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
236 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
237 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
238 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
239 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
240 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
241 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
242 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
243 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
244 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
245 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
246 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
247 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
248 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
249 CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
250 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
251 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
252 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
253 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
254 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
255 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
256 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
257 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
258 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X),
259 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X),
260 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X),
261 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X),
262 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X),
263 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X),
264 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X),
265 CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
266 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
267 CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
268 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
269 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
270 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
271 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
272 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
273 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
274 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
275 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
276 };
277
278 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
279 #define DPLL_AUTOIDLE_DISABLE 0x0
280 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
281
282 #define MAX_DPLL_WAIT_TRIES 1000000
283
284 /**
285 * omap3_dpll_recalc - recalculate DPLL rate
286 * @clk: DPLL struct clk
287 *
288 * Recalculate and propagate the DPLL rate.
289 */
290 static unsigned long omap3_dpll_recalc(struct clk *clk)
291 {
292 return omap2_get_dpll_rate(clk);
293 }
294
295 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
296 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
297 {
298 const struct dpll_data *dd;
299 u32 v;
300
301 dd = clk->dpll_data;
302
303 v = __raw_readl(dd->control_reg);
304 v &= ~dd->enable_mask;
305 v |= clken_bits << __ffs(dd->enable_mask);
306 __raw_writel(v, dd->control_reg);
307 }
308
309 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
310 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
311 {
312 const struct dpll_data *dd;
313 int i = 0;
314 int ret = -EINVAL;
315
316 dd = clk->dpll_data;
317
318 state <<= __ffs(dd->idlest_mask);
319
320 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
321 i < MAX_DPLL_WAIT_TRIES) {
322 i++;
323 udelay(1);
324 }
325
326 if (i == MAX_DPLL_WAIT_TRIES) {
327 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
328 clk->name, (state) ? "locked" : "bypassed");
329 } else {
330 pr_debug("clock: %s transition to '%s' in %d loops\n",
331 clk->name, (state) ? "locked" : "bypassed", i);
332
333 ret = 0;
334 }
335
336 return ret;
337 }
338
339 /* From 3430 TRM ES2 4.7.6.2 */
340 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
341 {
342 unsigned long fint;
343 u16 f = 0;
344
345 fint = clk->dpll_data->clk_ref->rate / (n + 1);
346
347 pr_debug("clock: fint is %lu\n", fint);
348
349 if (fint >= 750000 && fint <= 1000000)
350 f = 0x3;
351 else if (fint > 1000000 && fint <= 1250000)
352 f = 0x4;
353 else if (fint > 1250000 && fint <= 1500000)
354 f = 0x5;
355 else if (fint > 1500000 && fint <= 1750000)
356 f = 0x6;
357 else if (fint > 1750000 && fint <= 2100000)
358 f = 0x7;
359 else if (fint > 7500000 && fint <= 10000000)
360 f = 0xB;
361 else if (fint > 10000000 && fint <= 12500000)
362 f = 0xC;
363 else if (fint > 12500000 && fint <= 15000000)
364 f = 0xD;
365 else if (fint > 15000000 && fint <= 17500000)
366 f = 0xE;
367 else if (fint > 17500000 && fint <= 21000000)
368 f = 0xF;
369 else
370 pr_debug("clock: unknown freqsel setting for %d\n", n);
371
372 return f;
373 }
374
375 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
376
377 /*
378 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
379 * @clk: pointer to a DPLL struct clk
380 *
381 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
382 * readiness before returning. Will save and restore the DPLL's
383 * autoidle state across the enable, per the CDP code. If the DPLL
384 * locked successfully, return 0; if the DPLL did not lock in the time
385 * allotted, or DPLL3 was passed in, return -EINVAL.
386 */
387 static int _omap3_noncore_dpll_lock(struct clk *clk)
388 {
389 u8 ai;
390 int r;
391
392 if (clk == &dpll3_ck)
393 return -EINVAL;
394
395 pr_debug("clock: locking DPLL %s\n", clk->name);
396
397 ai = omap3_dpll_autoidle_read(clk);
398
399 omap3_dpll_deny_idle(clk);
400
401 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
402
403 r = _omap3_wait_dpll_status(clk, 1);
404
405 if (ai)
406 omap3_dpll_allow_idle(clk);
407
408 return r;
409 }
410
411 /*
412 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
413 * @clk: pointer to a DPLL struct clk
414 *
415 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
416 * bypass mode, the DPLL's rate is set equal to its parent clock's
417 * rate. Waits for the DPLL to report readiness before returning.
418 * Will save and restore the DPLL's autoidle state across the enable,
419 * per the CDP code. If the DPLL entered bypass mode successfully,
420 * return 0; if the DPLL did not enter bypass in the time allotted, or
421 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
422 * return -EINVAL.
423 */
424 static int _omap3_noncore_dpll_bypass(struct clk *clk)
425 {
426 int r;
427 u8 ai;
428
429 if (clk == &dpll3_ck)
430 return -EINVAL;
431
432 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
433 return -EINVAL;
434
435 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
436 clk->name);
437
438 ai = omap3_dpll_autoidle_read(clk);
439
440 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
441
442 r = _omap3_wait_dpll_status(clk, 0);
443
444 if (ai)
445 omap3_dpll_allow_idle(clk);
446 else
447 omap3_dpll_deny_idle(clk);
448
449 return r;
450 }
451
452 /*
453 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
454 * @clk: pointer to a DPLL struct clk
455 *
456 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
457 * restore the DPLL's autoidle state across the stop, per the CDP
458 * code. If DPLL3 was passed in, or the DPLL does not support
459 * low-power stop, return -EINVAL; otherwise, return 0.
460 */
461 static int _omap3_noncore_dpll_stop(struct clk *clk)
462 {
463 u8 ai;
464
465 if (clk == &dpll3_ck)
466 return -EINVAL;
467
468 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
469 return -EINVAL;
470
471 pr_debug("clock: stopping DPLL %s\n", clk->name);
472
473 ai = omap3_dpll_autoidle_read(clk);
474
475 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
476
477 if (ai)
478 omap3_dpll_allow_idle(clk);
479 else
480 omap3_dpll_deny_idle(clk);
481
482 return 0;
483 }
484
485 /**
486 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
487 * @clk: pointer to a DPLL struct clk
488 *
489 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
490 * The choice of modes depends on the DPLL's programmed rate: if it is
491 * the same as the DPLL's parent clock, it will enter bypass;
492 * otherwise, it will enter lock. This code will wait for the DPLL to
493 * indicate readiness before returning, unless the DPLL takes too long
494 * to enter the target state. Intended to be used as the struct clk's
495 * enable function. If DPLL3 was passed in, or the DPLL does not
496 * support low-power stop, or if the DPLL took too long to enter
497 * bypass or lock, return -EINVAL; otherwise, return 0.
498 */
499 static int omap3_noncore_dpll_enable(struct clk *clk)
500 {
501 int r;
502 struct dpll_data *dd;
503
504 if (clk == &dpll3_ck)
505 return -EINVAL;
506
507 dd = clk->dpll_data;
508 if (!dd)
509 return -EINVAL;
510
511 if (clk->rate == dd->clk_bypass->rate) {
512 WARN_ON(clk->parent != dd->clk_bypass);
513 r = _omap3_noncore_dpll_bypass(clk);
514 } else {
515 WARN_ON(clk->parent != dd->clk_ref);
516 r = _omap3_noncore_dpll_lock(clk);
517 }
518 /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */
519 if (!r)
520 clk->rate = omap2_get_dpll_rate(clk);
521
522 return r;
523 }
524
525 /**
526 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
527 * @clk: pointer to a DPLL struct clk
528 *
529 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
530 * The choice of modes depends on the DPLL's programmed rate: if it is
531 * the same as the DPLL's parent clock, it will enter bypass;
532 * otherwise, it will enter lock. This code will wait for the DPLL to
533 * indicate readiness before returning, unless the DPLL takes too long
534 * to enter the target state. Intended to be used as the struct clk's
535 * enable function. If DPLL3 was passed in, or the DPLL does not
536 * support low-power stop, or if the DPLL took too long to enter
537 * bypass or lock, return -EINVAL; otherwise, return 0.
538 */
539 static void omap3_noncore_dpll_disable(struct clk *clk)
540 {
541 if (clk == &dpll3_ck)
542 return;
543
544 _omap3_noncore_dpll_stop(clk);
545 }
546
547
548 /* Non-CORE DPLL rate set code */
549
550 /*
551 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
552 * @clk: struct clk * of DPLL to set
553 * @m: DPLL multiplier to set
554 * @n: DPLL divider to set
555 * @freqsel: FREQSEL value to set
556 *
557 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
558 * lock.. Returns -EINVAL upon error, or 0 upon success.
559 */
560 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
561 {
562 struct dpll_data *dd = clk->dpll_data;
563 u32 v;
564
565 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
566 _omap3_noncore_dpll_bypass(clk);
567
568 /* Set jitter correction */
569 v = __raw_readl(dd->control_reg);
570 v &= ~dd->freqsel_mask;
571 v |= freqsel << __ffs(dd->freqsel_mask);
572 __raw_writel(v, dd->control_reg);
573
574 /* Set DPLL multiplier, divider */
575 v = __raw_readl(dd->mult_div1_reg);
576 v &= ~(dd->mult_mask | dd->div1_mask);
577 v |= m << __ffs(dd->mult_mask);
578 v |= (n - 1) << __ffs(dd->div1_mask);
579 __raw_writel(v, dd->mult_div1_reg);
580
581 /* We let the clock framework set the other output dividers later */
582
583 /* REVISIT: Set ramp-up delay? */
584
585 _omap3_noncore_dpll_lock(clk);
586
587 return 0;
588 }
589
590 /**
591 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
592 * @clk: struct clk * of DPLL to set
593 * @rate: rounded target rate
594 *
595 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
596 * low-power bypass, and the target rate is the bypass source clock
597 * rate, then configure the DPLL for bypass. Otherwise, round the
598 * target rate if it hasn't been done already, then program and lock
599 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
600 */
601 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
602 {
603 struct clk *new_parent = NULL;
604 u16 freqsel;
605 struct dpll_data *dd;
606 int ret;
607
608 if (!clk || !rate)
609 return -EINVAL;
610
611 dd = clk->dpll_data;
612 if (!dd)
613 return -EINVAL;
614
615 if (rate == omap2_get_dpll_rate(clk))
616 return 0;
617
618 /*
619 * Ensure both the bypass and ref clocks are enabled prior to
620 * doing anything; we need the bypass clock running to reprogram
621 * the DPLL.
622 */
623 omap2_clk_enable(dd->clk_bypass);
624 omap2_clk_enable(dd->clk_ref);
625
626 if (dd->clk_bypass->rate == rate &&
627 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
628 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
629
630 ret = _omap3_noncore_dpll_bypass(clk);
631 if (!ret)
632 new_parent = dd->clk_bypass;
633 } else {
634 if (dd->last_rounded_rate != rate)
635 omap2_dpll_round_rate(clk, rate);
636
637 if (dd->last_rounded_rate == 0)
638 return -EINVAL;
639
640 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
641 if (!freqsel)
642 WARN_ON(1);
643
644 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
645 clk->name, rate);
646
647 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
648 dd->last_rounded_n, freqsel);
649 if (!ret)
650 new_parent = dd->clk_ref;
651 }
652 if (!ret) {
653 /*
654 * Switch the parent clock in the heirarchy, and make sure
655 * that the new parent's usecount is correct. Note: we
656 * enable the new parent before disabling the old to avoid
657 * any unnecessary hardware disable->enable transitions.
658 */
659 if (clk->usecount) {
660 omap2_clk_enable(new_parent);
661 omap2_clk_disable(clk->parent);
662 }
663 clk_reparent(clk, new_parent);
664 clk->rate = rate;
665 }
666 omap2_clk_disable(dd->clk_ref);
667 omap2_clk_disable(dd->clk_bypass);
668
669 return 0;
670 }
671
672 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
673 {
674 /*
675 * According to the 12-5 CDP code from TI, "Limitation 2.5"
676 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
677 * on DPLL4.
678 */
679 if (omap_rev() == OMAP3430_REV_ES1_0) {
680 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
681 "silicon 'Limitation 2.5' on 3430ES1.\n");
682 return -EINVAL;
683 }
684 return omap3_noncore_dpll_set_rate(clk, rate);
685 }
686
687
688 /*
689 * CORE DPLL (DPLL3) rate programming functions
690 *
691 * These call into SRAM code to do the actual CM writes, since the SDRAM
692 * is clocked from DPLL3.
693 */
694
695 /**
696 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
697 * @clk: struct clk * of DPLL to set
698 * @rate: rounded target rate
699 *
700 * Program the DPLL M2 divider with the rounded target rate. Returns
701 * -EINVAL upon error, or 0 upon success.
702 */
703 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
704 {
705 u32 new_div = 0;
706 unsigned long validrate, sdrcrate;
707 struct omap_sdrc_params *sp;
708
709 if (!clk || !rate)
710 return -EINVAL;
711
712 if (clk != &dpll3_m2_ck)
713 return -EINVAL;
714
715 if (rate == clk->rate)
716 return 0;
717
718 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
719 if (validrate != rate)
720 return -EINVAL;
721
722 sdrcrate = sdrc_ick.rate;
723 if (rate > clk->rate)
724 sdrcrate <<= ((rate / clk->rate) - 1);
725 else
726 sdrcrate >>= ((clk->rate / rate) - 1);
727
728 sp = omap2_sdrc_get_params(sdrcrate);
729 if (!sp)
730 return -EINVAL;
731
732 pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
733 validrate);
734 pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
735 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
736
737 /* REVISIT: SRAM code doesn't support other M2 divisors yet */
738 WARN_ON(new_div != 1 && new_div != 2);
739
740 /* REVISIT: Add SDRC_MR changing to this code also */
741 omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
742 sp->actim_ctrlb, new_div);
743
744 return 0;
745 }
746
747
748 static const struct clkops clkops_noncore_dpll_ops = {
749 .enable = &omap3_noncore_dpll_enable,
750 .disable = &omap3_noncore_dpll_disable,
751 };
752
753 /* DPLL autoidle read/set code */
754
755
756 /**
757 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
758 * @clk: struct clk * of the DPLL to read
759 *
760 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
761 * -EINVAL if passed a null pointer or if the struct clk does not
762 * appear to refer to a DPLL.
763 */
764 static u32 omap3_dpll_autoidle_read(struct clk *clk)
765 {
766 const struct dpll_data *dd;
767 u32 v;
768
769 if (!clk || !clk->dpll_data)
770 return -EINVAL;
771
772 dd = clk->dpll_data;
773
774 v = __raw_readl(dd->autoidle_reg);
775 v &= dd->autoidle_mask;
776 v >>= __ffs(dd->autoidle_mask);
777
778 return v;
779 }
780
781 /**
782 * omap3_dpll_allow_idle - enable DPLL autoidle bits
783 * @clk: struct clk * of the DPLL to operate on
784 *
785 * Enable DPLL automatic idle control. This automatic idle mode
786 * switching takes effect only when the DPLL is locked, at least on
787 * OMAP3430. The DPLL will enter low-power stop when its downstream
788 * clocks are gated. No return value.
789 */
790 static void omap3_dpll_allow_idle(struct clk *clk)
791 {
792 const struct dpll_data *dd;
793 u32 v;
794
795 if (!clk || !clk->dpll_data)
796 return;
797
798 dd = clk->dpll_data;
799
800 /*
801 * REVISIT: CORE DPLL can optionally enter low-power bypass
802 * by writing 0x5 instead of 0x1. Add some mechanism to
803 * optionally enter this mode.
804 */
805 v = __raw_readl(dd->autoidle_reg);
806 v &= ~dd->autoidle_mask;
807 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
808 __raw_writel(v, dd->autoidle_reg);
809 }
810
811 /**
812 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
813 * @clk: struct clk * of the DPLL to operate on
814 *
815 * Disable DPLL automatic idle control. No return value.
816 */
817 static void omap3_dpll_deny_idle(struct clk *clk)
818 {
819 const struct dpll_data *dd;
820 u32 v;
821
822 if (!clk || !clk->dpll_data)
823 return;
824
825 dd = clk->dpll_data;
826
827 v = __raw_readl(dd->autoidle_reg);
828 v &= ~dd->autoidle_mask;
829 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
830 __raw_writel(v, dd->autoidle_reg);
831 }
832
833 /* Clock control for DPLL outputs */
834
835 /**
836 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
837 * @clk: DPLL output struct clk
838 *
839 * Using parent clock DPLL data, look up DPLL state. If locked, set our
840 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
841 */
842 static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
843 {
844 const struct dpll_data *dd;
845 unsigned long rate;
846 u32 v;
847 struct clk *pclk;
848
849 /* Walk up the parents of clk, looking for a DPLL */
850 pclk = clk->parent;
851 while (pclk && !pclk->dpll_data)
852 pclk = pclk->parent;
853
854 /* clk does not have a DPLL as a parent? */
855 WARN_ON(!pclk);
856
857 dd = pclk->dpll_data;
858
859 WARN_ON(!dd->enable_mask);
860
861 v = __raw_readl(dd->control_reg) & dd->enable_mask;
862 v >>= __ffs(dd->enable_mask);
863 if (v != OMAP3XXX_EN_DPLL_LOCKED)
864 rate = clk->parent->rate;
865 else
866 rate = clk->parent->rate * 2;
867 return rate;
868 }
869
870 /* Common clock code */
871
872 /*
873 * As it is structured now, this will prevent an OMAP2/3 multiboot
874 * kernel from compiling. This will need further attention.
875 */
876 #if defined(CONFIG_ARCH_OMAP3)
877
878 static struct clk_functions omap2_clk_functions = {
879 .clk_enable = omap2_clk_enable,
880 .clk_disable = omap2_clk_disable,
881 .clk_round_rate = omap2_clk_round_rate,
882 .clk_set_rate = omap2_clk_set_rate,
883 .clk_set_parent = omap2_clk_set_parent,
884 .clk_disable_unused = omap2_clk_disable_unused,
885 };
886
887 /*
888 * Set clocks for bypass mode for reboot to work.
889 */
890 void omap2_clk_prepare_for_reboot(void)
891 {
892 /* REVISIT: Not ready for 343x */
893 #if 0
894 u32 rate;
895
896 if (vclk == NULL || sclk == NULL)
897 return;
898
899 rate = clk_get_rate(sclk);
900 clk_set_rate(vclk, rate);
901 #endif
902 }
903
904 /* REVISIT: Move this init stuff out into clock.c */
905
906 /*
907 * Switch the MPU rate if specified on cmdline.
908 * We cannot do this early until cmdline is parsed.
909 */
910 static int __init omap2_clk_arch_init(void)
911 {
912 if (!mpurate)
913 return -EINVAL;
914
915 /* REVISIT: not yet ready for 343x */
916 #if 0
917 if (clk_set_rate(&virt_prcm_set, mpurate))
918 printk(KERN_ERR "Could not find matching MPU rate\n");
919 #endif
920
921 recalculate_root_clocks();
922
923 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
924 "%ld.%01ld/%ld/%ld MHz\n",
925 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
926 (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
927
928 return 0;
929 }
930 arch_initcall(omap2_clk_arch_init);
931
932 int __init omap2_clk_init(void)
933 {
934 /* struct prcm_config *prcm; */
935 struct omap_clk *c;
936 /* u32 clkrate; */
937 u32 cpu_clkflg;
938
939 if (cpu_is_omap34xx()) {
940 cpu_mask = RATE_IN_343X;
941 cpu_clkflg = CK_343X;
942
943 /*
944 * Update this if there are further clock changes between ES2
945 * and production parts
946 */
947 if (omap_rev() == OMAP3430_REV_ES1_0) {
948 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
949 cpu_clkflg |= CK_3430ES1;
950 } else {
951 cpu_mask |= RATE_IN_3430ES2;
952 cpu_clkflg |= CK_3430ES2;
953 }
954 }
955
956 clk_init(&omap2_clk_functions);
957
958 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
959 clk_init_one(c->lk.clk);
960
961 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
962 if (c->cpu & cpu_clkflg) {
963 clkdev_add(&c->lk);
964 clk_register(c->lk.clk);
965 omap2_init_clk_clkdm(c->lk.clk);
966 }
967
968 /* REVISIT: Not yet ready for OMAP3 */
969 #if 0
970 /* Check the MPU rate set by bootloader */
971 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
972 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
973 if (!(prcm->flags & cpu_mask))
974 continue;
975 if (prcm->xtal_speed != sys_ck.rate)
976 continue;
977 if (prcm->dpll_speed <= clkrate)
978 break;
979 }
980 curr_prcm_set = prcm;
981 #endif
982
983 recalculate_root_clocks();
984
985 printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
986 "%ld.%01ld/%ld/%ld MHz\n",
987 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
988 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
989
990 /*
991 * Only enable those clocks we will need, let the drivers
992 * enable other clocks as necessary
993 */
994 clk_enable_init_clocks();
995
996 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
997 /* REVISIT: not yet ready for 343x */
998 #if 0
999 vclk = clk_get(NULL, "virt_prcm_set");
1000 sclk = clk_get(NULL, "sys_ck");
1001 #endif
1002 return 0;
1003 }
1004
1005 #endif
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