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[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / clock34xx.h
1 /*
2 * OMAP3 clock framework
3 *
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
10 *
11 */
12
13 /*
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
17 */
18
19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
21
22 #include <mach/control.h>
23
24 #include "clock.h"
25 #include "cm.h"
26 #include "cm-regbits-34xx.h"
27 #include "prm.h"
28 #include "prm-regbits-34xx.h"
29
30 static unsigned long omap3_dpll_recalc(struct clk *clk);
31 static unsigned long omap3_clkoutx2_recalc(struct clk *clk);
32 static void omap3_dpll_allow_idle(struct clk *clk);
33 static void omap3_dpll_deny_idle(struct clk *clk);
34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
35 static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
36 static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
37 static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
38
39 /* Maximum DPLL multiplier, divider values for OMAP3 */
40 #define OMAP3_MAX_DPLL_MULT 2048
41 #define OMAP3_MAX_DPLL_DIV 128
42
43 /*
44 * DPLL1 supplies clock to the MPU.
45 * DPLL2 supplies clock to the IVA2.
46 * DPLL3 supplies CORE domain clocks.
47 * DPLL4 supplies peripheral clocks.
48 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
49 */
50
51 /* Forward declarations for DPLL bypass clocks */
52 static struct clk dpll1_fck;
53 static struct clk dpll2_fck;
54
55 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
56 #define DPLL_LOW_POWER_STOP 0x1
57 #define DPLL_LOW_POWER_BYPASS 0x5
58 #define DPLL_LOCKED 0x7
59
60 /* PRM CLOCKS */
61
62 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
63 static struct clk omap_32k_fck = {
64 .name = "omap_32k_fck",
65 .ops = &clkops_null,
66 .rate = 32768,
67 .flags = RATE_FIXED,
68 };
69
70 static struct clk secure_32k_fck = {
71 .name = "secure_32k_fck",
72 .ops = &clkops_null,
73 .rate = 32768,
74 .flags = RATE_FIXED,
75 };
76
77 /* Virtual source clocks for osc_sys_ck */
78 static struct clk virt_12m_ck = {
79 .name = "virt_12m_ck",
80 .ops = &clkops_null,
81 .rate = 12000000,
82 .flags = RATE_FIXED,
83 };
84
85 static struct clk virt_13m_ck = {
86 .name = "virt_13m_ck",
87 .ops = &clkops_null,
88 .rate = 13000000,
89 .flags = RATE_FIXED,
90 };
91
92 static struct clk virt_16_8m_ck = {
93 .name = "virt_16_8m_ck",
94 .ops = &clkops_null,
95 .rate = 16800000,
96 .flags = RATE_FIXED,
97 };
98
99 static struct clk virt_19_2m_ck = {
100 .name = "virt_19_2m_ck",
101 .ops = &clkops_null,
102 .rate = 19200000,
103 .flags = RATE_FIXED,
104 };
105
106 static struct clk virt_26m_ck = {
107 .name = "virt_26m_ck",
108 .ops = &clkops_null,
109 .rate = 26000000,
110 .flags = RATE_FIXED,
111 };
112
113 static struct clk virt_38_4m_ck = {
114 .name = "virt_38_4m_ck",
115 .ops = &clkops_null,
116 .rate = 38400000,
117 .flags = RATE_FIXED,
118 };
119
120 static const struct clksel_rate osc_sys_12m_rates[] = {
121 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
122 { .div = 0 }
123 };
124
125 static const struct clksel_rate osc_sys_13m_rates[] = {
126 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
127 { .div = 0 }
128 };
129
130 static const struct clksel_rate osc_sys_16_8m_rates[] = {
131 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
132 { .div = 0 }
133 };
134
135 static const struct clksel_rate osc_sys_19_2m_rates[] = {
136 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
137 { .div = 0 }
138 };
139
140 static const struct clksel_rate osc_sys_26m_rates[] = {
141 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
142 { .div = 0 }
143 };
144
145 static const struct clksel_rate osc_sys_38_4m_rates[] = {
146 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
147 { .div = 0 }
148 };
149
150 static const struct clksel osc_sys_clksel[] = {
151 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
152 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
153 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
154 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
155 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
156 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
157 { .parent = NULL },
158 };
159
160 /* Oscillator clock */
161 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
162 static struct clk osc_sys_ck = {
163 .name = "osc_sys_ck",
164 .ops = &clkops_null,
165 .init = &omap2_init_clksel_parent,
166 .clksel_reg = OMAP3430_PRM_CLKSEL,
167 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
168 .clksel = osc_sys_clksel,
169 /* REVISIT: deal with autoextclkmode? */
170 .flags = RATE_FIXED,
171 .recalc = &omap2_clksel_recalc,
172 };
173
174 static const struct clksel_rate div2_rates[] = {
175 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
176 { .div = 2, .val = 2, .flags = RATE_IN_343X },
177 { .div = 0 }
178 };
179
180 static const struct clksel sys_clksel[] = {
181 { .parent = &osc_sys_ck, .rates = div2_rates },
182 { .parent = NULL }
183 };
184
185 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
186 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
187 static struct clk sys_ck = {
188 .name = "sys_ck",
189 .ops = &clkops_null,
190 .parent = &osc_sys_ck,
191 .init = &omap2_init_clksel_parent,
192 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
193 .clksel_mask = OMAP_SYSCLKDIV_MASK,
194 .clksel = sys_clksel,
195 .recalc = &omap2_clksel_recalc,
196 };
197
198 static struct clk sys_altclk = {
199 .name = "sys_altclk",
200 .ops = &clkops_null,
201 };
202
203 /* Optional external clock input for some McBSPs */
204 static struct clk mcbsp_clks = {
205 .name = "mcbsp_clks",
206 .ops = &clkops_null,
207 };
208
209 /* PRM EXTERNAL CLOCK OUTPUT */
210
211 static struct clk sys_clkout1 = {
212 .name = "sys_clkout1",
213 .ops = &clkops_omap2_dflt,
214 .parent = &osc_sys_ck,
215 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
216 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
217 .recalc = &followparent_recalc,
218 };
219
220 /* DPLLS */
221
222 /* CM CLOCKS */
223
224 static const struct clksel_rate div16_dpll_rates[] = {
225 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
226 { .div = 2, .val = 2, .flags = RATE_IN_343X },
227 { .div = 3, .val = 3, .flags = RATE_IN_343X },
228 { .div = 4, .val = 4, .flags = RATE_IN_343X },
229 { .div = 5, .val = 5, .flags = RATE_IN_343X },
230 { .div = 6, .val = 6, .flags = RATE_IN_343X },
231 { .div = 7, .val = 7, .flags = RATE_IN_343X },
232 { .div = 8, .val = 8, .flags = RATE_IN_343X },
233 { .div = 9, .val = 9, .flags = RATE_IN_343X },
234 { .div = 10, .val = 10, .flags = RATE_IN_343X },
235 { .div = 11, .val = 11, .flags = RATE_IN_343X },
236 { .div = 12, .val = 12, .flags = RATE_IN_343X },
237 { .div = 13, .val = 13, .flags = RATE_IN_343X },
238 { .div = 14, .val = 14, .flags = RATE_IN_343X },
239 { .div = 15, .val = 15, .flags = RATE_IN_343X },
240 { .div = 16, .val = 16, .flags = RATE_IN_343X },
241 { .div = 0 }
242 };
243
244 /* DPLL1 */
245 /* MPU clock source */
246 /* Type: DPLL */
247 static struct dpll_data dpll1_dd = {
248 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
249 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
250 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
251 .clk_bypass = &dpll1_fck,
252 .clk_ref = &sys_ck,
253 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
254 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
255 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
256 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
257 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
258 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
259 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
260 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
261 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
262 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
263 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
264 .max_multiplier = OMAP3_MAX_DPLL_MULT,
265 .min_divider = 1,
266 .max_divider = OMAP3_MAX_DPLL_DIV,
267 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
268 };
269
270 static struct clk dpll1_ck = {
271 .name = "dpll1_ck",
272 .ops = &clkops_null,
273 .parent = &sys_ck,
274 .dpll_data = &dpll1_dd,
275 .round_rate = &omap2_dpll_round_rate,
276 .set_rate = &omap3_noncore_dpll_set_rate,
277 .clkdm_name = "dpll1_clkdm",
278 .recalc = &omap3_dpll_recalc,
279 };
280
281 /*
282 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
283 * DPLL isn't bypassed.
284 */
285 static struct clk dpll1_x2_ck = {
286 .name = "dpll1_x2_ck",
287 .ops = &clkops_null,
288 .parent = &dpll1_ck,
289 .clkdm_name = "dpll1_clkdm",
290 .recalc = &omap3_clkoutx2_recalc,
291 };
292
293 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
294 static const struct clksel div16_dpll1_x2m2_clksel[] = {
295 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
296 { .parent = NULL }
297 };
298
299 /*
300 * Does not exist in the TRM - needed to separate the M2 divider from
301 * bypass selection in mpu_ck
302 */
303 static struct clk dpll1_x2m2_ck = {
304 .name = "dpll1_x2m2_ck",
305 .ops = &clkops_null,
306 .parent = &dpll1_x2_ck,
307 .init = &omap2_init_clksel_parent,
308 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
309 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
310 .clksel = div16_dpll1_x2m2_clksel,
311 .clkdm_name = "dpll1_clkdm",
312 .recalc = &omap2_clksel_recalc,
313 };
314
315 /* DPLL2 */
316 /* IVA2 clock source */
317 /* Type: DPLL */
318
319 static struct dpll_data dpll2_dd = {
320 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
321 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
322 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
323 .clk_bypass = &dpll2_fck,
324 .clk_ref = &sys_ck,
325 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
326 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
327 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
328 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
329 (1 << DPLL_LOW_POWER_BYPASS),
330 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
331 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
332 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
333 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
334 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
335 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
336 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
337 .max_multiplier = OMAP3_MAX_DPLL_MULT,
338 .min_divider = 1,
339 .max_divider = OMAP3_MAX_DPLL_DIV,
340 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
341 };
342
343 static struct clk dpll2_ck = {
344 .name = "dpll2_ck",
345 .ops = &clkops_noncore_dpll_ops,
346 .parent = &sys_ck,
347 .dpll_data = &dpll2_dd,
348 .round_rate = &omap2_dpll_round_rate,
349 .set_rate = &omap3_noncore_dpll_set_rate,
350 .clkdm_name = "dpll2_clkdm",
351 .recalc = &omap3_dpll_recalc,
352 };
353
354 static const struct clksel div16_dpll2_m2x2_clksel[] = {
355 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
356 { .parent = NULL }
357 };
358
359 /*
360 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
361 * or CLKOUTX2. CLKOUT seems most plausible.
362 */
363 static struct clk dpll2_m2_ck = {
364 .name = "dpll2_m2_ck",
365 .ops = &clkops_null,
366 .parent = &dpll2_ck,
367 .init = &omap2_init_clksel_parent,
368 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
369 OMAP3430_CM_CLKSEL2_PLL),
370 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
371 .clksel = div16_dpll2_m2x2_clksel,
372 .clkdm_name = "dpll2_clkdm",
373 .recalc = &omap2_clksel_recalc,
374 };
375
376 /*
377 * DPLL3
378 * Source clock for all interfaces and for some device fclks
379 * REVISIT: Also supports fast relock bypass - not included below
380 */
381 static struct dpll_data dpll3_dd = {
382 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
383 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
384 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
385 .clk_bypass = &sys_ck,
386 .clk_ref = &sys_ck,
387 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
388 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
389 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
390 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
391 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
392 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
393 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
394 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
395 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
396 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
397 .max_multiplier = OMAP3_MAX_DPLL_MULT,
398 .min_divider = 1,
399 .max_divider = OMAP3_MAX_DPLL_DIV,
400 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
401 };
402
403 static struct clk dpll3_ck = {
404 .name = "dpll3_ck",
405 .ops = &clkops_null,
406 .parent = &sys_ck,
407 .dpll_data = &dpll3_dd,
408 .round_rate = &omap2_dpll_round_rate,
409 .clkdm_name = "dpll3_clkdm",
410 .recalc = &omap3_dpll_recalc,
411 };
412
413 /*
414 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
415 * DPLL isn't bypassed
416 */
417 static struct clk dpll3_x2_ck = {
418 .name = "dpll3_x2_ck",
419 .ops = &clkops_null,
420 .parent = &dpll3_ck,
421 .clkdm_name = "dpll3_clkdm",
422 .recalc = &omap3_clkoutx2_recalc,
423 };
424
425 static const struct clksel_rate div31_dpll3_rates[] = {
426 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
427 { .div = 2, .val = 2, .flags = RATE_IN_343X },
428 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
429 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
430 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
431 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
432 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
433 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
434 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
435 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
436 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
437 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
438 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
439 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
440 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
441 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
442 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
443 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
444 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
445 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
446 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
447 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
448 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
449 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
450 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
451 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
452 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
453 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
454 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
455 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
456 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
457 { .div = 0 },
458 };
459
460 static const struct clksel div31_dpll3m2_clksel[] = {
461 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
462 { .parent = NULL }
463 };
464
465 /* DPLL3 output M2 - primary control point for CORE speed */
466 static struct clk dpll3_m2_ck = {
467 .name = "dpll3_m2_ck",
468 .ops = &clkops_null,
469 .parent = &dpll3_ck,
470 .init = &omap2_init_clksel_parent,
471 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
472 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
473 .clksel = div31_dpll3m2_clksel,
474 .clkdm_name = "dpll3_clkdm",
475 .round_rate = &omap2_clksel_round_rate,
476 .set_rate = &omap3_core_dpll_m2_set_rate,
477 .recalc = &omap2_clksel_recalc,
478 };
479
480 static struct clk core_ck = {
481 .name = "core_ck",
482 .ops = &clkops_null,
483 .parent = &dpll3_m2_ck,
484 .recalc = &followparent_recalc,
485 };
486
487 static struct clk dpll3_m2x2_ck = {
488 .name = "dpll3_m2x2_ck",
489 .ops = &clkops_null,
490 .parent = &dpll3_x2_ck,
491 .clkdm_name = "dpll3_clkdm",
492 .recalc = &followparent_recalc,
493 };
494
495 /* The PWRDN bit is apparently only available on 3430ES2 and above */
496 static const struct clksel div16_dpll3_clksel[] = {
497 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
498 { .parent = NULL }
499 };
500
501 /* This virtual clock is the source for dpll3_m3x2_ck */
502 static struct clk dpll3_m3_ck = {
503 .name = "dpll3_m3_ck",
504 .ops = &clkops_null,
505 .parent = &dpll3_ck,
506 .init = &omap2_init_clksel_parent,
507 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
508 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
509 .clksel = div16_dpll3_clksel,
510 .clkdm_name = "dpll3_clkdm",
511 .recalc = &omap2_clksel_recalc,
512 };
513
514 /* The PWRDN bit is apparently only available on 3430ES2 and above */
515 static struct clk dpll3_m3x2_ck = {
516 .name = "dpll3_m3x2_ck",
517 .ops = &clkops_omap2_dflt_wait,
518 .parent = &dpll3_m3_ck,
519 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
520 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
521 .flags = INVERT_ENABLE,
522 .clkdm_name = "dpll3_clkdm",
523 .recalc = &omap3_clkoutx2_recalc,
524 };
525
526 static struct clk emu_core_alwon_ck = {
527 .name = "emu_core_alwon_ck",
528 .ops = &clkops_null,
529 .parent = &dpll3_m3x2_ck,
530 .clkdm_name = "dpll3_clkdm",
531 .recalc = &followparent_recalc,
532 };
533
534 /* DPLL4 */
535 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
536 /* Type: DPLL */
537 static struct dpll_data dpll4_dd = {
538 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
539 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
540 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
541 .clk_bypass = &sys_ck,
542 .clk_ref = &sys_ck,
543 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
544 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
545 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
546 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
547 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
548 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
549 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
550 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
551 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
552 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
553 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
554 .max_multiplier = OMAP3_MAX_DPLL_MULT,
555 .min_divider = 1,
556 .max_divider = OMAP3_MAX_DPLL_DIV,
557 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
558 };
559
560 static struct clk dpll4_ck = {
561 .name = "dpll4_ck",
562 .ops = &clkops_noncore_dpll_ops,
563 .parent = &sys_ck,
564 .dpll_data = &dpll4_dd,
565 .round_rate = &omap2_dpll_round_rate,
566 .set_rate = &omap3_dpll4_set_rate,
567 .clkdm_name = "dpll4_clkdm",
568 .recalc = &omap3_dpll_recalc,
569 };
570
571 /*
572 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
573 * DPLL isn't bypassed --
574 * XXX does this serve any downstream clocks?
575 */
576 static struct clk dpll4_x2_ck = {
577 .name = "dpll4_x2_ck",
578 .ops = &clkops_null,
579 .parent = &dpll4_ck,
580 .clkdm_name = "dpll4_clkdm",
581 .recalc = &omap3_clkoutx2_recalc,
582 };
583
584 static const struct clksel div16_dpll4_clksel[] = {
585 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
586 { .parent = NULL }
587 };
588
589 /* This virtual clock is the source for dpll4_m2x2_ck */
590 static struct clk dpll4_m2_ck = {
591 .name = "dpll4_m2_ck",
592 .ops = &clkops_null,
593 .parent = &dpll4_ck,
594 .init = &omap2_init_clksel_parent,
595 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
596 .clksel_mask = OMAP3430_DIV_96M_MASK,
597 .clksel = div16_dpll4_clksel,
598 .clkdm_name = "dpll4_clkdm",
599 .recalc = &omap2_clksel_recalc,
600 };
601
602 /* The PWRDN bit is apparently only available on 3430ES2 and above */
603 static struct clk dpll4_m2x2_ck = {
604 .name = "dpll4_m2x2_ck",
605 .ops = &clkops_omap2_dflt_wait,
606 .parent = &dpll4_m2_ck,
607 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
608 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
609 .flags = INVERT_ENABLE,
610 .clkdm_name = "dpll4_clkdm",
611 .recalc = &omap3_clkoutx2_recalc,
612 };
613
614 /*
615 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
616 * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
617 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
618 * CM_96K_(F)CLK.
619 */
620 static struct clk omap_96m_alwon_fck = {
621 .name = "omap_96m_alwon_fck",
622 .ops = &clkops_null,
623 .parent = &dpll4_m2x2_ck,
624 .recalc = &followparent_recalc,
625 };
626
627 static struct clk cm_96m_fck = {
628 .name = "cm_96m_fck",
629 .ops = &clkops_null,
630 .parent = &omap_96m_alwon_fck,
631 .recalc = &followparent_recalc,
632 };
633
634 static const struct clksel_rate omap_96m_dpll_rates[] = {
635 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
636 { .div = 0 }
637 };
638
639 static const struct clksel_rate omap_96m_sys_rates[] = {
640 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
641 { .div = 0 }
642 };
643
644 static const struct clksel omap_96m_fck_clksel[] = {
645 { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
646 { .parent = &sys_ck, .rates = omap_96m_sys_rates },
647 { .parent = NULL }
648 };
649
650 static struct clk omap_96m_fck = {
651 .name = "omap_96m_fck",
652 .ops = &clkops_null,
653 .parent = &sys_ck,
654 .init = &omap2_init_clksel_parent,
655 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
656 .clksel_mask = OMAP3430_SOURCE_96M_MASK,
657 .clksel = omap_96m_fck_clksel,
658 .recalc = &omap2_clksel_recalc,
659 };
660
661 /* This virtual clock is the source for dpll4_m3x2_ck */
662 static struct clk dpll4_m3_ck = {
663 .name = "dpll4_m3_ck",
664 .ops = &clkops_null,
665 .parent = &dpll4_ck,
666 .init = &omap2_init_clksel_parent,
667 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
668 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
669 .clksel = div16_dpll4_clksel,
670 .clkdm_name = "dpll4_clkdm",
671 .recalc = &omap2_clksel_recalc,
672 };
673
674 /* The PWRDN bit is apparently only available on 3430ES2 and above */
675 static struct clk dpll4_m3x2_ck = {
676 .name = "dpll4_m3x2_ck",
677 .ops = &clkops_omap2_dflt_wait,
678 .parent = &dpll4_m3_ck,
679 .init = &omap2_init_clksel_parent,
680 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
681 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
682 .flags = INVERT_ENABLE,
683 .clkdm_name = "dpll4_clkdm",
684 .recalc = &omap3_clkoutx2_recalc,
685 };
686
687 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
688 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
689 { .div = 0 }
690 };
691
692 static const struct clksel_rate omap_54m_alt_rates[] = {
693 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
694 { .div = 0 }
695 };
696
697 static const struct clksel omap_54m_clksel[] = {
698 { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
699 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
700 { .parent = NULL }
701 };
702
703 static struct clk omap_54m_fck = {
704 .name = "omap_54m_fck",
705 .ops = &clkops_null,
706 .init = &omap2_init_clksel_parent,
707 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
708 .clksel_mask = OMAP3430_SOURCE_54M_MASK,
709 .clksel = omap_54m_clksel,
710 .recalc = &omap2_clksel_recalc,
711 };
712
713 static const struct clksel_rate omap_48m_cm96m_rates[] = {
714 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
715 { .div = 0 }
716 };
717
718 static const struct clksel_rate omap_48m_alt_rates[] = {
719 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
720 { .div = 0 }
721 };
722
723 static const struct clksel omap_48m_clksel[] = {
724 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
725 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
726 { .parent = NULL }
727 };
728
729 static struct clk omap_48m_fck = {
730 .name = "omap_48m_fck",
731 .ops = &clkops_null,
732 .init = &omap2_init_clksel_parent,
733 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
734 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
735 .clksel = omap_48m_clksel,
736 .recalc = &omap2_clksel_recalc,
737 };
738
739 static struct clk omap_12m_fck = {
740 .name = "omap_12m_fck",
741 .ops = &clkops_null,
742 .parent = &omap_48m_fck,
743 .fixed_div = 4,
744 .recalc = &omap2_fixed_divisor_recalc,
745 };
746
747 /* This virstual clock is the source for dpll4_m4x2_ck */
748 static struct clk dpll4_m4_ck = {
749 .name = "dpll4_m4_ck",
750 .ops = &clkops_null,
751 .parent = &dpll4_ck,
752 .init = &omap2_init_clksel_parent,
753 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
754 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
755 .clksel = div16_dpll4_clksel,
756 .clkdm_name = "dpll4_clkdm",
757 .recalc = &omap2_clksel_recalc,
758 .set_rate = &omap2_clksel_set_rate,
759 .round_rate = &omap2_clksel_round_rate,
760 };
761
762 /* The PWRDN bit is apparently only available on 3430ES2 and above */
763 static struct clk dpll4_m4x2_ck = {
764 .name = "dpll4_m4x2_ck",
765 .ops = &clkops_omap2_dflt_wait,
766 .parent = &dpll4_m4_ck,
767 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
768 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
769 .flags = INVERT_ENABLE,
770 .clkdm_name = "dpll4_clkdm",
771 .recalc = &omap3_clkoutx2_recalc,
772 };
773
774 /* This virtual clock is the source for dpll4_m5x2_ck */
775 static struct clk dpll4_m5_ck = {
776 .name = "dpll4_m5_ck",
777 .ops = &clkops_null,
778 .parent = &dpll4_ck,
779 .init = &omap2_init_clksel_parent,
780 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
781 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
782 .clksel = div16_dpll4_clksel,
783 .clkdm_name = "dpll4_clkdm",
784 .recalc = &omap2_clksel_recalc,
785 };
786
787 /* The PWRDN bit is apparently only available on 3430ES2 and above */
788 static struct clk dpll4_m5x2_ck = {
789 .name = "dpll4_m5x2_ck",
790 .ops = &clkops_omap2_dflt_wait,
791 .parent = &dpll4_m5_ck,
792 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
793 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
794 .flags = INVERT_ENABLE,
795 .clkdm_name = "dpll4_clkdm",
796 .recalc = &omap3_clkoutx2_recalc,
797 };
798
799 /* This virtual clock is the source for dpll4_m6x2_ck */
800 static struct clk dpll4_m6_ck = {
801 .name = "dpll4_m6_ck",
802 .ops = &clkops_null,
803 .parent = &dpll4_ck,
804 .init = &omap2_init_clksel_parent,
805 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
806 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
807 .clksel = div16_dpll4_clksel,
808 .clkdm_name = "dpll4_clkdm",
809 .recalc = &omap2_clksel_recalc,
810 };
811
812 /* The PWRDN bit is apparently only available on 3430ES2 and above */
813 static struct clk dpll4_m6x2_ck = {
814 .name = "dpll4_m6x2_ck",
815 .ops = &clkops_omap2_dflt_wait,
816 .parent = &dpll4_m6_ck,
817 .init = &omap2_init_clksel_parent,
818 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
819 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
820 .flags = INVERT_ENABLE,
821 .clkdm_name = "dpll4_clkdm",
822 .recalc = &omap3_clkoutx2_recalc,
823 };
824
825 static struct clk emu_per_alwon_ck = {
826 .name = "emu_per_alwon_ck",
827 .ops = &clkops_null,
828 .parent = &dpll4_m6x2_ck,
829 .clkdm_name = "dpll4_clkdm",
830 .recalc = &followparent_recalc,
831 };
832
833 /* DPLL5 */
834 /* Supplies 120MHz clock, USIM source clock */
835 /* Type: DPLL */
836 /* 3430ES2 only */
837 static struct dpll_data dpll5_dd = {
838 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
839 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
840 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
841 .clk_bypass = &sys_ck,
842 .clk_ref = &sys_ck,
843 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
844 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
845 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
846 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
847 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
848 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
849 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
850 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
851 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
852 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
853 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
854 .max_multiplier = OMAP3_MAX_DPLL_MULT,
855 .min_divider = 1,
856 .max_divider = OMAP3_MAX_DPLL_DIV,
857 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
858 };
859
860 static struct clk dpll5_ck = {
861 .name = "dpll5_ck",
862 .ops = &clkops_noncore_dpll_ops,
863 .parent = &sys_ck,
864 .dpll_data = &dpll5_dd,
865 .round_rate = &omap2_dpll_round_rate,
866 .set_rate = &omap3_noncore_dpll_set_rate,
867 .clkdm_name = "dpll5_clkdm",
868 .recalc = &omap3_dpll_recalc,
869 };
870
871 static const struct clksel div16_dpll5_clksel[] = {
872 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
873 { .parent = NULL }
874 };
875
876 static struct clk dpll5_m2_ck = {
877 .name = "dpll5_m2_ck",
878 .ops = &clkops_null,
879 .parent = &dpll5_ck,
880 .init = &omap2_init_clksel_parent,
881 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
882 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
883 .clksel = div16_dpll5_clksel,
884 .clkdm_name = "dpll5_clkdm",
885 .recalc = &omap2_clksel_recalc,
886 };
887
888 /* CM EXTERNAL CLOCK OUTPUTS */
889
890 static const struct clksel_rate clkout2_src_core_rates[] = {
891 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
892 { .div = 0 }
893 };
894
895 static const struct clksel_rate clkout2_src_sys_rates[] = {
896 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
897 { .div = 0 }
898 };
899
900 static const struct clksel_rate clkout2_src_96m_rates[] = {
901 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
902 { .div = 0 }
903 };
904
905 static const struct clksel_rate clkout2_src_54m_rates[] = {
906 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
907 { .div = 0 }
908 };
909
910 static const struct clksel clkout2_src_clksel[] = {
911 { .parent = &core_ck, .rates = clkout2_src_core_rates },
912 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
913 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
914 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
915 { .parent = NULL }
916 };
917
918 static struct clk clkout2_src_ck = {
919 .name = "clkout2_src_ck",
920 .ops = &clkops_omap2_dflt,
921 .init = &omap2_init_clksel_parent,
922 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
923 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
924 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
925 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
926 .clksel = clkout2_src_clksel,
927 .clkdm_name = "core_clkdm",
928 .recalc = &omap2_clksel_recalc,
929 };
930
931 static const struct clksel_rate sys_clkout2_rates[] = {
932 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
933 { .div = 2, .val = 1, .flags = RATE_IN_343X },
934 { .div = 4, .val = 2, .flags = RATE_IN_343X },
935 { .div = 8, .val = 3, .flags = RATE_IN_343X },
936 { .div = 16, .val = 4, .flags = RATE_IN_343X },
937 { .div = 0 },
938 };
939
940 static const struct clksel sys_clkout2_clksel[] = {
941 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
942 { .parent = NULL },
943 };
944
945 static struct clk sys_clkout2 = {
946 .name = "sys_clkout2",
947 .ops = &clkops_null,
948 .init = &omap2_init_clksel_parent,
949 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
950 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
951 .clksel = sys_clkout2_clksel,
952 .recalc = &omap2_clksel_recalc,
953 };
954
955 /* CM OUTPUT CLOCKS */
956
957 static struct clk corex2_fck = {
958 .name = "corex2_fck",
959 .ops = &clkops_null,
960 .parent = &dpll3_m2x2_ck,
961 .recalc = &followparent_recalc,
962 };
963
964 /* DPLL power domain clock controls */
965
966 static const struct clksel_rate div4_rates[] = {
967 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
968 { .div = 2, .val = 2, .flags = RATE_IN_343X },
969 { .div = 4, .val = 4, .flags = RATE_IN_343X },
970 { .div = 0 }
971 };
972
973 static const struct clksel div4_core_clksel[] = {
974 { .parent = &core_ck, .rates = div4_rates },
975 { .parent = NULL }
976 };
977
978 /*
979 * REVISIT: Are these in DPLL power domain or CM power domain? docs
980 * may be inconsistent here?
981 */
982 static struct clk dpll1_fck = {
983 .name = "dpll1_fck",
984 .ops = &clkops_null,
985 .parent = &core_ck,
986 .init = &omap2_init_clksel_parent,
987 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
988 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
989 .clksel = div4_core_clksel,
990 .recalc = &omap2_clksel_recalc,
991 };
992
993 static struct clk mpu_ck = {
994 .name = "mpu_ck",
995 .ops = &clkops_null,
996 .parent = &dpll1_x2m2_ck,
997 .clkdm_name = "mpu_clkdm",
998 .recalc = &followparent_recalc,
999 };
1000
1001 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1002 static const struct clksel_rate arm_fck_rates[] = {
1003 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1004 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1005 { .div = 0 },
1006 };
1007
1008 static const struct clksel arm_fck_clksel[] = {
1009 { .parent = &mpu_ck, .rates = arm_fck_rates },
1010 { .parent = NULL }
1011 };
1012
1013 static struct clk arm_fck = {
1014 .name = "arm_fck",
1015 .ops = &clkops_null,
1016 .parent = &mpu_ck,
1017 .init = &omap2_init_clksel_parent,
1018 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1019 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1020 .clksel = arm_fck_clksel,
1021 .recalc = &omap2_clksel_recalc,
1022 };
1023
1024 /* XXX What about neon_clkdm ? */
1025
1026 /*
1027 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1028 * although it is referenced - so this is a guess
1029 */
1030 static struct clk emu_mpu_alwon_ck = {
1031 .name = "emu_mpu_alwon_ck",
1032 .ops = &clkops_null,
1033 .parent = &mpu_ck,
1034 .recalc = &followparent_recalc,
1035 };
1036
1037 static struct clk dpll2_fck = {
1038 .name = "dpll2_fck",
1039 .ops = &clkops_null,
1040 .parent = &core_ck,
1041 .init = &omap2_init_clksel_parent,
1042 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1043 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1044 .clksel = div4_core_clksel,
1045 .recalc = &omap2_clksel_recalc,
1046 };
1047
1048 static struct clk iva2_ck = {
1049 .name = "iva2_ck",
1050 .ops = &clkops_omap2_dflt_wait,
1051 .parent = &dpll2_m2_ck,
1052 .init = &omap2_init_clksel_parent,
1053 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1054 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1055 .clkdm_name = "iva2_clkdm",
1056 .recalc = &followparent_recalc,
1057 };
1058
1059 /* Common interface clocks */
1060
1061 static const struct clksel div2_core_clksel[] = {
1062 { .parent = &core_ck, .rates = div2_rates },
1063 { .parent = NULL }
1064 };
1065
1066 static struct clk l3_ick = {
1067 .name = "l3_ick",
1068 .ops = &clkops_null,
1069 .parent = &core_ck,
1070 .init = &omap2_init_clksel_parent,
1071 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1072 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1073 .clksel = div2_core_clksel,
1074 .clkdm_name = "core_l3_clkdm",
1075 .recalc = &omap2_clksel_recalc,
1076 };
1077
1078 static const struct clksel div2_l3_clksel[] = {
1079 { .parent = &l3_ick, .rates = div2_rates },
1080 { .parent = NULL }
1081 };
1082
1083 static struct clk l4_ick = {
1084 .name = "l4_ick",
1085 .ops = &clkops_null,
1086 .parent = &l3_ick,
1087 .init = &omap2_init_clksel_parent,
1088 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1089 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1090 .clksel = div2_l3_clksel,
1091 .clkdm_name = "core_l4_clkdm",
1092 .recalc = &omap2_clksel_recalc,
1093
1094 };
1095
1096 static const struct clksel div2_l4_clksel[] = {
1097 { .parent = &l4_ick, .rates = div2_rates },
1098 { .parent = NULL }
1099 };
1100
1101 static struct clk rm_ick = {
1102 .name = "rm_ick",
1103 .ops = &clkops_null,
1104 .parent = &l4_ick,
1105 .init = &omap2_init_clksel_parent,
1106 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1107 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1108 .clksel = div2_l4_clksel,
1109 .recalc = &omap2_clksel_recalc,
1110 };
1111
1112 /* GFX power domain */
1113
1114 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1115
1116 static const struct clksel gfx_l3_clksel[] = {
1117 { .parent = &l3_ick, .rates = gfx_l3_rates },
1118 { .parent = NULL }
1119 };
1120
1121 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1122 static struct clk gfx_l3_ck = {
1123 .name = "gfx_l3_ck",
1124 .ops = &clkops_omap2_dflt_wait,
1125 .parent = &l3_ick,
1126 .init = &omap2_init_clksel_parent,
1127 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1128 .enable_bit = OMAP_EN_GFX_SHIFT,
1129 .recalc = &followparent_recalc,
1130 };
1131
1132 static struct clk gfx_l3_fck = {
1133 .name = "gfx_l3_fck",
1134 .ops = &clkops_null,
1135 .parent = &gfx_l3_ck,
1136 .init = &omap2_init_clksel_parent,
1137 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1138 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1139 .clksel = gfx_l3_clksel,
1140 .clkdm_name = "gfx_3430es1_clkdm",
1141 .recalc = &omap2_clksel_recalc,
1142 };
1143
1144 static struct clk gfx_l3_ick = {
1145 .name = "gfx_l3_ick",
1146 .ops = &clkops_null,
1147 .parent = &gfx_l3_ck,
1148 .clkdm_name = "gfx_3430es1_clkdm",
1149 .recalc = &followparent_recalc,
1150 };
1151
1152 static struct clk gfx_cg1_ck = {
1153 .name = "gfx_cg1_ck",
1154 .ops = &clkops_omap2_dflt_wait,
1155 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1156 .init = &omap2_init_clk_clkdm,
1157 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1158 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1159 .clkdm_name = "gfx_3430es1_clkdm",
1160 .recalc = &followparent_recalc,
1161 };
1162
1163 static struct clk gfx_cg2_ck = {
1164 .name = "gfx_cg2_ck",
1165 .ops = &clkops_omap2_dflt_wait,
1166 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1167 .init = &omap2_init_clk_clkdm,
1168 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1169 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1170 .clkdm_name = "gfx_3430es1_clkdm",
1171 .recalc = &followparent_recalc,
1172 };
1173
1174 /* SGX power domain - 3430ES2 only */
1175
1176 static const struct clksel_rate sgx_core_rates[] = {
1177 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1178 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1179 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1180 { .div = 0 },
1181 };
1182
1183 static const struct clksel_rate sgx_96m_rates[] = {
1184 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1185 { .div = 0 },
1186 };
1187
1188 static const struct clksel sgx_clksel[] = {
1189 { .parent = &core_ck, .rates = sgx_core_rates },
1190 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1191 { .parent = NULL },
1192 };
1193
1194 static struct clk sgx_fck = {
1195 .name = "sgx_fck",
1196 .ops = &clkops_omap2_dflt_wait,
1197 .init = &omap2_init_clksel_parent,
1198 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1199 .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1200 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1201 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1202 .clksel = sgx_clksel,
1203 .clkdm_name = "sgx_clkdm",
1204 .recalc = &omap2_clksel_recalc,
1205 };
1206
1207 static struct clk sgx_ick = {
1208 .name = "sgx_ick",
1209 .ops = &clkops_omap2_dflt_wait,
1210 .parent = &l3_ick,
1211 .init = &omap2_init_clk_clkdm,
1212 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1213 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1214 .clkdm_name = "sgx_clkdm",
1215 .recalc = &followparent_recalc,
1216 };
1217
1218 /* CORE power domain */
1219
1220 static struct clk d2d_26m_fck = {
1221 .name = "d2d_26m_fck",
1222 .ops = &clkops_omap2_dflt_wait,
1223 .parent = &sys_ck,
1224 .init = &omap2_init_clk_clkdm,
1225 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1226 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1227 .clkdm_name = "d2d_clkdm",
1228 .recalc = &followparent_recalc,
1229 };
1230
1231 static const struct clksel omap343x_gpt_clksel[] = {
1232 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1233 { .parent = &sys_ck, .rates = gpt_sys_rates },
1234 { .parent = NULL}
1235 };
1236
1237 static struct clk gpt10_fck = {
1238 .name = "gpt10_fck",
1239 .ops = &clkops_omap2_dflt_wait,
1240 .parent = &sys_ck,
1241 .init = &omap2_init_clksel_parent,
1242 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1243 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1244 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1245 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1246 .clksel = omap343x_gpt_clksel,
1247 .clkdm_name = "core_l4_clkdm",
1248 .recalc = &omap2_clksel_recalc,
1249 };
1250
1251 static struct clk gpt11_fck = {
1252 .name = "gpt11_fck",
1253 .ops = &clkops_omap2_dflt_wait,
1254 .parent = &sys_ck,
1255 .init = &omap2_init_clksel_parent,
1256 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1257 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1258 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1259 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1260 .clksel = omap343x_gpt_clksel,
1261 .clkdm_name = "core_l4_clkdm",
1262 .recalc = &omap2_clksel_recalc,
1263 };
1264
1265 static struct clk cpefuse_fck = {
1266 .name = "cpefuse_fck",
1267 .ops = &clkops_omap2_dflt,
1268 .parent = &sys_ck,
1269 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1270 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1271 .recalc = &followparent_recalc,
1272 };
1273
1274 static struct clk ts_fck = {
1275 .name = "ts_fck",
1276 .ops = &clkops_omap2_dflt,
1277 .parent = &omap_32k_fck,
1278 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1279 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1280 .recalc = &followparent_recalc,
1281 };
1282
1283 static struct clk usbtll_fck = {
1284 .name = "usbtll_fck",
1285 .ops = &clkops_omap2_dflt,
1286 .parent = &dpll5_m2_ck,
1287 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1288 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1289 .recalc = &followparent_recalc,
1290 };
1291
1292 /* CORE 96M FCLK-derived clocks */
1293
1294 static struct clk core_96m_fck = {
1295 .name = "core_96m_fck",
1296 .ops = &clkops_null,
1297 .parent = &omap_96m_fck,
1298 .clkdm_name = "core_l4_clkdm",
1299 .recalc = &followparent_recalc,
1300 };
1301
1302 static struct clk mmchs3_fck = {
1303 .name = "mmchs_fck",
1304 .ops = &clkops_omap2_dflt_wait,
1305 .id = 2,
1306 .parent = &core_96m_fck,
1307 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1308 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1309 .clkdm_name = "core_l4_clkdm",
1310 .recalc = &followparent_recalc,
1311 };
1312
1313 static struct clk mmchs2_fck = {
1314 .name = "mmchs_fck",
1315 .ops = &clkops_omap2_dflt_wait,
1316 .id = 1,
1317 .parent = &core_96m_fck,
1318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1319 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1320 .clkdm_name = "core_l4_clkdm",
1321 .recalc = &followparent_recalc,
1322 };
1323
1324 static struct clk mspro_fck = {
1325 .name = "mspro_fck",
1326 .ops = &clkops_omap2_dflt_wait,
1327 .parent = &core_96m_fck,
1328 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1329 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1330 .clkdm_name = "core_l4_clkdm",
1331 .recalc = &followparent_recalc,
1332 };
1333
1334 static struct clk mmchs1_fck = {
1335 .name = "mmchs_fck",
1336 .ops = &clkops_omap2_dflt_wait,
1337 .parent = &core_96m_fck,
1338 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1339 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1340 .clkdm_name = "core_l4_clkdm",
1341 .recalc = &followparent_recalc,
1342 };
1343
1344 static struct clk i2c3_fck = {
1345 .name = "i2c_fck",
1346 .ops = &clkops_omap2_dflt_wait,
1347 .id = 3,
1348 .parent = &core_96m_fck,
1349 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1350 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1351 .clkdm_name = "core_l4_clkdm",
1352 .recalc = &followparent_recalc,
1353 };
1354
1355 static struct clk i2c2_fck = {
1356 .name = "i2c_fck",
1357 .ops = &clkops_omap2_dflt_wait,
1358 .id = 2,
1359 .parent = &core_96m_fck,
1360 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1361 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1362 .clkdm_name = "core_l4_clkdm",
1363 .recalc = &followparent_recalc,
1364 };
1365
1366 static struct clk i2c1_fck = {
1367 .name = "i2c_fck",
1368 .ops = &clkops_omap2_dflt_wait,
1369 .id = 1,
1370 .parent = &core_96m_fck,
1371 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1372 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1373 .clkdm_name = "core_l4_clkdm",
1374 .recalc = &followparent_recalc,
1375 };
1376
1377 /*
1378 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1379 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1380 */
1381 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1382 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1383 { .div = 0 }
1384 };
1385
1386 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1387 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1388 { .div = 0 }
1389 };
1390
1391 static const struct clksel mcbsp_15_clksel[] = {
1392 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1393 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1394 { .parent = NULL }
1395 };
1396
1397 static struct clk mcbsp5_fck = {
1398 .name = "mcbsp_fck",
1399 .ops = &clkops_omap2_dflt_wait,
1400 .id = 5,
1401 .init = &omap2_init_clksel_parent,
1402 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1403 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1404 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1405 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1406 .clksel = mcbsp_15_clksel,
1407 .clkdm_name = "core_l4_clkdm",
1408 .recalc = &omap2_clksel_recalc,
1409 };
1410
1411 static struct clk mcbsp1_fck = {
1412 .name = "mcbsp_fck",
1413 .ops = &clkops_omap2_dflt_wait,
1414 .id = 1,
1415 .init = &omap2_init_clksel_parent,
1416 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1417 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1418 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1419 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1420 .clksel = mcbsp_15_clksel,
1421 .clkdm_name = "core_l4_clkdm",
1422 .recalc = &omap2_clksel_recalc,
1423 };
1424
1425 /* CORE_48M_FCK-derived clocks */
1426
1427 static struct clk core_48m_fck = {
1428 .name = "core_48m_fck",
1429 .ops = &clkops_null,
1430 .parent = &omap_48m_fck,
1431 .clkdm_name = "core_l4_clkdm",
1432 .recalc = &followparent_recalc,
1433 };
1434
1435 static struct clk mcspi4_fck = {
1436 .name = "mcspi_fck",
1437 .ops = &clkops_omap2_dflt_wait,
1438 .id = 4,
1439 .parent = &core_48m_fck,
1440 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1441 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1442 .recalc = &followparent_recalc,
1443 };
1444
1445 static struct clk mcspi3_fck = {
1446 .name = "mcspi_fck",
1447 .ops = &clkops_omap2_dflt_wait,
1448 .id = 3,
1449 .parent = &core_48m_fck,
1450 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1451 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1452 .recalc = &followparent_recalc,
1453 };
1454
1455 static struct clk mcspi2_fck = {
1456 .name = "mcspi_fck",
1457 .ops = &clkops_omap2_dflt_wait,
1458 .id = 2,
1459 .parent = &core_48m_fck,
1460 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1461 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1462 .recalc = &followparent_recalc,
1463 };
1464
1465 static struct clk mcspi1_fck = {
1466 .name = "mcspi_fck",
1467 .ops = &clkops_omap2_dflt_wait,
1468 .id = 1,
1469 .parent = &core_48m_fck,
1470 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1471 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1472 .recalc = &followparent_recalc,
1473 };
1474
1475 static struct clk uart2_fck = {
1476 .name = "uart2_fck",
1477 .ops = &clkops_omap2_dflt_wait,
1478 .parent = &core_48m_fck,
1479 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1480 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1481 .recalc = &followparent_recalc,
1482 };
1483
1484 static struct clk uart1_fck = {
1485 .name = "uart1_fck",
1486 .ops = &clkops_omap2_dflt_wait,
1487 .parent = &core_48m_fck,
1488 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1489 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1490 .recalc = &followparent_recalc,
1491 };
1492
1493 static struct clk fshostusb_fck = {
1494 .name = "fshostusb_fck",
1495 .ops = &clkops_omap2_dflt_wait,
1496 .parent = &core_48m_fck,
1497 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1498 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1499 .recalc = &followparent_recalc,
1500 };
1501
1502 /* CORE_12M_FCK based clocks */
1503
1504 static struct clk core_12m_fck = {
1505 .name = "core_12m_fck",
1506 .ops = &clkops_null,
1507 .parent = &omap_12m_fck,
1508 .clkdm_name = "core_l4_clkdm",
1509 .recalc = &followparent_recalc,
1510 };
1511
1512 static struct clk hdq_fck = {
1513 .name = "hdq_fck",
1514 .ops = &clkops_omap2_dflt_wait,
1515 .parent = &core_12m_fck,
1516 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1517 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1518 .recalc = &followparent_recalc,
1519 };
1520
1521 /* DPLL3-derived clock */
1522
1523 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1524 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1525 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1526 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1527 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1528 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1529 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1530 { .div = 0 }
1531 };
1532
1533 static const struct clksel ssi_ssr_clksel[] = {
1534 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1535 { .parent = NULL }
1536 };
1537
1538 static struct clk ssi_ssr_fck = {
1539 .name = "ssi_ssr_fck",
1540 .ops = &clkops_omap2_dflt,
1541 .init = &omap2_init_clksel_parent,
1542 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1543 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1544 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1545 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1546 .clksel = ssi_ssr_clksel,
1547 .clkdm_name = "core_l4_clkdm",
1548 .recalc = &omap2_clksel_recalc,
1549 };
1550
1551 static struct clk ssi_sst_fck = {
1552 .name = "ssi_sst_fck",
1553 .ops = &clkops_null,
1554 .parent = &ssi_ssr_fck,
1555 .fixed_div = 2,
1556 .recalc = &omap2_fixed_divisor_recalc,
1557 };
1558
1559
1560
1561 /* CORE_L3_ICK based clocks */
1562
1563 /*
1564 * XXX must add clk_enable/clk_disable for these if standard code won't
1565 * handle it
1566 */
1567 static struct clk core_l3_ick = {
1568 .name = "core_l3_ick",
1569 .ops = &clkops_null,
1570 .parent = &l3_ick,
1571 .init = &omap2_init_clk_clkdm,
1572 .clkdm_name = "core_l3_clkdm",
1573 .recalc = &followparent_recalc,
1574 };
1575
1576 static struct clk hsotgusb_ick = {
1577 .name = "hsotgusb_ick",
1578 .ops = &clkops_omap2_dflt_wait,
1579 .parent = &core_l3_ick,
1580 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1581 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1582 .clkdm_name = "core_l3_clkdm",
1583 .recalc = &followparent_recalc,
1584 };
1585
1586 static struct clk sdrc_ick = {
1587 .name = "sdrc_ick",
1588 .ops = &clkops_omap2_dflt_wait,
1589 .parent = &core_l3_ick,
1590 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1591 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1592 .flags = ENABLE_ON_INIT,
1593 .clkdm_name = "core_l3_clkdm",
1594 .recalc = &followparent_recalc,
1595 };
1596
1597 static struct clk gpmc_fck = {
1598 .name = "gpmc_fck",
1599 .ops = &clkops_null,
1600 .parent = &core_l3_ick,
1601 .flags = ENABLE_ON_INIT, /* huh? */
1602 .clkdm_name = "core_l3_clkdm",
1603 .recalc = &followparent_recalc,
1604 };
1605
1606 /* SECURITY_L3_ICK based clocks */
1607
1608 static struct clk security_l3_ick = {
1609 .name = "security_l3_ick",
1610 .ops = &clkops_null,
1611 .parent = &l3_ick,
1612 .recalc = &followparent_recalc,
1613 };
1614
1615 static struct clk pka_ick = {
1616 .name = "pka_ick",
1617 .ops = &clkops_omap2_dflt_wait,
1618 .parent = &security_l3_ick,
1619 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1620 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1621 .recalc = &followparent_recalc,
1622 };
1623
1624 /* CORE_L4_ICK based clocks */
1625
1626 static struct clk core_l4_ick = {
1627 .name = "core_l4_ick",
1628 .ops = &clkops_null,
1629 .parent = &l4_ick,
1630 .init = &omap2_init_clk_clkdm,
1631 .clkdm_name = "core_l4_clkdm",
1632 .recalc = &followparent_recalc,
1633 };
1634
1635 static struct clk usbtll_ick = {
1636 .name = "usbtll_ick",
1637 .ops = &clkops_omap2_dflt_wait,
1638 .parent = &core_l4_ick,
1639 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1640 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1641 .clkdm_name = "core_l4_clkdm",
1642 .recalc = &followparent_recalc,
1643 };
1644
1645 static struct clk mmchs3_ick = {
1646 .name = "mmchs_ick",
1647 .ops = &clkops_omap2_dflt_wait,
1648 .id = 2,
1649 .parent = &core_l4_ick,
1650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1651 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1652 .clkdm_name = "core_l4_clkdm",
1653 .recalc = &followparent_recalc,
1654 };
1655
1656 /* Intersystem Communication Registers - chassis mode only */
1657 static struct clk icr_ick = {
1658 .name = "icr_ick",
1659 .ops = &clkops_omap2_dflt_wait,
1660 .parent = &core_l4_ick,
1661 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1662 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1663 .clkdm_name = "core_l4_clkdm",
1664 .recalc = &followparent_recalc,
1665 };
1666
1667 static struct clk aes2_ick = {
1668 .name = "aes2_ick",
1669 .ops = &clkops_omap2_dflt_wait,
1670 .parent = &core_l4_ick,
1671 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1672 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1673 .clkdm_name = "core_l4_clkdm",
1674 .recalc = &followparent_recalc,
1675 };
1676
1677 static struct clk sha12_ick = {
1678 .name = "sha12_ick",
1679 .ops = &clkops_omap2_dflt_wait,
1680 .parent = &core_l4_ick,
1681 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1682 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1683 .clkdm_name = "core_l4_clkdm",
1684 .recalc = &followparent_recalc,
1685 };
1686
1687 static struct clk des2_ick = {
1688 .name = "des2_ick",
1689 .ops = &clkops_omap2_dflt_wait,
1690 .parent = &core_l4_ick,
1691 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1692 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1693 .clkdm_name = "core_l4_clkdm",
1694 .recalc = &followparent_recalc,
1695 };
1696
1697 static struct clk mmchs2_ick = {
1698 .name = "mmchs_ick",
1699 .ops = &clkops_omap2_dflt_wait,
1700 .id = 1,
1701 .parent = &core_l4_ick,
1702 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1703 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1704 .clkdm_name = "core_l4_clkdm",
1705 .recalc = &followparent_recalc,
1706 };
1707
1708 static struct clk mmchs1_ick = {
1709 .name = "mmchs_ick",
1710 .ops = &clkops_omap2_dflt_wait,
1711 .parent = &core_l4_ick,
1712 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1713 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1714 .clkdm_name = "core_l4_clkdm",
1715 .recalc = &followparent_recalc,
1716 };
1717
1718 static struct clk mspro_ick = {
1719 .name = "mspro_ick",
1720 .ops = &clkops_omap2_dflt_wait,
1721 .parent = &core_l4_ick,
1722 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1723 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1724 .clkdm_name = "core_l4_clkdm",
1725 .recalc = &followparent_recalc,
1726 };
1727
1728 static struct clk hdq_ick = {
1729 .name = "hdq_ick",
1730 .ops = &clkops_omap2_dflt_wait,
1731 .parent = &core_l4_ick,
1732 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1733 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1734 .clkdm_name = "core_l4_clkdm",
1735 .recalc = &followparent_recalc,
1736 };
1737
1738 static struct clk mcspi4_ick = {
1739 .name = "mcspi_ick",
1740 .ops = &clkops_omap2_dflt_wait,
1741 .id = 4,
1742 .parent = &core_l4_ick,
1743 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1744 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1745 .clkdm_name = "core_l4_clkdm",
1746 .recalc = &followparent_recalc,
1747 };
1748
1749 static struct clk mcspi3_ick = {
1750 .name = "mcspi_ick",
1751 .ops = &clkops_omap2_dflt_wait,
1752 .id = 3,
1753 .parent = &core_l4_ick,
1754 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1755 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1756 .clkdm_name = "core_l4_clkdm",
1757 .recalc = &followparent_recalc,
1758 };
1759
1760 static struct clk mcspi2_ick = {
1761 .name = "mcspi_ick",
1762 .ops = &clkops_omap2_dflt_wait,
1763 .id = 2,
1764 .parent = &core_l4_ick,
1765 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1766 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1767 .clkdm_name = "core_l4_clkdm",
1768 .recalc = &followparent_recalc,
1769 };
1770
1771 static struct clk mcspi1_ick = {
1772 .name = "mcspi_ick",
1773 .ops = &clkops_omap2_dflt_wait,
1774 .id = 1,
1775 .parent = &core_l4_ick,
1776 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1777 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1778 .clkdm_name = "core_l4_clkdm",
1779 .recalc = &followparent_recalc,
1780 };
1781
1782 static struct clk i2c3_ick = {
1783 .name = "i2c_ick",
1784 .ops = &clkops_omap2_dflt_wait,
1785 .id = 3,
1786 .parent = &core_l4_ick,
1787 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1788 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1789 .clkdm_name = "core_l4_clkdm",
1790 .recalc = &followparent_recalc,
1791 };
1792
1793 static struct clk i2c2_ick = {
1794 .name = "i2c_ick",
1795 .ops = &clkops_omap2_dflt_wait,
1796 .id = 2,
1797 .parent = &core_l4_ick,
1798 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1799 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1800 .clkdm_name = "core_l4_clkdm",
1801 .recalc = &followparent_recalc,
1802 };
1803
1804 static struct clk i2c1_ick = {
1805 .name = "i2c_ick",
1806 .ops = &clkops_omap2_dflt_wait,
1807 .id = 1,
1808 .parent = &core_l4_ick,
1809 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1810 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1811 .clkdm_name = "core_l4_clkdm",
1812 .recalc = &followparent_recalc,
1813 };
1814
1815 static struct clk uart2_ick = {
1816 .name = "uart2_ick",
1817 .ops = &clkops_omap2_dflt_wait,
1818 .parent = &core_l4_ick,
1819 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1820 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1821 .clkdm_name = "core_l4_clkdm",
1822 .recalc = &followparent_recalc,
1823 };
1824
1825 static struct clk uart1_ick = {
1826 .name = "uart1_ick",
1827 .ops = &clkops_omap2_dflt_wait,
1828 .parent = &core_l4_ick,
1829 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1830 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1831 .clkdm_name = "core_l4_clkdm",
1832 .recalc = &followparent_recalc,
1833 };
1834
1835 static struct clk gpt11_ick = {
1836 .name = "gpt11_ick",
1837 .ops = &clkops_omap2_dflt_wait,
1838 .parent = &core_l4_ick,
1839 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1840 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1841 .clkdm_name = "core_l4_clkdm",
1842 .recalc = &followparent_recalc,
1843 };
1844
1845 static struct clk gpt10_ick = {
1846 .name = "gpt10_ick",
1847 .ops = &clkops_omap2_dflt_wait,
1848 .parent = &core_l4_ick,
1849 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1850 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1851 .clkdm_name = "core_l4_clkdm",
1852 .recalc = &followparent_recalc,
1853 };
1854
1855 static struct clk mcbsp5_ick = {
1856 .name = "mcbsp_ick",
1857 .ops = &clkops_omap2_dflt_wait,
1858 .id = 5,
1859 .parent = &core_l4_ick,
1860 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1861 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1862 .clkdm_name = "core_l4_clkdm",
1863 .recalc = &followparent_recalc,
1864 };
1865
1866 static struct clk mcbsp1_ick = {
1867 .name = "mcbsp_ick",
1868 .ops = &clkops_omap2_dflt_wait,
1869 .id = 1,
1870 .parent = &core_l4_ick,
1871 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1872 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1873 .clkdm_name = "core_l4_clkdm",
1874 .recalc = &followparent_recalc,
1875 };
1876
1877 static struct clk fac_ick = {
1878 .name = "fac_ick",
1879 .ops = &clkops_omap2_dflt_wait,
1880 .parent = &core_l4_ick,
1881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1882 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1883 .clkdm_name = "core_l4_clkdm",
1884 .recalc = &followparent_recalc,
1885 };
1886
1887 static struct clk mailboxes_ick = {
1888 .name = "mailboxes_ick",
1889 .ops = &clkops_omap2_dflt_wait,
1890 .parent = &core_l4_ick,
1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1892 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1893 .clkdm_name = "core_l4_clkdm",
1894 .recalc = &followparent_recalc,
1895 };
1896
1897 static struct clk omapctrl_ick = {
1898 .name = "omapctrl_ick",
1899 .ops = &clkops_omap2_dflt_wait,
1900 .parent = &core_l4_ick,
1901 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1902 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
1903 .flags = ENABLE_ON_INIT,
1904 .recalc = &followparent_recalc,
1905 };
1906
1907 /* SSI_L4_ICK based clocks */
1908
1909 static struct clk ssi_l4_ick = {
1910 .name = "ssi_l4_ick",
1911 .ops = &clkops_null,
1912 .parent = &l4_ick,
1913 .clkdm_name = "core_l4_clkdm",
1914 .recalc = &followparent_recalc,
1915 };
1916
1917 static struct clk ssi_ick = {
1918 .name = "ssi_ick",
1919 .ops = &clkops_omap2_dflt,
1920 .parent = &ssi_l4_ick,
1921 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1922 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1923 .clkdm_name = "core_l4_clkdm",
1924 .recalc = &followparent_recalc,
1925 };
1926
1927 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1928 * but l4_ick makes more sense to me */
1929
1930 static const struct clksel usb_l4_clksel[] = {
1931 { .parent = &l4_ick, .rates = div2_rates },
1932 { .parent = NULL },
1933 };
1934
1935 static struct clk usb_l4_ick = {
1936 .name = "usb_l4_ick",
1937 .ops = &clkops_omap2_dflt_wait,
1938 .parent = &l4_ick,
1939 .init = &omap2_init_clksel_parent,
1940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1941 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1942 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1943 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
1944 .clksel = usb_l4_clksel,
1945 .recalc = &omap2_clksel_recalc,
1946 };
1947
1948 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1949
1950 /* SECURITY_L4_ICK2 based clocks */
1951
1952 static struct clk security_l4_ick2 = {
1953 .name = "security_l4_ick2",
1954 .ops = &clkops_null,
1955 .parent = &l4_ick,
1956 .recalc = &followparent_recalc,
1957 };
1958
1959 static struct clk aes1_ick = {
1960 .name = "aes1_ick",
1961 .ops = &clkops_omap2_dflt_wait,
1962 .parent = &security_l4_ick2,
1963 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1964 .enable_bit = OMAP3430_EN_AES1_SHIFT,
1965 .recalc = &followparent_recalc,
1966 };
1967
1968 static struct clk rng_ick = {
1969 .name = "rng_ick",
1970 .ops = &clkops_omap2_dflt_wait,
1971 .parent = &security_l4_ick2,
1972 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1973 .enable_bit = OMAP3430_EN_RNG_SHIFT,
1974 .recalc = &followparent_recalc,
1975 };
1976
1977 static struct clk sha11_ick = {
1978 .name = "sha11_ick",
1979 .ops = &clkops_omap2_dflt_wait,
1980 .parent = &security_l4_ick2,
1981 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1982 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
1983 .recalc = &followparent_recalc,
1984 };
1985
1986 static struct clk des1_ick = {
1987 .name = "des1_ick",
1988 .ops = &clkops_omap2_dflt_wait,
1989 .parent = &security_l4_ick2,
1990 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1991 .enable_bit = OMAP3430_EN_DES1_SHIFT,
1992 .recalc = &followparent_recalc,
1993 };
1994
1995 /* DSS */
1996 static struct clk dss1_alwon_fck = {
1997 .name = "dss1_alwon_fck",
1998 .ops = &clkops_omap2_dflt,
1999 .parent = &dpll4_m4x2_ck,
2000 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2001 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
2002 .clkdm_name = "dss_clkdm",
2003 .recalc = &followparent_recalc,
2004 };
2005
2006 static struct clk dss_tv_fck = {
2007 .name = "dss_tv_fck",
2008 .ops = &clkops_omap2_dflt,
2009 .parent = &omap_54m_fck,
2010 .init = &omap2_init_clk_clkdm,
2011 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2012 .enable_bit = OMAP3430_EN_TV_SHIFT,
2013 .clkdm_name = "dss_clkdm",
2014 .recalc = &followparent_recalc,
2015 };
2016
2017 static struct clk dss_96m_fck = {
2018 .name = "dss_96m_fck",
2019 .ops = &clkops_omap2_dflt,
2020 .parent = &omap_96m_fck,
2021 .init = &omap2_init_clk_clkdm,
2022 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2023 .enable_bit = OMAP3430_EN_TV_SHIFT,
2024 .clkdm_name = "dss_clkdm",
2025 .recalc = &followparent_recalc,
2026 };
2027
2028 static struct clk dss2_alwon_fck = {
2029 .name = "dss2_alwon_fck",
2030 .ops = &clkops_omap2_dflt,
2031 .parent = &sys_ck,
2032 .init = &omap2_init_clk_clkdm,
2033 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2034 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2035 .clkdm_name = "dss_clkdm",
2036 .recalc = &followparent_recalc,
2037 };
2038
2039 static struct clk dss_ick = {
2040 /* Handles both L3 and L4 clocks */
2041 .name = "dss_ick",
2042 .ops = &clkops_omap2_dflt,
2043 .parent = &l4_ick,
2044 .init = &omap2_init_clk_clkdm,
2045 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2046 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2047 .clkdm_name = "dss_clkdm",
2048 .recalc = &followparent_recalc,
2049 };
2050
2051 /* CAM */
2052
2053 static struct clk cam_mclk = {
2054 .name = "cam_mclk",
2055 .ops = &clkops_omap2_dflt,
2056 .parent = &dpll4_m5x2_ck,
2057 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2058 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2059 .clkdm_name = "cam_clkdm",
2060 .recalc = &followparent_recalc,
2061 };
2062
2063 static struct clk cam_ick = {
2064 /* Handles both L3 and L4 clocks */
2065 .name = "cam_ick",
2066 .ops = &clkops_omap2_dflt,
2067 .parent = &l4_ick,
2068 .init = &omap2_init_clk_clkdm,
2069 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2070 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2071 .clkdm_name = "cam_clkdm",
2072 .recalc = &followparent_recalc,
2073 };
2074
2075 static struct clk csi2_96m_fck = {
2076 .name = "csi2_96m_fck",
2077 .ops = &clkops_omap2_dflt,
2078 .parent = &core_96m_fck,
2079 .init = &omap2_init_clk_clkdm,
2080 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2081 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
2082 .clkdm_name = "cam_clkdm",
2083 .recalc = &followparent_recalc,
2084 };
2085
2086 /* USBHOST - 3430ES2 only */
2087
2088 static struct clk usbhost_120m_fck = {
2089 .name = "usbhost_120m_fck",
2090 .ops = &clkops_omap2_dflt_wait,
2091 .parent = &dpll5_m2_ck,
2092 .init = &omap2_init_clk_clkdm,
2093 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2094 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2095 .clkdm_name = "usbhost_clkdm",
2096 .recalc = &followparent_recalc,
2097 };
2098
2099 static struct clk usbhost_48m_fck = {
2100 .name = "usbhost_48m_fck",
2101 .ops = &clkops_omap2_dflt_wait,
2102 .parent = &omap_48m_fck,
2103 .init = &omap2_init_clk_clkdm,
2104 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2105 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2106 .clkdm_name = "usbhost_clkdm",
2107 .recalc = &followparent_recalc,
2108 };
2109
2110 static struct clk usbhost_ick = {
2111 /* Handles both L3 and L4 clocks */
2112 .name = "usbhost_ick",
2113 .ops = &clkops_omap2_dflt_wait,
2114 .parent = &l4_ick,
2115 .init = &omap2_init_clk_clkdm,
2116 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2117 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2118 .clkdm_name = "usbhost_clkdm",
2119 .recalc = &followparent_recalc,
2120 };
2121
2122 /* WKUP */
2123
2124 static const struct clksel_rate usim_96m_rates[] = {
2125 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2126 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2127 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2128 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2129 { .div = 0 },
2130 };
2131
2132 static const struct clksel_rate usim_120m_rates[] = {
2133 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2134 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2135 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2136 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2137 { .div = 0 },
2138 };
2139
2140 static const struct clksel usim_clksel[] = {
2141 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2142 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
2143 { .parent = &sys_ck, .rates = div2_rates },
2144 { .parent = NULL },
2145 };
2146
2147 /* 3430ES2 only */
2148 static struct clk usim_fck = {
2149 .name = "usim_fck",
2150 .ops = &clkops_omap2_dflt_wait,
2151 .init = &omap2_init_clksel_parent,
2152 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2153 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2154 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2155 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2156 .clksel = usim_clksel,
2157 .recalc = &omap2_clksel_recalc,
2158 };
2159
2160 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2161 static struct clk gpt1_fck = {
2162 .name = "gpt1_fck",
2163 .ops = &clkops_omap2_dflt_wait,
2164 .init = &omap2_init_clksel_parent,
2165 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2166 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2167 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2168 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2169 .clksel = omap343x_gpt_clksel,
2170 .clkdm_name = "wkup_clkdm",
2171 .recalc = &omap2_clksel_recalc,
2172 };
2173
2174 static struct clk wkup_32k_fck = {
2175 .name = "wkup_32k_fck",
2176 .ops = &clkops_null,
2177 .init = &omap2_init_clk_clkdm,
2178 .parent = &omap_32k_fck,
2179 .clkdm_name = "wkup_clkdm",
2180 .recalc = &followparent_recalc,
2181 };
2182
2183 static struct clk gpio1_dbck = {
2184 .name = "gpio1_dbck",
2185 .ops = &clkops_omap2_dflt_wait,
2186 .parent = &wkup_32k_fck,
2187 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2188 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2189 .clkdm_name = "wkup_clkdm",
2190 .recalc = &followparent_recalc,
2191 };
2192
2193 static struct clk wdt2_fck = {
2194 .name = "wdt2_fck",
2195 .ops = &clkops_omap2_dflt_wait,
2196 .parent = &wkup_32k_fck,
2197 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2198 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2199 .clkdm_name = "wkup_clkdm",
2200 .recalc = &followparent_recalc,
2201 };
2202
2203 static struct clk wkup_l4_ick = {
2204 .name = "wkup_l4_ick",
2205 .ops = &clkops_null,
2206 .parent = &sys_ck,
2207 .clkdm_name = "wkup_clkdm",
2208 .recalc = &followparent_recalc,
2209 };
2210
2211 /* 3430ES2 only */
2212 /* Never specifically named in the TRM, so we have to infer a likely name */
2213 static struct clk usim_ick = {
2214 .name = "usim_ick",
2215 .ops = &clkops_omap2_dflt_wait,
2216 .parent = &wkup_l4_ick,
2217 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2218 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2219 .clkdm_name = "wkup_clkdm",
2220 .recalc = &followparent_recalc,
2221 };
2222
2223 static struct clk wdt2_ick = {
2224 .name = "wdt2_ick",
2225 .ops = &clkops_omap2_dflt_wait,
2226 .parent = &wkup_l4_ick,
2227 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2228 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2229 .clkdm_name = "wkup_clkdm",
2230 .recalc = &followparent_recalc,
2231 };
2232
2233 static struct clk wdt1_ick = {
2234 .name = "wdt1_ick",
2235 .ops = &clkops_omap2_dflt_wait,
2236 .parent = &wkup_l4_ick,
2237 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2238 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2239 .clkdm_name = "wkup_clkdm",
2240 .recalc = &followparent_recalc,
2241 };
2242
2243 static struct clk gpio1_ick = {
2244 .name = "gpio1_ick",
2245 .ops = &clkops_omap2_dflt_wait,
2246 .parent = &wkup_l4_ick,
2247 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2248 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2249 .clkdm_name = "wkup_clkdm",
2250 .recalc = &followparent_recalc,
2251 };
2252
2253 static struct clk omap_32ksync_ick = {
2254 .name = "omap_32ksync_ick",
2255 .ops = &clkops_omap2_dflt_wait,
2256 .parent = &wkup_l4_ick,
2257 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2258 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2259 .clkdm_name = "wkup_clkdm",
2260 .recalc = &followparent_recalc,
2261 };
2262
2263 /* XXX This clock no longer exists in 3430 TRM rev F */
2264 static struct clk gpt12_ick = {
2265 .name = "gpt12_ick",
2266 .ops = &clkops_omap2_dflt_wait,
2267 .parent = &wkup_l4_ick,
2268 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2269 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2270 .clkdm_name = "wkup_clkdm",
2271 .recalc = &followparent_recalc,
2272 };
2273
2274 static struct clk gpt1_ick = {
2275 .name = "gpt1_ick",
2276 .ops = &clkops_omap2_dflt_wait,
2277 .parent = &wkup_l4_ick,
2278 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2279 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2280 .clkdm_name = "wkup_clkdm",
2281 .recalc = &followparent_recalc,
2282 };
2283
2284
2285
2286 /* PER clock domain */
2287
2288 static struct clk per_96m_fck = {
2289 .name = "per_96m_fck",
2290 .ops = &clkops_null,
2291 .parent = &omap_96m_alwon_fck,
2292 .init = &omap2_init_clk_clkdm,
2293 .clkdm_name = "per_clkdm",
2294 .recalc = &followparent_recalc,
2295 };
2296
2297 static struct clk per_48m_fck = {
2298 .name = "per_48m_fck",
2299 .ops = &clkops_null,
2300 .parent = &omap_48m_fck,
2301 .init = &omap2_init_clk_clkdm,
2302 .clkdm_name = "per_clkdm",
2303 .recalc = &followparent_recalc,
2304 };
2305
2306 static struct clk uart3_fck = {
2307 .name = "uart3_fck",
2308 .ops = &clkops_omap2_dflt_wait,
2309 .parent = &per_48m_fck,
2310 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2311 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2312 .clkdm_name = "per_clkdm",
2313 .recalc = &followparent_recalc,
2314 };
2315
2316 static struct clk gpt2_fck = {
2317 .name = "gpt2_fck",
2318 .ops = &clkops_omap2_dflt_wait,
2319 .init = &omap2_init_clksel_parent,
2320 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2321 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2322 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2323 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2324 .clksel = omap343x_gpt_clksel,
2325 .clkdm_name = "per_clkdm",
2326 .recalc = &omap2_clksel_recalc,
2327 };
2328
2329 static struct clk gpt3_fck = {
2330 .name = "gpt3_fck",
2331 .ops = &clkops_omap2_dflt_wait,
2332 .init = &omap2_init_clksel_parent,
2333 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2334 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2335 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2336 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2337 .clksel = omap343x_gpt_clksel,
2338 .clkdm_name = "per_clkdm",
2339 .recalc = &omap2_clksel_recalc,
2340 };
2341
2342 static struct clk gpt4_fck = {
2343 .name = "gpt4_fck",
2344 .ops = &clkops_omap2_dflt_wait,
2345 .init = &omap2_init_clksel_parent,
2346 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2347 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2348 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2349 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2350 .clksel = omap343x_gpt_clksel,
2351 .clkdm_name = "per_clkdm",
2352 .recalc = &omap2_clksel_recalc,
2353 };
2354
2355 static struct clk gpt5_fck = {
2356 .name = "gpt5_fck",
2357 .ops = &clkops_omap2_dflt_wait,
2358 .init = &omap2_init_clksel_parent,
2359 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2360 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2361 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2362 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2363 .clksel = omap343x_gpt_clksel,
2364 .clkdm_name = "per_clkdm",
2365 .recalc = &omap2_clksel_recalc,
2366 };
2367
2368 static struct clk gpt6_fck = {
2369 .name = "gpt6_fck",
2370 .ops = &clkops_omap2_dflt_wait,
2371 .init = &omap2_init_clksel_parent,
2372 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2373 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2374 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2375 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2376 .clksel = omap343x_gpt_clksel,
2377 .clkdm_name = "per_clkdm",
2378 .recalc = &omap2_clksel_recalc,
2379 };
2380
2381 static struct clk gpt7_fck = {
2382 .name = "gpt7_fck",
2383 .ops = &clkops_omap2_dflt_wait,
2384 .init = &omap2_init_clksel_parent,
2385 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2386 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2387 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2388 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2389 .clksel = omap343x_gpt_clksel,
2390 .clkdm_name = "per_clkdm",
2391 .recalc = &omap2_clksel_recalc,
2392 };
2393
2394 static struct clk gpt8_fck = {
2395 .name = "gpt8_fck",
2396 .ops = &clkops_omap2_dflt_wait,
2397 .init = &omap2_init_clksel_parent,
2398 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2399 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2400 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2401 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2402 .clksel = omap343x_gpt_clksel,
2403 .clkdm_name = "per_clkdm",
2404 .recalc = &omap2_clksel_recalc,
2405 };
2406
2407 static struct clk gpt9_fck = {
2408 .name = "gpt9_fck",
2409 .ops = &clkops_omap2_dflt_wait,
2410 .init = &omap2_init_clksel_parent,
2411 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2412 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2413 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2414 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2415 .clksel = omap343x_gpt_clksel,
2416 .clkdm_name = "per_clkdm",
2417 .recalc = &omap2_clksel_recalc,
2418 };
2419
2420 static struct clk per_32k_alwon_fck = {
2421 .name = "per_32k_alwon_fck",
2422 .ops = &clkops_null,
2423 .parent = &omap_32k_fck,
2424 .clkdm_name = "per_clkdm",
2425 .recalc = &followparent_recalc,
2426 };
2427
2428 static struct clk gpio6_dbck = {
2429 .name = "gpio6_dbck",
2430 .ops = &clkops_omap2_dflt_wait,
2431 .parent = &per_32k_alwon_fck,
2432 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2433 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2434 .clkdm_name = "per_clkdm",
2435 .recalc = &followparent_recalc,
2436 };
2437
2438 static struct clk gpio5_dbck = {
2439 .name = "gpio5_dbck",
2440 .ops = &clkops_omap2_dflt_wait,
2441 .parent = &per_32k_alwon_fck,
2442 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2443 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2444 .clkdm_name = "per_clkdm",
2445 .recalc = &followparent_recalc,
2446 };
2447
2448 static struct clk gpio4_dbck = {
2449 .name = "gpio4_dbck",
2450 .ops = &clkops_omap2_dflt_wait,
2451 .parent = &per_32k_alwon_fck,
2452 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2453 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2454 .clkdm_name = "per_clkdm",
2455 .recalc = &followparent_recalc,
2456 };
2457
2458 static struct clk gpio3_dbck = {
2459 .name = "gpio3_dbck",
2460 .ops = &clkops_omap2_dflt_wait,
2461 .parent = &per_32k_alwon_fck,
2462 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2463 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2464 .clkdm_name = "per_clkdm",
2465 .recalc = &followparent_recalc,
2466 };
2467
2468 static struct clk gpio2_dbck = {
2469 .name = "gpio2_dbck",
2470 .ops = &clkops_omap2_dflt_wait,
2471 .parent = &per_32k_alwon_fck,
2472 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2473 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2474 .clkdm_name = "per_clkdm",
2475 .recalc = &followparent_recalc,
2476 };
2477
2478 static struct clk wdt3_fck = {
2479 .name = "wdt3_fck",
2480 .ops = &clkops_omap2_dflt_wait,
2481 .parent = &per_32k_alwon_fck,
2482 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2483 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2484 .clkdm_name = "per_clkdm",
2485 .recalc = &followparent_recalc,
2486 };
2487
2488 static struct clk per_l4_ick = {
2489 .name = "per_l4_ick",
2490 .ops = &clkops_null,
2491 .parent = &l4_ick,
2492 .clkdm_name = "per_clkdm",
2493 .recalc = &followparent_recalc,
2494 };
2495
2496 static struct clk gpio6_ick = {
2497 .name = "gpio6_ick",
2498 .ops = &clkops_omap2_dflt_wait,
2499 .parent = &per_l4_ick,
2500 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2501 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2502 .clkdm_name = "per_clkdm",
2503 .recalc = &followparent_recalc,
2504 };
2505
2506 static struct clk gpio5_ick = {
2507 .name = "gpio5_ick",
2508 .ops = &clkops_omap2_dflt_wait,
2509 .parent = &per_l4_ick,
2510 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2511 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2512 .clkdm_name = "per_clkdm",
2513 .recalc = &followparent_recalc,
2514 };
2515
2516 static struct clk gpio4_ick = {
2517 .name = "gpio4_ick",
2518 .ops = &clkops_omap2_dflt_wait,
2519 .parent = &per_l4_ick,
2520 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2521 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2522 .clkdm_name = "per_clkdm",
2523 .recalc = &followparent_recalc,
2524 };
2525
2526 static struct clk gpio3_ick = {
2527 .name = "gpio3_ick",
2528 .ops = &clkops_omap2_dflt_wait,
2529 .parent = &per_l4_ick,
2530 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2531 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2532 .clkdm_name = "per_clkdm",
2533 .recalc = &followparent_recalc,
2534 };
2535
2536 static struct clk gpio2_ick = {
2537 .name = "gpio2_ick",
2538 .ops = &clkops_omap2_dflt_wait,
2539 .parent = &per_l4_ick,
2540 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2541 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2542 .clkdm_name = "per_clkdm",
2543 .recalc = &followparent_recalc,
2544 };
2545
2546 static struct clk wdt3_ick = {
2547 .name = "wdt3_ick",
2548 .ops = &clkops_omap2_dflt_wait,
2549 .parent = &per_l4_ick,
2550 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2551 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2552 .clkdm_name = "per_clkdm",
2553 .recalc = &followparent_recalc,
2554 };
2555
2556 static struct clk uart3_ick = {
2557 .name = "uart3_ick",
2558 .ops = &clkops_omap2_dflt_wait,
2559 .parent = &per_l4_ick,
2560 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2561 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2562 .clkdm_name = "per_clkdm",
2563 .recalc = &followparent_recalc,
2564 };
2565
2566 static struct clk gpt9_ick = {
2567 .name = "gpt9_ick",
2568 .ops = &clkops_omap2_dflt_wait,
2569 .parent = &per_l4_ick,
2570 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2571 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2572 .clkdm_name = "per_clkdm",
2573 .recalc = &followparent_recalc,
2574 };
2575
2576 static struct clk gpt8_ick = {
2577 .name = "gpt8_ick",
2578 .ops = &clkops_omap2_dflt_wait,
2579 .parent = &per_l4_ick,
2580 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2581 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2582 .clkdm_name = "per_clkdm",
2583 .recalc = &followparent_recalc,
2584 };
2585
2586 static struct clk gpt7_ick = {
2587 .name = "gpt7_ick",
2588 .ops = &clkops_omap2_dflt_wait,
2589 .parent = &per_l4_ick,
2590 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2591 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2592 .clkdm_name = "per_clkdm",
2593 .recalc = &followparent_recalc,
2594 };
2595
2596 static struct clk gpt6_ick = {
2597 .name = "gpt6_ick",
2598 .ops = &clkops_omap2_dflt_wait,
2599 .parent = &per_l4_ick,
2600 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2601 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2602 .clkdm_name = "per_clkdm",
2603 .recalc = &followparent_recalc,
2604 };
2605
2606 static struct clk gpt5_ick = {
2607 .name = "gpt5_ick",
2608 .ops = &clkops_omap2_dflt_wait,
2609 .parent = &per_l4_ick,
2610 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2611 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2612 .clkdm_name = "per_clkdm",
2613 .recalc = &followparent_recalc,
2614 };
2615
2616 static struct clk gpt4_ick = {
2617 .name = "gpt4_ick",
2618 .ops = &clkops_omap2_dflt_wait,
2619 .parent = &per_l4_ick,
2620 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2621 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2622 .clkdm_name = "per_clkdm",
2623 .recalc = &followparent_recalc,
2624 };
2625
2626 static struct clk gpt3_ick = {
2627 .name = "gpt3_ick",
2628 .ops = &clkops_omap2_dflt_wait,
2629 .parent = &per_l4_ick,
2630 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2631 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2632 .clkdm_name = "per_clkdm",
2633 .recalc = &followparent_recalc,
2634 };
2635
2636 static struct clk gpt2_ick = {
2637 .name = "gpt2_ick",
2638 .ops = &clkops_omap2_dflt_wait,
2639 .parent = &per_l4_ick,
2640 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2641 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2642 .clkdm_name = "per_clkdm",
2643 .recalc = &followparent_recalc,
2644 };
2645
2646 static struct clk mcbsp2_ick = {
2647 .name = "mcbsp_ick",
2648 .ops = &clkops_omap2_dflt_wait,
2649 .id = 2,
2650 .parent = &per_l4_ick,
2651 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2652 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2653 .clkdm_name = "per_clkdm",
2654 .recalc = &followparent_recalc,
2655 };
2656
2657 static struct clk mcbsp3_ick = {
2658 .name = "mcbsp_ick",
2659 .ops = &clkops_omap2_dflt_wait,
2660 .id = 3,
2661 .parent = &per_l4_ick,
2662 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2663 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2664 .clkdm_name = "per_clkdm",
2665 .recalc = &followparent_recalc,
2666 };
2667
2668 static struct clk mcbsp4_ick = {
2669 .name = "mcbsp_ick",
2670 .ops = &clkops_omap2_dflt_wait,
2671 .id = 4,
2672 .parent = &per_l4_ick,
2673 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2674 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2675 .clkdm_name = "per_clkdm",
2676 .recalc = &followparent_recalc,
2677 };
2678
2679 static const struct clksel mcbsp_234_clksel[] = {
2680 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2681 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2682 { .parent = NULL }
2683 };
2684
2685 static struct clk mcbsp2_fck = {
2686 .name = "mcbsp_fck",
2687 .ops = &clkops_omap2_dflt_wait,
2688 .id = 2,
2689 .init = &omap2_init_clksel_parent,
2690 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2691 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2692 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2693 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2694 .clksel = mcbsp_234_clksel,
2695 .clkdm_name = "per_clkdm",
2696 .recalc = &omap2_clksel_recalc,
2697 };
2698
2699 static struct clk mcbsp3_fck = {
2700 .name = "mcbsp_fck",
2701 .ops = &clkops_omap2_dflt_wait,
2702 .id = 3,
2703 .init = &omap2_init_clksel_parent,
2704 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2705 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2706 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2707 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2708 .clksel = mcbsp_234_clksel,
2709 .clkdm_name = "per_clkdm",
2710 .recalc = &omap2_clksel_recalc,
2711 };
2712
2713 static struct clk mcbsp4_fck = {
2714 .name = "mcbsp_fck",
2715 .ops = &clkops_omap2_dflt_wait,
2716 .id = 4,
2717 .init = &omap2_init_clksel_parent,
2718 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2719 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2720 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2721 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2722 .clksel = mcbsp_234_clksel,
2723 .clkdm_name = "per_clkdm",
2724 .recalc = &omap2_clksel_recalc,
2725 };
2726
2727 /* EMU clocks */
2728
2729 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2730
2731 static const struct clksel_rate emu_src_sys_rates[] = {
2732 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2733 { .div = 0 },
2734 };
2735
2736 static const struct clksel_rate emu_src_core_rates[] = {
2737 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2738 { .div = 0 },
2739 };
2740
2741 static const struct clksel_rate emu_src_per_rates[] = {
2742 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2743 { .div = 0 },
2744 };
2745
2746 static const struct clksel_rate emu_src_mpu_rates[] = {
2747 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2748 { .div = 0 },
2749 };
2750
2751 static const struct clksel emu_src_clksel[] = {
2752 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2753 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2754 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2755 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2756 { .parent = NULL },
2757 };
2758
2759 /*
2760 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2761 * to switch the source of some of the EMU clocks.
2762 * XXX Are there CLKEN bits for these EMU clks?
2763 */
2764 static struct clk emu_src_ck = {
2765 .name = "emu_src_ck",
2766 .ops = &clkops_null,
2767 .init = &omap2_init_clksel_parent,
2768 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2769 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2770 .clksel = emu_src_clksel,
2771 .clkdm_name = "emu_clkdm",
2772 .recalc = &omap2_clksel_recalc,
2773 };
2774
2775 static const struct clksel_rate pclk_emu_rates[] = {
2776 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2777 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2778 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2779 { .div = 6, .val = 6, .flags = RATE_IN_343X },
2780 { .div = 0 },
2781 };
2782
2783 static const struct clksel pclk_emu_clksel[] = {
2784 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2785 { .parent = NULL },
2786 };
2787
2788 static struct clk pclk_fck = {
2789 .name = "pclk_fck",
2790 .ops = &clkops_null,
2791 .init = &omap2_init_clksel_parent,
2792 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2793 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2794 .clksel = pclk_emu_clksel,
2795 .clkdm_name = "emu_clkdm",
2796 .recalc = &omap2_clksel_recalc,
2797 };
2798
2799 static const struct clksel_rate pclkx2_emu_rates[] = {
2800 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2801 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2802 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2803 { .div = 0 },
2804 };
2805
2806 static const struct clksel pclkx2_emu_clksel[] = {
2807 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2808 { .parent = NULL },
2809 };
2810
2811 static struct clk pclkx2_fck = {
2812 .name = "pclkx2_fck",
2813 .ops = &clkops_null,
2814 .init = &omap2_init_clksel_parent,
2815 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2816 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2817 .clksel = pclkx2_emu_clksel,
2818 .clkdm_name = "emu_clkdm",
2819 .recalc = &omap2_clksel_recalc,
2820 };
2821
2822 static const struct clksel atclk_emu_clksel[] = {
2823 { .parent = &emu_src_ck, .rates = div2_rates },
2824 { .parent = NULL },
2825 };
2826
2827 static struct clk atclk_fck = {
2828 .name = "atclk_fck",
2829 .ops = &clkops_null,
2830 .init = &omap2_init_clksel_parent,
2831 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2832 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2833 .clksel = atclk_emu_clksel,
2834 .clkdm_name = "emu_clkdm",
2835 .recalc = &omap2_clksel_recalc,
2836 };
2837
2838 static struct clk traceclk_src_fck = {
2839 .name = "traceclk_src_fck",
2840 .ops = &clkops_null,
2841 .init = &omap2_init_clksel_parent,
2842 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2843 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2844 .clksel = emu_src_clksel,
2845 .clkdm_name = "emu_clkdm",
2846 .recalc = &omap2_clksel_recalc,
2847 };
2848
2849 static const struct clksel_rate traceclk_rates[] = {
2850 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2851 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2852 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2853 { .div = 0 },
2854 };
2855
2856 static const struct clksel traceclk_clksel[] = {
2857 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2858 { .parent = NULL },
2859 };
2860
2861 static struct clk traceclk_fck = {
2862 .name = "traceclk_fck",
2863 .ops = &clkops_null,
2864 .init = &omap2_init_clksel_parent,
2865 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2866 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2867 .clksel = traceclk_clksel,
2868 .clkdm_name = "emu_clkdm",
2869 .recalc = &omap2_clksel_recalc,
2870 };
2871
2872 /* SR clocks */
2873
2874 /* SmartReflex fclk (VDD1) */
2875 static struct clk sr1_fck = {
2876 .name = "sr1_fck",
2877 .ops = &clkops_omap2_dflt_wait,
2878 .parent = &sys_ck,
2879 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2880 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2881 .recalc = &followparent_recalc,
2882 };
2883
2884 /* SmartReflex fclk (VDD2) */
2885 static struct clk sr2_fck = {
2886 .name = "sr2_fck",
2887 .ops = &clkops_omap2_dflt_wait,
2888 .parent = &sys_ck,
2889 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2890 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2891 .recalc = &followparent_recalc,
2892 };
2893
2894 static struct clk sr_l4_ick = {
2895 .name = "sr_l4_ick",
2896 .ops = &clkops_null, /* RMK: missing? */
2897 .parent = &l4_ick,
2898 .clkdm_name = "core_l4_clkdm",
2899 .recalc = &followparent_recalc,
2900 };
2901
2902 /* SECURE_32K_FCK clocks */
2903
2904 static struct clk gpt12_fck = {
2905 .name = "gpt12_fck",
2906 .ops = &clkops_null,
2907 .parent = &secure_32k_fck,
2908 .recalc = &followparent_recalc,
2909 };
2910
2911 static struct clk wdt1_fck = {
2912 .name = "wdt1_fck",
2913 .ops = &clkops_null,
2914 .parent = &secure_32k_fck,
2915 .recalc = &followparent_recalc,
2916 };
2917
2918 #endif
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