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ARM: OMAP2+: Fix broken gpmc support
[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-omap2 / gpmc.c
1 /*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15 #undef DEBUG
16
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/ioport.h>
23 #include <linux/spinlock.h>
24 #include <linux/io.h>
25 #include <linux/module.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/of.h>
29 #include <linux/of_mtd.h>
30 #include <linux/of_device.h>
31 #include <linux/mtd/nand.h>
32
33 #include <linux/platform_data/mtd-nand-omap2.h>
34
35 #include <asm/mach-types.h>
36
37 #include "soc.h"
38 #include "common.h"
39 #include "omap_device.h"
40 #include "gpmc.h"
41 #include "gpmc-nand.h"
42 #include "gpmc-onenand.h"
43
44 #define DEVICE_NAME "omap-gpmc"
45
46 /* GPMC register offsets */
47 #define GPMC_REVISION 0x00
48 #define GPMC_SYSCONFIG 0x10
49 #define GPMC_SYSSTATUS 0x14
50 #define GPMC_IRQSTATUS 0x18
51 #define GPMC_IRQENABLE 0x1c
52 #define GPMC_TIMEOUT_CONTROL 0x40
53 #define GPMC_ERR_ADDRESS 0x44
54 #define GPMC_ERR_TYPE 0x48
55 #define GPMC_CONFIG 0x50
56 #define GPMC_STATUS 0x54
57 #define GPMC_PREFETCH_CONFIG1 0x1e0
58 #define GPMC_PREFETCH_CONFIG2 0x1e4
59 #define GPMC_PREFETCH_CONTROL 0x1ec
60 #define GPMC_PREFETCH_STATUS 0x1f0
61 #define GPMC_ECC_CONFIG 0x1f4
62 #define GPMC_ECC_CONTROL 0x1f8
63 #define GPMC_ECC_SIZE_CONFIG 0x1fc
64 #define GPMC_ECC1_RESULT 0x200
65 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
66 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
67 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
68 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
69
70 /* GPMC ECC control settings */
71 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
72 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
73 #define GPMC_ECC_CTRL_ECCREG1 0x001
74 #define GPMC_ECC_CTRL_ECCREG2 0x002
75 #define GPMC_ECC_CTRL_ECCREG3 0x003
76 #define GPMC_ECC_CTRL_ECCREG4 0x004
77 #define GPMC_ECC_CTRL_ECCREG5 0x005
78 #define GPMC_ECC_CTRL_ECCREG6 0x006
79 #define GPMC_ECC_CTRL_ECCREG7 0x007
80 #define GPMC_ECC_CTRL_ECCREG8 0x008
81 #define GPMC_ECC_CTRL_ECCREG9 0x009
82
83 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
84 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
85 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
86 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
87 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
88 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
89
90 #define GPMC_CS0_OFFSET 0x60
91 #define GPMC_CS_SIZE 0x30
92 #define GPMC_BCH_SIZE 0x10
93
94 #define GPMC_MEM_START 0x00000000
95 #define GPMC_MEM_END 0x3FFFFFFF
96 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
97
98 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
99 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
100
101 #define CS_NUM_SHIFT 24
102 #define ENABLE_PREFETCH (0x1 << 7)
103 #define DMA_MPU_MODE 2
104
105 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
106 #define GPMC_REVISION_MINOR(l) (l & 0xf)
107
108 #define GPMC_HAS_WR_ACCESS 0x1
109 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
110
111 /* XXX: Only NAND irq has been considered,currently these are the only ones used
112 */
113 #define GPMC_NR_IRQ 2
114
115 struct gpmc_client_irq {
116 unsigned irq;
117 u32 bitmask;
118 };
119
120 /* Structure to save gpmc cs context */
121 struct gpmc_cs_config {
122 u32 config1;
123 u32 config2;
124 u32 config3;
125 u32 config4;
126 u32 config5;
127 u32 config6;
128 u32 config7;
129 int is_valid;
130 };
131
132 /*
133 * Structure to save/restore gpmc context
134 * to support core off on OMAP3
135 */
136 struct omap3_gpmc_regs {
137 u32 sysconfig;
138 u32 irqenable;
139 u32 timeout_ctrl;
140 u32 config;
141 u32 prefetch_config1;
142 u32 prefetch_config2;
143 u32 prefetch_control;
144 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
145 };
146
147 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
148 static struct irq_chip gpmc_irq_chip;
149 static unsigned gpmc_irq_start;
150
151 static struct resource gpmc_mem_root;
152 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
153 static DEFINE_SPINLOCK(gpmc_mem_lock);
154 /* Define chip-selects as reserved by default until probe completes */
155 static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
156 static struct device *gpmc_dev;
157 static int gpmc_irq;
158 static resource_size_t phys_base, mem_size;
159 static unsigned gpmc_capability;
160 static void __iomem *gpmc_base;
161
162 static struct clk *gpmc_l3_clk;
163
164 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
165
166 static void gpmc_write_reg(int idx, u32 val)
167 {
168 __raw_writel(val, gpmc_base + idx);
169 }
170
171 static u32 gpmc_read_reg(int idx)
172 {
173 return __raw_readl(gpmc_base + idx);
174 }
175
176 void gpmc_cs_write_reg(int cs, int idx, u32 val)
177 {
178 void __iomem *reg_addr;
179
180 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
181 __raw_writel(val, reg_addr);
182 }
183
184 u32 gpmc_cs_read_reg(int cs, int idx)
185 {
186 void __iomem *reg_addr;
187
188 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
189 return __raw_readl(reg_addr);
190 }
191
192 /* TODO: Add support for gpmc_fck to clock framework and use it */
193 unsigned long gpmc_get_fclk_period(void)
194 {
195 unsigned long rate = clk_get_rate(gpmc_l3_clk);
196
197 if (rate == 0) {
198 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
199 return 0;
200 }
201
202 rate /= 1000;
203 rate = 1000000000 / rate; /* In picoseconds */
204
205 return rate;
206 }
207
208 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
209 {
210 unsigned long tick_ps;
211
212 /* Calculate in picosecs to yield more exact results */
213 tick_ps = gpmc_get_fclk_period();
214
215 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
216 }
217
218 unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
219 {
220 unsigned long tick_ps;
221
222 /* Calculate in picosecs to yield more exact results */
223 tick_ps = gpmc_get_fclk_period();
224
225 return (time_ps + tick_ps - 1) / tick_ps;
226 }
227
228 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
229 {
230 return ticks * gpmc_get_fclk_period() / 1000;
231 }
232
233 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
234 {
235 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
236
237 return ticks * gpmc_get_fclk_period() / 1000;
238 }
239
240 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
241 {
242 return ticks * gpmc_get_fclk_period();
243 }
244
245 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
246 {
247 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
248
249 return ticks * gpmc_get_fclk_period();
250 }
251
252 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
253 {
254 u32 l;
255
256 l = gpmc_cs_read_reg(cs, reg);
257 if (value)
258 l |= mask;
259 else
260 l &= ~mask;
261 gpmc_cs_write_reg(cs, reg, l);
262 }
263
264 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
265 {
266 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
267 GPMC_CONFIG1_TIME_PARA_GRAN,
268 p->time_para_granularity);
269 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
270 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
271 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
272 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
273 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
274 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
275 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
276 GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
277 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
278 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
279 p->cycle2cyclesamecsen);
280 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
281 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
282 p->cycle2cyclediffcsen);
283 }
284
285 #ifdef DEBUG
286 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
287 int time, const char *name)
288 #else
289 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
290 int time)
291 #endif
292 {
293 u32 l;
294 int ticks, mask, nr_bits;
295
296 if (time == 0)
297 ticks = 0;
298 else
299 ticks = gpmc_ns_to_ticks(time);
300 nr_bits = end_bit - st_bit + 1;
301 if (ticks >= 1 << nr_bits) {
302 #ifdef DEBUG
303 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
304 cs, name, time, ticks, 1 << nr_bits);
305 #endif
306 return -1;
307 }
308
309 mask = (1 << nr_bits) - 1;
310 l = gpmc_cs_read_reg(cs, reg);
311 #ifdef DEBUG
312 printk(KERN_INFO
313 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
314 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
315 (l >> st_bit) & mask, time);
316 #endif
317 l &= ~(mask << st_bit);
318 l |= ticks << st_bit;
319 gpmc_cs_write_reg(cs, reg, l);
320
321 return 0;
322 }
323
324 #ifdef DEBUG
325 #define GPMC_SET_ONE(reg, st, end, field) \
326 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
327 t->field, #field) < 0) \
328 return -1
329 #else
330 #define GPMC_SET_ONE(reg, st, end, field) \
331 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
332 return -1
333 #endif
334
335 int gpmc_calc_divider(unsigned int sync_clk)
336 {
337 int div;
338 u32 l;
339
340 l = sync_clk + (gpmc_get_fclk_period() - 1);
341 div = l / gpmc_get_fclk_period();
342 if (div > 4)
343 return -1;
344 if (div <= 0)
345 div = 1;
346
347 return div;
348 }
349
350 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
351 {
352 int div;
353 u32 l;
354
355 div = gpmc_calc_divider(t->sync_clk);
356 if (div < 0)
357 return div;
358
359 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
360 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
361 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
362
363 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
364 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
365 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
366
367 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
368 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
369 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
370 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
371
372 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
373 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
374 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
375
376 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
377
378 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
379 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
380
381 GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
382 GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
383
384 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
385 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
386 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
387 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
388
389 /* caller is expected to have initialized CONFIG1 to cover
390 * at least sync vs async
391 */
392 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
393 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
394 #ifdef DEBUG
395 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
396 cs, (div * gpmc_get_fclk_period()) / 1000, div);
397 #endif
398 l &= ~0x03;
399 l |= (div - 1);
400 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
401 }
402
403 gpmc_cs_bool_timings(cs, &t->bool_timings);
404
405 return 0;
406 }
407
408 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
409 {
410 u32 l;
411 u32 mask;
412
413 mask = (1 << GPMC_SECTION_SHIFT) - size;
414 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
415 l &= ~0x3f;
416 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
417 l &= ~(0x0f << 8);
418 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
419 l |= GPMC_CONFIG7_CSVALID;
420 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
421 }
422
423 static void gpmc_cs_disable_mem(int cs)
424 {
425 u32 l;
426
427 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
428 l &= ~GPMC_CONFIG7_CSVALID;
429 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
430 }
431
432 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
433 {
434 u32 l;
435 u32 mask;
436
437 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
438 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
439 mask = (l >> 8) & 0x0f;
440 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
441 }
442
443 static int gpmc_cs_mem_enabled(int cs)
444 {
445 u32 l;
446
447 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
448 return l & GPMC_CONFIG7_CSVALID;
449 }
450
451 int gpmc_cs_set_reserved(int cs, int reserved)
452 {
453 if (cs > GPMC_CS_NUM)
454 return -ENODEV;
455
456 gpmc_cs_map &= ~(1 << cs);
457 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
458
459 return 0;
460 }
461
462 int gpmc_cs_reserved(int cs)
463 {
464 if (cs > GPMC_CS_NUM)
465 return -ENODEV;
466
467 return gpmc_cs_map & (1 << cs);
468 }
469
470 static unsigned long gpmc_mem_align(unsigned long size)
471 {
472 int order;
473
474 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
475 order = GPMC_CHUNK_SHIFT - 1;
476 do {
477 size >>= 1;
478 order++;
479 } while (size);
480 size = 1 << order;
481 return size;
482 }
483
484 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
485 {
486 struct resource *res = &gpmc_cs_mem[cs];
487 int r;
488
489 size = gpmc_mem_align(size);
490 spin_lock(&gpmc_mem_lock);
491 res->start = base;
492 res->end = base + size - 1;
493 r = request_resource(&gpmc_mem_root, res);
494 spin_unlock(&gpmc_mem_lock);
495
496 return r;
497 }
498
499 static int gpmc_cs_delete_mem(int cs)
500 {
501 struct resource *res = &gpmc_cs_mem[cs];
502 int r;
503
504 spin_lock(&gpmc_mem_lock);
505 r = release_resource(&gpmc_cs_mem[cs]);
506 res->start = 0;
507 res->end = 0;
508 spin_unlock(&gpmc_mem_lock);
509
510 return r;
511 }
512
513 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
514 {
515 struct resource *res = &gpmc_cs_mem[cs];
516 int r = -1;
517
518 if (cs > GPMC_CS_NUM)
519 return -ENODEV;
520
521 size = gpmc_mem_align(size);
522 if (size > (1 << GPMC_SECTION_SHIFT))
523 return -ENOMEM;
524
525 spin_lock(&gpmc_mem_lock);
526 if (gpmc_cs_reserved(cs)) {
527 r = -EBUSY;
528 goto out;
529 }
530 if (gpmc_cs_mem_enabled(cs))
531 r = adjust_resource(res, res->start & ~(size - 1), size);
532 if (r < 0)
533 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
534 size, NULL, NULL);
535 if (r < 0)
536 goto out;
537
538 gpmc_cs_enable_mem(cs, res->start, resource_size(res));
539 *base = res->start;
540 gpmc_cs_set_reserved(cs, 1);
541 out:
542 spin_unlock(&gpmc_mem_lock);
543 return r;
544 }
545 EXPORT_SYMBOL(gpmc_cs_request);
546
547 void gpmc_cs_free(int cs)
548 {
549 spin_lock(&gpmc_mem_lock);
550 if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
551 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
552 BUG();
553 spin_unlock(&gpmc_mem_lock);
554 return;
555 }
556 gpmc_cs_disable_mem(cs);
557 release_resource(&gpmc_cs_mem[cs]);
558 gpmc_cs_set_reserved(cs, 0);
559 spin_unlock(&gpmc_mem_lock);
560 }
561 EXPORT_SYMBOL(gpmc_cs_free);
562
563 /**
564 * gpmc_cs_configure - write request to configure gpmc
565 * @cs: chip select number
566 * @cmd: command type
567 * @wval: value to write
568 * @return status of the operation
569 */
570 int gpmc_cs_configure(int cs, int cmd, int wval)
571 {
572 int err = 0;
573 u32 regval = 0;
574
575 switch (cmd) {
576 case GPMC_ENABLE_IRQ:
577 gpmc_write_reg(GPMC_IRQENABLE, wval);
578 break;
579
580 case GPMC_SET_IRQ_STATUS:
581 gpmc_write_reg(GPMC_IRQSTATUS, wval);
582 break;
583
584 case GPMC_CONFIG_WP:
585 regval = gpmc_read_reg(GPMC_CONFIG);
586 if (wval)
587 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
588 else
589 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
590 gpmc_write_reg(GPMC_CONFIG, regval);
591 break;
592
593 case GPMC_CONFIG_RDY_BSY:
594 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
595 if (wval)
596 regval |= WR_RD_PIN_MONITORING;
597 else
598 regval &= ~WR_RD_PIN_MONITORING;
599 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
600 break;
601
602 case GPMC_CONFIG_DEV_SIZE:
603 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
604
605 /* clear 2 target bits */
606 regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
607
608 /* set the proper value */
609 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
610
611 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
612 break;
613
614 case GPMC_CONFIG_DEV_TYPE:
615 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
616 regval |= GPMC_CONFIG1_DEVICETYPE(wval);
617 if (wval == GPMC_DEVICETYPE_NOR)
618 regval |= GPMC_CONFIG1_MUXADDDATA;
619 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
620 break;
621
622 default:
623 printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
624 err = -EINVAL;
625 }
626
627 return err;
628 }
629 EXPORT_SYMBOL(gpmc_cs_configure);
630
631 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
632 {
633 int i;
634
635 reg->gpmc_status = gpmc_base + GPMC_STATUS;
636 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
637 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
638 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
639 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
640 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
641 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
642 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
643 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
644 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
645 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
646 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
647 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
648 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
649 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
650
651 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
652 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
653 GPMC_BCH_SIZE * i;
654 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
655 GPMC_BCH_SIZE * i;
656 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
657 GPMC_BCH_SIZE * i;
658 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
659 GPMC_BCH_SIZE * i;
660 }
661 }
662
663 int gpmc_get_client_irq(unsigned irq_config)
664 {
665 int i;
666
667 if (hweight32(irq_config) > 1)
668 return 0;
669
670 for (i = 0; i < GPMC_NR_IRQ; i++)
671 if (gpmc_client_irq[i].bitmask & irq_config)
672 return gpmc_client_irq[i].irq;
673
674 return 0;
675 }
676
677 static int gpmc_irq_endis(unsigned irq, bool endis)
678 {
679 int i;
680 u32 regval;
681
682 for (i = 0; i < GPMC_NR_IRQ; i++)
683 if (irq == gpmc_client_irq[i].irq) {
684 regval = gpmc_read_reg(GPMC_IRQENABLE);
685 if (endis)
686 regval |= gpmc_client_irq[i].bitmask;
687 else
688 regval &= ~gpmc_client_irq[i].bitmask;
689 gpmc_write_reg(GPMC_IRQENABLE, regval);
690 break;
691 }
692
693 return 0;
694 }
695
696 static void gpmc_irq_disable(struct irq_data *p)
697 {
698 gpmc_irq_endis(p->irq, false);
699 }
700
701 static void gpmc_irq_enable(struct irq_data *p)
702 {
703 gpmc_irq_endis(p->irq, true);
704 }
705
706 static void gpmc_irq_noop(struct irq_data *data) { }
707
708 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
709
710 static int gpmc_setup_irq(void)
711 {
712 int i;
713 u32 regval;
714
715 if (!gpmc_irq)
716 return -EINVAL;
717
718 gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
719 if (IS_ERR_VALUE(gpmc_irq_start)) {
720 pr_err("irq_alloc_descs failed\n");
721 return gpmc_irq_start;
722 }
723
724 gpmc_irq_chip.name = "gpmc";
725 gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
726 gpmc_irq_chip.irq_enable = gpmc_irq_enable;
727 gpmc_irq_chip.irq_disable = gpmc_irq_disable;
728 gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
729 gpmc_irq_chip.irq_ack = gpmc_irq_noop;
730 gpmc_irq_chip.irq_mask = gpmc_irq_noop;
731 gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
732
733 gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
734 gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
735
736 for (i = 0; i < GPMC_NR_IRQ; i++) {
737 gpmc_client_irq[i].irq = gpmc_irq_start + i;
738 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
739 &gpmc_irq_chip, handle_simple_irq);
740 set_irq_flags(gpmc_client_irq[i].irq,
741 IRQF_VALID | IRQF_NOAUTOEN);
742 }
743
744 /* Disable interrupts */
745 gpmc_write_reg(GPMC_IRQENABLE, 0);
746
747 /* clear interrupts */
748 regval = gpmc_read_reg(GPMC_IRQSTATUS);
749 gpmc_write_reg(GPMC_IRQSTATUS, regval);
750
751 return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
752 }
753
754 static int gpmc_free_irq(void)
755 {
756 int i;
757
758 if (gpmc_irq)
759 free_irq(gpmc_irq, NULL);
760
761 for (i = 0; i < GPMC_NR_IRQ; i++) {
762 irq_set_handler(gpmc_client_irq[i].irq, NULL);
763 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
764 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
765 }
766
767 irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
768
769 return 0;
770 }
771
772 static void gpmc_mem_exit(void)
773 {
774 int cs;
775
776 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
777 if (!gpmc_cs_mem_enabled(cs))
778 continue;
779 gpmc_cs_delete_mem(cs);
780 }
781
782 }
783
784 static int gpmc_mem_init(void)
785 {
786 int cs, rc;
787 unsigned long boot_rom_space = 0;
788
789 /* never allocate the first page, to facilitate bug detection;
790 * even if we didn't boot from ROM.
791 */
792 boot_rom_space = BOOT_ROM_SPACE;
793 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
794 gpmc_mem_root.end = GPMC_MEM_END;
795
796 /* Reserve all regions that has been set up by bootloader */
797 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
798 u32 base, size;
799
800 if (!gpmc_cs_mem_enabled(cs))
801 continue;
802 gpmc_cs_get_memconf(cs, &base, &size);
803 rc = gpmc_cs_insert_mem(cs, base, size);
804 if (IS_ERR_VALUE(rc)) {
805 while (--cs >= 0)
806 if (gpmc_cs_mem_enabled(cs))
807 gpmc_cs_delete_mem(cs);
808 return rc;
809 }
810 }
811
812 return 0;
813 }
814
815 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
816 {
817 u32 temp;
818 int div;
819
820 div = gpmc_calc_divider(sync_clk);
821 temp = gpmc_ps_to_ticks(time_ps);
822 temp = (temp + div - 1) / div;
823 return gpmc_ticks_to_ps(temp * div);
824 }
825
826 /* XXX: can the cycles be avoided ? */
827 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
828 struct gpmc_device_timings *dev_t)
829 {
830 bool mux = dev_t->mux;
831 u32 temp;
832
833 /* adv_rd_off */
834 temp = dev_t->t_avdp_r;
835 /* XXX: mux check required ? */
836 if (mux) {
837 /* XXX: t_avdp not to be required for sync, only added for tusb
838 * this indirectly necessitates requirement of t_avdp_r and
839 * t_avdp_w instead of having a single t_avdp
840 */
841 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
842 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
843 }
844 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
845
846 /* oe_on */
847 temp = dev_t->t_oeasu; /* XXX: remove this ? */
848 if (mux) {
849 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
850 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
851 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
852 }
853 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
854
855 /* access */
856 /* XXX: any scope for improvement ?, by combining oe_on
857 * and clk_activation, need to check whether
858 * access = clk_activation + round to sync clk ?
859 */
860 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
861 temp += gpmc_t->clk_activation;
862 if (dev_t->cyc_oe)
863 temp = max_t(u32, temp, gpmc_t->oe_on +
864 gpmc_ticks_to_ps(dev_t->cyc_oe));
865 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
866
867 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
868 gpmc_t->cs_rd_off = gpmc_t->oe_off;
869
870 /* rd_cycle */
871 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
872 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
873 gpmc_t->access;
874 /* XXX: barter t_ce_rdyz with t_cez_r ? */
875 if (dev_t->t_ce_rdyz)
876 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
877 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
878
879 return 0;
880 }
881
882 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
883 struct gpmc_device_timings *dev_t)
884 {
885 bool mux = dev_t->mux;
886 u32 temp;
887
888 /* adv_wr_off */
889 temp = dev_t->t_avdp_w;
890 if (mux) {
891 temp = max_t(u32, temp,
892 gpmc_t->clk_activation + dev_t->t_avdh);
893 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
894 }
895 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
896
897 /* wr_data_mux_bus */
898 temp = max_t(u32, dev_t->t_weasu,
899 gpmc_t->clk_activation + dev_t->t_rdyo);
900 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
901 * and in that case remember to handle we_on properly
902 */
903 if (mux) {
904 temp = max_t(u32, temp,
905 gpmc_t->adv_wr_off + dev_t->t_aavdh);
906 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
907 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
908 }
909 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
910
911 /* we_on */
912 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
913 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
914 else
915 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
916
917 /* wr_access */
918 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
919 gpmc_t->wr_access = gpmc_t->access;
920
921 /* we_off */
922 temp = gpmc_t->we_on + dev_t->t_wpl;
923 temp = max_t(u32, temp,
924 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
925 temp = max_t(u32, temp,
926 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
927 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
928
929 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
930 dev_t->t_wph);
931
932 /* wr_cycle */
933 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
934 temp += gpmc_t->wr_access;
935 /* XXX: barter t_ce_rdyz with t_cez_w ? */
936 if (dev_t->t_ce_rdyz)
937 temp = max_t(u32, temp,
938 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
939 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
940
941 return 0;
942 }
943
944 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
945 struct gpmc_device_timings *dev_t)
946 {
947 bool mux = dev_t->mux;
948 u32 temp;
949
950 /* adv_rd_off */
951 temp = dev_t->t_avdp_r;
952 if (mux)
953 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
954 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
955
956 /* oe_on */
957 temp = dev_t->t_oeasu;
958 if (mux)
959 temp = max_t(u32, temp,
960 gpmc_t->adv_rd_off + dev_t->t_aavdh);
961 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
962
963 /* access */
964 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
965 gpmc_t->oe_on + dev_t->t_oe);
966 temp = max_t(u32, temp,
967 gpmc_t->cs_on + dev_t->t_ce);
968 temp = max_t(u32, temp,
969 gpmc_t->adv_on + dev_t->t_aa);
970 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
971
972 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
973 gpmc_t->cs_rd_off = gpmc_t->oe_off;
974
975 /* rd_cycle */
976 temp = max_t(u32, dev_t->t_rd_cycle,
977 gpmc_t->cs_rd_off + dev_t->t_cez_r);
978 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
979 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
980
981 return 0;
982 }
983
984 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
985 struct gpmc_device_timings *dev_t)
986 {
987 bool mux = dev_t->mux;
988 u32 temp;
989
990 /* adv_wr_off */
991 temp = dev_t->t_avdp_w;
992 if (mux)
993 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
994 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
995
996 /* wr_data_mux_bus */
997 temp = dev_t->t_weasu;
998 if (mux) {
999 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1000 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1001 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1002 }
1003 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1004
1005 /* we_on */
1006 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1007 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1008 else
1009 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1010
1011 /* we_off */
1012 temp = gpmc_t->we_on + dev_t->t_wpl;
1013 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1014
1015 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1016 dev_t->t_wph);
1017
1018 /* wr_cycle */
1019 temp = max_t(u32, dev_t->t_wr_cycle,
1020 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1021 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1022
1023 return 0;
1024 }
1025
1026 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1027 struct gpmc_device_timings *dev_t)
1028 {
1029 u32 temp;
1030
1031 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1032 gpmc_get_fclk_period();
1033
1034 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1035 dev_t->t_bacc,
1036 gpmc_t->sync_clk);
1037
1038 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1039 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1040
1041 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1042 return 0;
1043
1044 if (dev_t->ce_xdelay)
1045 gpmc_t->bool_timings.cs_extra_delay = true;
1046 if (dev_t->avd_xdelay)
1047 gpmc_t->bool_timings.adv_extra_delay = true;
1048 if (dev_t->oe_xdelay)
1049 gpmc_t->bool_timings.oe_extra_delay = true;
1050 if (dev_t->we_xdelay)
1051 gpmc_t->bool_timings.we_extra_delay = true;
1052
1053 return 0;
1054 }
1055
1056 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1057 struct gpmc_device_timings *dev_t)
1058 {
1059 u32 temp;
1060
1061 /* cs_on */
1062 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1063
1064 /* adv_on */
1065 temp = dev_t->t_avdasu;
1066 if (dev_t->t_ce_avd)
1067 temp = max_t(u32, temp,
1068 gpmc_t->cs_on + dev_t->t_ce_avd);
1069 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1070
1071 if (dev_t->sync_write || dev_t->sync_read)
1072 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1073
1074 return 0;
1075 }
1076
1077 /* TODO: remove this function once all peripherals are confirmed to
1078 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1079 * has to be modified to handle timings in ps instead of ns
1080 */
1081 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1082 {
1083 t->cs_on /= 1000;
1084 t->cs_rd_off /= 1000;
1085 t->cs_wr_off /= 1000;
1086 t->adv_on /= 1000;
1087 t->adv_rd_off /= 1000;
1088 t->adv_wr_off /= 1000;
1089 t->we_on /= 1000;
1090 t->we_off /= 1000;
1091 t->oe_on /= 1000;
1092 t->oe_off /= 1000;
1093 t->page_burst_access /= 1000;
1094 t->access /= 1000;
1095 t->rd_cycle /= 1000;
1096 t->wr_cycle /= 1000;
1097 t->bus_turnaround /= 1000;
1098 t->cycle2cycle_delay /= 1000;
1099 t->wait_monitoring /= 1000;
1100 t->clk_activation /= 1000;
1101 t->wr_access /= 1000;
1102 t->wr_data_mux_bus /= 1000;
1103 }
1104
1105 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1106 struct gpmc_device_timings *dev_t)
1107 {
1108 memset(gpmc_t, 0, sizeof(*gpmc_t));
1109
1110 gpmc_calc_common_timings(gpmc_t, dev_t);
1111
1112 if (dev_t->sync_read)
1113 gpmc_calc_sync_read_timings(gpmc_t, dev_t);
1114 else
1115 gpmc_calc_async_read_timings(gpmc_t, dev_t);
1116
1117 if (dev_t->sync_write)
1118 gpmc_calc_sync_write_timings(gpmc_t, dev_t);
1119 else
1120 gpmc_calc_async_write_timings(gpmc_t, dev_t);
1121
1122 /* TODO: remove, see function definition */
1123 gpmc_convert_ps_to_ns(gpmc_t);
1124
1125 return 0;
1126 }
1127
1128 #ifdef CONFIG_OF
1129 static struct of_device_id gpmc_dt_ids[] = {
1130 { .compatible = "ti,omap2420-gpmc" },
1131 { .compatible = "ti,omap2430-gpmc" },
1132 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1133 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1134 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1135 { }
1136 };
1137 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1138
1139 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1140 struct gpmc_timings *gpmc_t)
1141 {
1142 u32 val;
1143
1144 memset(gpmc_t, 0, sizeof(*gpmc_t));
1145
1146 /* minimum clock period for syncronous mode */
1147 if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
1148 gpmc_t->sync_clk = val;
1149
1150 /* chip select timtings */
1151 if (!of_property_read_u32(np, "gpmc,cs-on", &val))
1152 gpmc_t->cs_on = val;
1153
1154 if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
1155 gpmc_t->cs_rd_off = val;
1156
1157 if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
1158 gpmc_t->cs_wr_off = val;
1159
1160 /* ADV signal timings */
1161 if (!of_property_read_u32(np, "gpmc,adv-on", &val))
1162 gpmc_t->adv_on = val;
1163
1164 if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
1165 gpmc_t->adv_rd_off = val;
1166
1167 if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
1168 gpmc_t->adv_wr_off = val;
1169
1170 /* WE signal timings */
1171 if (!of_property_read_u32(np, "gpmc,we-on", &val))
1172 gpmc_t->we_on = val;
1173
1174 if (!of_property_read_u32(np, "gpmc,we-off", &val))
1175 gpmc_t->we_off = val;
1176
1177 /* OE signal timings */
1178 if (!of_property_read_u32(np, "gpmc,oe-on", &val))
1179 gpmc_t->oe_on = val;
1180
1181 if (!of_property_read_u32(np, "gpmc,oe-off", &val))
1182 gpmc_t->oe_off = val;
1183
1184 /* access and cycle timings */
1185 if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
1186 gpmc_t->page_burst_access = val;
1187
1188 if (!of_property_read_u32(np, "gpmc,access", &val))
1189 gpmc_t->access = val;
1190
1191 if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
1192 gpmc_t->rd_cycle = val;
1193
1194 if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
1195 gpmc_t->wr_cycle = val;
1196
1197 /* only for OMAP3430 */
1198 if (!of_property_read_u32(np, "gpmc,wr-access", &val))
1199 gpmc_t->wr_access = val;
1200
1201 if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
1202 gpmc_t->wr_data_mux_bus = val;
1203 }
1204
1205 #ifdef CONFIG_MTD_NAND
1206
1207 static const char * const nand_ecc_opts[] = {
1208 [OMAP_ECC_HAMMING_CODE_DEFAULT] = "sw",
1209 [OMAP_ECC_HAMMING_CODE_HW] = "hw",
1210 [OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = "hw-romcode",
1211 [OMAP_ECC_BCH4_CODE_HW] = "bch4",
1212 [OMAP_ECC_BCH8_CODE_HW] = "bch8",
1213 };
1214
1215 static int gpmc_probe_nand_child(struct platform_device *pdev,
1216 struct device_node *child)
1217 {
1218 u32 val;
1219 const char *s;
1220 struct gpmc_timings gpmc_t;
1221 struct omap_nand_platform_data *gpmc_nand_data;
1222
1223 if (of_property_read_u32(child, "reg", &val) < 0) {
1224 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1225 child->full_name);
1226 return -ENODEV;
1227 }
1228
1229 gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1230 GFP_KERNEL);
1231 if (!gpmc_nand_data)
1232 return -ENOMEM;
1233
1234 gpmc_nand_data->cs = val;
1235 gpmc_nand_data->of_node = child;
1236
1237 if (!of_property_read_string(child, "ti,nand-ecc-opt", &s))
1238 for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++)
1239 if (!strcasecmp(s, nand_ecc_opts[val])) {
1240 gpmc_nand_data->ecc_opt = val;
1241 break;
1242 }
1243
1244 val = of_get_nand_bus_width(child);
1245 if (val == 16)
1246 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1247
1248 gpmc_read_timings_dt(child, &gpmc_t);
1249 gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1250
1251 return 0;
1252 }
1253 #else
1254 static int gpmc_probe_nand_child(struct platform_device *pdev,
1255 struct device_node *child)
1256 {
1257 return 0;
1258 }
1259 #endif
1260
1261 #ifdef CONFIG_MTD_ONENAND
1262 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1263 struct device_node *child)
1264 {
1265 u32 val;
1266 struct omap_onenand_platform_data *gpmc_onenand_data;
1267
1268 if (of_property_read_u32(child, "reg", &val) < 0) {
1269 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1270 child->full_name);
1271 return -ENODEV;
1272 }
1273
1274 gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1275 GFP_KERNEL);
1276 if (!gpmc_onenand_data)
1277 return -ENOMEM;
1278
1279 gpmc_onenand_data->cs = val;
1280 gpmc_onenand_data->of_node = child;
1281 gpmc_onenand_data->dma_channel = -1;
1282
1283 if (!of_property_read_u32(child, "dma-channel", &val))
1284 gpmc_onenand_data->dma_channel = val;
1285
1286 gpmc_onenand_init(gpmc_onenand_data);
1287
1288 return 0;
1289 }
1290 #else
1291 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1292 struct device_node *child)
1293 {
1294 return 0;
1295 }
1296 #endif
1297
1298 static int gpmc_probe_dt(struct platform_device *pdev)
1299 {
1300 int ret;
1301 struct device_node *child;
1302 const struct of_device_id *of_id =
1303 of_match_device(gpmc_dt_ids, &pdev->dev);
1304
1305 if (!of_id)
1306 return 0;
1307
1308 for_each_node_by_name(child, "nand") {
1309 ret = gpmc_probe_nand_child(pdev, child);
1310 if (ret < 0) {
1311 of_node_put(child);
1312 return ret;
1313 }
1314 }
1315
1316 for_each_node_by_name(child, "onenand") {
1317 ret = gpmc_probe_onenand_child(pdev, child);
1318 if (ret < 0) {
1319 of_node_put(child);
1320 return ret;
1321 }
1322 }
1323 return 0;
1324 }
1325 #else
1326 static int gpmc_probe_dt(struct platform_device *pdev)
1327 {
1328 return 0;
1329 }
1330 #endif
1331
1332 static int gpmc_probe(struct platform_device *pdev)
1333 {
1334 int rc;
1335 u32 l;
1336 struct resource *res;
1337
1338 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1339 if (res == NULL)
1340 return -ENOENT;
1341
1342 phys_base = res->start;
1343 mem_size = resource_size(res);
1344
1345 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
1346 if (IS_ERR(gpmc_base))
1347 return PTR_ERR(gpmc_base);
1348
1349 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1350 if (res == NULL)
1351 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
1352 else
1353 gpmc_irq = res->start;
1354
1355 gpmc_l3_clk = clk_get(&pdev->dev, "fck");
1356 if (IS_ERR(gpmc_l3_clk)) {
1357 dev_err(&pdev->dev, "error: clk_get\n");
1358 gpmc_irq = 0;
1359 return PTR_ERR(gpmc_l3_clk);
1360 }
1361
1362 clk_prepare_enable(gpmc_l3_clk);
1363
1364 gpmc_dev = &pdev->dev;
1365
1366 l = gpmc_read_reg(GPMC_REVISION);
1367 if (GPMC_REVISION_MAJOR(l) > 0x4)
1368 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
1369 dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
1370 GPMC_REVISION_MINOR(l));
1371
1372 rc = gpmc_mem_init();
1373 if (IS_ERR_VALUE(rc)) {
1374 clk_disable_unprepare(gpmc_l3_clk);
1375 clk_put(gpmc_l3_clk);
1376 dev_err(gpmc_dev, "failed to reserve memory\n");
1377 return rc;
1378 }
1379
1380 if (IS_ERR_VALUE(gpmc_setup_irq()))
1381 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
1382
1383 /* Now the GPMC is initialised, unreserve the chip-selects */
1384 gpmc_cs_map = 0;
1385
1386 rc = gpmc_probe_dt(pdev);
1387 if (rc < 0) {
1388 clk_disable_unprepare(gpmc_l3_clk);
1389 clk_put(gpmc_l3_clk);
1390 dev_err(gpmc_dev, "failed to probe DT parameters\n");
1391 return rc;
1392 }
1393
1394 return 0;
1395 }
1396
1397 static int gpmc_remove(struct platform_device *pdev)
1398 {
1399 gpmc_free_irq();
1400 gpmc_mem_exit();
1401 gpmc_dev = NULL;
1402 return 0;
1403 }
1404
1405 static struct platform_driver gpmc_driver = {
1406 .probe = gpmc_probe,
1407 .remove = gpmc_remove,
1408 .driver = {
1409 .name = DEVICE_NAME,
1410 .owner = THIS_MODULE,
1411 .of_match_table = of_match_ptr(gpmc_dt_ids),
1412 },
1413 };
1414
1415 static __init int gpmc_init(void)
1416 {
1417 return platform_driver_register(&gpmc_driver);
1418 }
1419
1420 static __exit void gpmc_exit(void)
1421 {
1422 platform_driver_unregister(&gpmc_driver);
1423
1424 }
1425
1426 omap_postcore_initcall(gpmc_init);
1427 module_exit(gpmc_exit);
1428
1429 static int __init omap_gpmc_init(void)
1430 {
1431 struct omap_hwmod *oh;
1432 struct platform_device *pdev;
1433 char *oh_name = "gpmc";
1434
1435 /*
1436 * if the board boots up with a populated DT, do not
1437 * manually add the device from this initcall
1438 */
1439 if (of_have_populated_dt())
1440 return -ENODEV;
1441
1442 oh = omap_hwmod_lookup(oh_name);
1443 if (!oh) {
1444 pr_err("Could not look up %s\n", oh_name);
1445 return -ENODEV;
1446 }
1447
1448 pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0);
1449 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
1450
1451 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
1452 }
1453 omap_postcore_initcall(omap_gpmc_init);
1454
1455 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
1456 {
1457 int i;
1458 u32 regval;
1459
1460 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1461
1462 if (!regval)
1463 return IRQ_NONE;
1464
1465 for (i = 0; i < GPMC_NR_IRQ; i++)
1466 if (regval & gpmc_client_irq[i].bitmask)
1467 generic_handle_irq(gpmc_client_irq[i].irq);
1468
1469 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1470
1471 return IRQ_HANDLED;
1472 }
1473
1474 #ifdef CONFIG_ARCH_OMAP3
1475 static struct omap3_gpmc_regs gpmc_context;
1476
1477 void omap3_gpmc_save_context(void)
1478 {
1479 int i;
1480
1481 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
1482 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
1483 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
1484 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
1485 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
1486 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
1487 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
1488 for (i = 0; i < GPMC_CS_NUM; i++) {
1489 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
1490 if (gpmc_context.cs_context[i].is_valid) {
1491 gpmc_context.cs_context[i].config1 =
1492 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
1493 gpmc_context.cs_context[i].config2 =
1494 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
1495 gpmc_context.cs_context[i].config3 =
1496 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
1497 gpmc_context.cs_context[i].config4 =
1498 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
1499 gpmc_context.cs_context[i].config5 =
1500 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
1501 gpmc_context.cs_context[i].config6 =
1502 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
1503 gpmc_context.cs_context[i].config7 =
1504 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
1505 }
1506 }
1507 }
1508
1509 void omap3_gpmc_restore_context(void)
1510 {
1511 int i;
1512
1513 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
1514 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
1515 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
1516 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
1517 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
1518 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
1519 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
1520 for (i = 0; i < GPMC_CS_NUM; i++) {
1521 if (gpmc_context.cs_context[i].is_valid) {
1522 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
1523 gpmc_context.cs_context[i].config1);
1524 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
1525 gpmc_context.cs_context[i].config2);
1526 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
1527 gpmc_context.cs_context[i].config3);
1528 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
1529 gpmc_context.cs_context[i].config4);
1530 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
1531 gpmc_context.cs_context[i].config5);
1532 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
1533 gpmc_context.cs_context[i].config6);
1534 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
1535 gpmc_context.cs_context[i].config7);
1536 }
1537 }
1538 }
1539 #endif /* CONFIG_ARCH_OMAP3 */
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