2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/err.h>
15 #include <linux/clk.h>
16 #include <linux/ioport.h>
17 #include <linux/spinlock.h>
20 #include <asm/mach-types.h>
21 #include <asm/arch/gpmc.h>
25 #ifdef CONFIG_ARCH_OMAP2420
26 #define GPMC_BASE 0x6800a000
29 #ifdef CONFIG_ARCH_OMAP2430
30 #define GPMC_BASE 0x6E000000
33 #define GPMC_REVISION 0x00
34 #define GPMC_SYSCONFIG 0x10
35 #define GPMC_SYSSTATUS 0x14
36 #define GPMC_IRQSTATUS 0x18
37 #define GPMC_IRQENABLE 0x1c
38 #define GPMC_TIMEOUT_CONTROL 0x40
39 #define GPMC_ERR_ADDRESS 0x44
40 #define GPMC_ERR_TYPE 0x48
41 #define GPMC_CONFIG 0x50
42 #define GPMC_STATUS 0x54
43 #define GPMC_PREFETCH_CONFIG1 0x1e0
44 #define GPMC_PREFETCH_CONFIG2 0x1e4
45 #define GPMC_PREFETCH_CONTROL 0x1e8
46 #define GPMC_PREFETCH_STATUS 0x1f0
47 #define GPMC_ECC_CONFIG 0x1f4
48 #define GPMC_ECC_CONTROL 0x1f8
49 #define GPMC_ECC_SIZE_CONFIG 0x1fc
52 #define GPMC_CS_SIZE 0x30
55 #define GPMC_MEM_START 0x00000000
56 #define GPMC_MEM_END 0x3FFFFFFF
57 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
59 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
60 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
62 static struct resource gpmc_mem_root
;
63 static struct resource gpmc_cs_mem
[GPMC_CS_NUM
];
64 static DEFINE_SPINLOCK(gpmc_mem_lock
);
65 static unsigned gpmc_cs_map
;
67 static void __iomem
*gpmc_base
=
68 (void __iomem
*) IO_ADDRESS(GPMC_BASE
);
69 static void __iomem
*gpmc_cs_base
=
70 (void __iomem
*) IO_ADDRESS(GPMC_BASE
) + GPMC_CS0
;
72 static struct clk
*gpmc_fck
;
74 static void gpmc_write_reg(int idx
, u32 val
)
76 __raw_writel(val
, gpmc_base
+ idx
);
79 static u32
gpmc_read_reg(int idx
)
81 return __raw_readl(gpmc_base
+ idx
);
84 void gpmc_cs_write_reg(int cs
, int idx
, u32 val
)
86 void __iomem
*reg_addr
;
88 reg_addr
= gpmc_cs_base
+ (cs
* GPMC_CS_SIZE
) + idx
;
89 __raw_writel(val
, reg_addr
);
92 u32
gpmc_cs_read_reg(int cs
, int idx
)
94 return __raw_readl(gpmc_cs_base
+ (cs
* GPMC_CS_SIZE
) + idx
);
97 unsigned long gpmc_get_fclk_period(void)
100 return 1000000000 / ((clk_get_rate(gpmc_fck
)) / 1000);
103 unsigned int gpmc_ns_to_ticks(unsigned int time_ns
)
105 unsigned long tick_ps
;
107 /* Calculate in picosecs to yield more exact results */
108 tick_ps
= gpmc_get_fclk_period();
110 return (time_ns
* 1000 + tick_ps
- 1) / tick_ps
;
113 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns
)
115 unsigned long ticks
= gpmc_ns_to_ticks(time_ns
);
117 return ticks
* gpmc_get_fclk_period() / 1000;
121 static int set_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
,
122 int time
, const char *name
)
124 static int set_gpmc_timing_reg(int cs
, int reg
, int st_bit
, int end_bit
,
129 int ticks
, mask
, nr_bits
;
134 ticks
= gpmc_ns_to_ticks(time
);
135 nr_bits
= end_bit
- st_bit
+ 1;
136 if (ticks
>= 1 << nr_bits
) {
138 printk(KERN_INFO
"GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
139 cs
, name
, time
, ticks
, 1 << nr_bits
);
144 mask
= (1 << nr_bits
) - 1;
145 l
= gpmc_cs_read_reg(cs
, reg
);
148 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
149 cs
, name
, ticks
, gpmc_get_fclk_period() * ticks
/ 1000,
150 (l
>> st_bit
) & mask
, time
);
152 l
&= ~(mask
<< st_bit
);
153 l
|= ticks
<< st_bit
;
154 gpmc_cs_write_reg(cs
, reg
, l
);
160 #define GPMC_SET_ONE(reg, st, end, field) \
161 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
162 t->field, #field) < 0) \
165 #define GPMC_SET_ONE(reg, st, end, field) \
166 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
170 int gpmc_cs_calc_divider(int cs
, unsigned int sync_clk
)
175 l
= sync_clk
* 1000 + (gpmc_get_fclk_period() - 1);
176 div
= l
/ gpmc_get_fclk_period();
185 int gpmc_cs_set_timings(int cs
, const struct gpmc_timings
*t
)
190 div
= gpmc_cs_calc_divider(cs
, t
->sync_clk
);
194 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 0, 3, cs_on
);
195 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 8, 12, cs_rd_off
);
196 GPMC_SET_ONE(GPMC_CS_CONFIG2
, 16, 20, cs_wr_off
);
198 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 0, 3, adv_on
);
199 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 8, 12, adv_rd_off
);
200 GPMC_SET_ONE(GPMC_CS_CONFIG3
, 16, 20, adv_wr_off
);
202 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 0, 3, oe_on
);
203 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 8, 12, oe_off
);
204 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 16, 19, we_on
);
205 GPMC_SET_ONE(GPMC_CS_CONFIG4
, 24, 28, we_off
);
207 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 0, 4, rd_cycle
);
208 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 8, 12, wr_cycle
);
209 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 16, 20, access
);
211 GPMC_SET_ONE(GPMC_CS_CONFIG5
, 24, 27, page_burst_access
);
213 /* caller is expected to have initialized CONFIG1 to cover
214 * at least sync vs async
216 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG1
);
217 if (l
& (GPMC_CONFIG1_READTYPE_SYNC
| GPMC_CONFIG1_WRITETYPE_SYNC
)) {
219 printk(KERN_INFO
"GPMC CS%d CLK period is %lu ns (div %d)\n",
220 cs
, (div
* gpmc_get_fclk_period()) / 1000, div
);
224 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG1
, l
);
230 static void gpmc_cs_enable_mem(int cs
, u32 base
, u32 size
)
235 mask
= (1 << GPMC_SECTION_SHIFT
) - size
;
236 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
238 l
= (base
>> GPMC_CHUNK_SHIFT
) & 0x3f;
240 l
|= ((mask
>> GPMC_CHUNK_SHIFT
) & 0x0f) << 8;
241 l
|= 1 << 6; /* CSVALID */
242 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
245 static void gpmc_cs_disable_mem(int cs
)
249 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
250 l
&= ~(1 << 6); /* CSVALID */
251 gpmc_cs_write_reg(cs
, GPMC_CS_CONFIG7
, l
);
254 static void gpmc_cs_get_memconf(int cs
, u32
*base
, u32
*size
)
259 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
260 *base
= (l
& 0x3f) << GPMC_CHUNK_SHIFT
;
261 mask
= (l
>> 8) & 0x0f;
262 *size
= (1 << GPMC_SECTION_SHIFT
) - (mask
<< GPMC_CHUNK_SHIFT
);
265 static int gpmc_cs_mem_enabled(int cs
)
269 l
= gpmc_cs_read_reg(cs
, GPMC_CS_CONFIG7
);
273 int gpmc_cs_set_reserved(int cs
, int reserved
)
275 if (cs
> GPMC_CS_NUM
)
278 gpmc_cs_map
&= ~(1 << cs
);
279 gpmc_cs_map
|= (reserved
? 1 : 0) << cs
;
284 int gpmc_cs_reserved(int cs
)
286 if (cs
> GPMC_CS_NUM
)
289 return gpmc_cs_map
& (1 << cs
);
292 static unsigned long gpmc_mem_align(unsigned long size
)
296 size
= (size
- 1) >> (GPMC_CHUNK_SHIFT
- 1);
297 order
= GPMC_CHUNK_SHIFT
- 1;
306 static int gpmc_cs_insert_mem(int cs
, unsigned long base
, unsigned long size
)
308 struct resource
*res
= &gpmc_cs_mem
[cs
];
311 size
= gpmc_mem_align(size
);
312 spin_lock(&gpmc_mem_lock
);
314 res
->end
= base
+ size
- 1;
315 r
= request_resource(&gpmc_mem_root
, res
);
316 spin_unlock(&gpmc_mem_lock
);
321 int gpmc_cs_request(int cs
, unsigned long size
, unsigned long *base
)
323 struct resource
*res
= &gpmc_cs_mem
[cs
];
326 if (cs
> GPMC_CS_NUM
)
329 size
= gpmc_mem_align(size
);
330 if (size
> (1 << GPMC_SECTION_SHIFT
))
333 spin_lock(&gpmc_mem_lock
);
334 if (gpmc_cs_reserved(cs
)) {
338 if (gpmc_cs_mem_enabled(cs
))
339 r
= adjust_resource(res
, res
->start
& ~(size
- 1), size
);
341 r
= allocate_resource(&gpmc_mem_root
, res
, size
, 0, ~0,
346 gpmc_cs_enable_mem(cs
, res
->start
, res
->end
- res
->start
+ 1);
348 gpmc_cs_set_reserved(cs
, 1);
350 spin_unlock(&gpmc_mem_lock
);
354 void gpmc_cs_free(int cs
)
356 spin_lock(&gpmc_mem_lock
);
357 if (cs
>= GPMC_CS_NUM
|| !gpmc_cs_reserved(cs
)) {
358 printk(KERN_ERR
"Trying to free non-reserved GPMC CS%d\n", cs
);
360 spin_unlock(&gpmc_mem_lock
);
363 gpmc_cs_disable_mem(cs
);
364 release_resource(&gpmc_cs_mem
[cs
]);
365 gpmc_cs_set_reserved(cs
, 0);
366 spin_unlock(&gpmc_mem_lock
);
369 void __init
gpmc_mem_init(void)
372 unsigned long boot_rom_space
= 0;
374 /* never allocate the first page, to facilitate bug detection;
375 * even if we didn't boot from ROM.
377 boot_rom_space
= BOOT_ROM_SPACE
;
378 /* In apollon the CS0 is mapped as 0x0000 0000 */
379 if (machine_is_omap_apollon())
381 gpmc_mem_root
.start
= GPMC_MEM_START
+ boot_rom_space
;
382 gpmc_mem_root
.end
= GPMC_MEM_END
;
384 /* Reserve all regions that has been set up by bootloader */
385 for (cs
= 0; cs
< GPMC_CS_NUM
; cs
++) {
388 if (!gpmc_cs_mem_enabled(cs
))
390 gpmc_cs_get_memconf(cs
, &base
, &size
);
391 if (gpmc_cs_insert_mem(cs
, base
, size
) < 0)
396 void __init
gpmc_init(void)
400 gpmc_fck
= clk_get(NULL
, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
401 if (IS_ERR(gpmc_fck
))
404 clk_enable(gpmc_fck
);
406 l
= gpmc_read_reg(GPMC_REVISION
);
407 printk(KERN_INFO
"GPMC revision %d.%d\n", (l
>> 4) & 0x0f, l
& 0x0f);
408 /* Set smart idle mode and automatic L3 clock gating */
409 l
= gpmc_read_reg(GPMC_SYSCONFIG
);
411 l
|= (0x02 << 3) | (1 << 0);
412 gpmc_write_reg(GPMC_SYSCONFIG
, l
);