2 * linux/arch/arm/mach-omap2/io.c
4 * OMAP2 I/O mapping code
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
24 #include <linux/clk.h>
25 #include <linux/omapfb.h>
29 #include <asm/mach/map.h>
31 #include <plat/sram.h>
32 #include <plat/sdrc.h>
33 #include <plat/serial.h>
35 #include "clock2xxx.h"
36 #include "clock3xxx.h"
37 #include "clock44xx.h"
40 #include <plat/omap-pm.h>
41 #include "powerdomain.h"
43 #include "clockdomain.h"
44 #include <plat/omap_hwmod.h>
45 #include <plat/multi.h>
48 * The machine specific code may provide the extra mapping besides the
49 * default mapping provided here.
52 #ifdef CONFIG_ARCH_OMAP2
53 static struct map_desc omap24xx_io_desc
[] __initdata
= {
55 .virtual = L3_24XX_VIRT
,
56 .pfn
= __phys_to_pfn(L3_24XX_PHYS
),
57 .length
= L3_24XX_SIZE
,
61 .virtual = L4_24XX_VIRT
,
62 .pfn
= __phys_to_pfn(L4_24XX_PHYS
),
63 .length
= L4_24XX_SIZE
,
68 #ifdef CONFIG_SOC_OMAP2420
69 static struct map_desc omap242x_io_desc
[] __initdata
= {
71 .virtual = DSP_MEM_2420_VIRT
,
72 .pfn
= __phys_to_pfn(DSP_MEM_2420_PHYS
),
73 .length
= DSP_MEM_2420_SIZE
,
77 .virtual = DSP_IPI_2420_VIRT
,
78 .pfn
= __phys_to_pfn(DSP_IPI_2420_PHYS
),
79 .length
= DSP_IPI_2420_SIZE
,
83 .virtual = DSP_MMU_2420_VIRT
,
84 .pfn
= __phys_to_pfn(DSP_MMU_2420_PHYS
),
85 .length
= DSP_MMU_2420_SIZE
,
92 #ifdef CONFIG_SOC_OMAP2430
93 static struct map_desc omap243x_io_desc
[] __initdata
= {
95 .virtual = L4_WK_243X_VIRT
,
96 .pfn
= __phys_to_pfn(L4_WK_243X_PHYS
),
97 .length
= L4_WK_243X_SIZE
,
101 .virtual = OMAP243X_GPMC_VIRT
,
102 .pfn
= __phys_to_pfn(OMAP243X_GPMC_PHYS
),
103 .length
= OMAP243X_GPMC_SIZE
,
107 .virtual = OMAP243X_SDRC_VIRT
,
108 .pfn
= __phys_to_pfn(OMAP243X_SDRC_PHYS
),
109 .length
= OMAP243X_SDRC_SIZE
,
113 .virtual = OMAP243X_SMS_VIRT
,
114 .pfn
= __phys_to_pfn(OMAP243X_SMS_PHYS
),
115 .length
= OMAP243X_SMS_SIZE
,
122 #ifdef CONFIG_ARCH_OMAP3
123 static struct map_desc omap34xx_io_desc
[] __initdata
= {
125 .virtual = L3_34XX_VIRT
,
126 .pfn
= __phys_to_pfn(L3_34XX_PHYS
),
127 .length
= L3_34XX_SIZE
,
131 .virtual = L4_34XX_VIRT
,
132 .pfn
= __phys_to_pfn(L4_34XX_PHYS
),
133 .length
= L4_34XX_SIZE
,
137 .virtual = OMAP34XX_GPMC_VIRT
,
138 .pfn
= __phys_to_pfn(OMAP34XX_GPMC_PHYS
),
139 .length
= OMAP34XX_GPMC_SIZE
,
143 .virtual = OMAP343X_SMS_VIRT
,
144 .pfn
= __phys_to_pfn(OMAP343X_SMS_PHYS
),
145 .length
= OMAP343X_SMS_SIZE
,
149 .virtual = OMAP343X_SDRC_VIRT
,
150 .pfn
= __phys_to_pfn(OMAP343X_SDRC_PHYS
),
151 .length
= OMAP343X_SDRC_SIZE
,
155 .virtual = L4_PER_34XX_VIRT
,
156 .pfn
= __phys_to_pfn(L4_PER_34XX_PHYS
),
157 .length
= L4_PER_34XX_SIZE
,
161 .virtual = L4_EMU_34XX_VIRT
,
162 .pfn
= __phys_to_pfn(L4_EMU_34XX_PHYS
),
163 .length
= L4_EMU_34XX_SIZE
,
166 #if defined(CONFIG_DEBUG_LL) && \
167 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
169 .virtual = ZOOM_UART_VIRT
,
170 .pfn
= __phys_to_pfn(ZOOM_UART_BASE
),
178 #ifdef CONFIG_SOC_OMAPTI816X
179 static struct map_desc omapti816x_io_desc
[] __initdata
= {
181 .virtual = L4_34XX_VIRT
,
182 .pfn
= __phys_to_pfn(L4_34XX_PHYS
),
183 .length
= L4_34XX_SIZE
,
189 #ifdef CONFIG_ARCH_OMAP4
190 static struct map_desc omap44xx_io_desc
[] __initdata
= {
192 .virtual = L3_44XX_VIRT
,
193 .pfn
= __phys_to_pfn(L3_44XX_PHYS
),
194 .length
= L3_44XX_SIZE
,
198 .virtual = L4_44XX_VIRT
,
199 .pfn
= __phys_to_pfn(L4_44XX_PHYS
),
200 .length
= L4_44XX_SIZE
,
204 .virtual = OMAP44XX_GPMC_VIRT
,
205 .pfn
= __phys_to_pfn(OMAP44XX_GPMC_PHYS
),
206 .length
= OMAP44XX_GPMC_SIZE
,
210 .virtual = OMAP44XX_EMIF1_VIRT
,
211 .pfn
= __phys_to_pfn(OMAP44XX_EMIF1_PHYS
),
212 .length
= OMAP44XX_EMIF1_SIZE
,
216 .virtual = OMAP44XX_EMIF2_VIRT
,
217 .pfn
= __phys_to_pfn(OMAP44XX_EMIF2_PHYS
),
218 .length
= OMAP44XX_EMIF2_SIZE
,
222 .virtual = OMAP44XX_DMM_VIRT
,
223 .pfn
= __phys_to_pfn(OMAP44XX_DMM_PHYS
),
224 .length
= OMAP44XX_DMM_SIZE
,
228 .virtual = L4_PER_44XX_VIRT
,
229 .pfn
= __phys_to_pfn(L4_PER_44XX_PHYS
),
230 .length
= L4_PER_44XX_SIZE
,
234 .virtual = L4_EMU_44XX_VIRT
,
235 .pfn
= __phys_to_pfn(L4_EMU_44XX_PHYS
),
236 .length
= L4_EMU_44XX_SIZE
,
242 static void __init
_omap2_map_common_io(void)
244 /* Normally devicemaps_init() would flush caches and tlb after
245 * mdesc->map_io(), but we must also do it here because of the CPU
246 * revision check below.
248 local_flush_tlb_all();
251 omap2_check_revision();
255 #ifdef CONFIG_SOC_OMAP2420
256 void __init
omap242x_map_common_io(void)
258 iotable_init(omap24xx_io_desc
, ARRAY_SIZE(omap24xx_io_desc
));
259 iotable_init(omap242x_io_desc
, ARRAY_SIZE(omap242x_io_desc
));
260 _omap2_map_common_io();
264 #ifdef CONFIG_SOC_OMAP2430
265 void __init
omap243x_map_common_io(void)
267 iotable_init(omap24xx_io_desc
, ARRAY_SIZE(omap24xx_io_desc
));
268 iotable_init(omap243x_io_desc
, ARRAY_SIZE(omap243x_io_desc
));
269 _omap2_map_common_io();
273 #ifdef CONFIG_ARCH_OMAP3
274 void __init
omap34xx_map_common_io(void)
276 iotable_init(omap34xx_io_desc
, ARRAY_SIZE(omap34xx_io_desc
));
277 _omap2_map_common_io();
281 #ifdef CONFIG_SOC_OMAPTI816X
282 void __init
omapti816x_map_common_io(void)
284 iotable_init(omapti816x_io_desc
, ARRAY_SIZE(omapti816x_io_desc
));
285 _omap2_map_common_io();
289 #ifdef CONFIG_ARCH_OMAP4
290 void __init
omap44xx_map_common_io(void)
292 iotable_init(omap44xx_io_desc
, ARRAY_SIZE(omap44xx_io_desc
));
293 _omap2_map_common_io();
298 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
300 * Sets the CORE DPLL3 M2 divider to the same value that it's at
301 * currently. This has the effect of setting the SDRC SDRAM AC timing
302 * registers to the values currently defined by the kernel. Currently
303 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
304 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
305 * or passes along the return value of clk_set_rate().
307 static int __init
_omap2_init_reprogram_sdrc(void)
309 struct clk
*dpll3_m2_ck
;
313 if (!cpu_is_omap34xx())
316 dpll3_m2_ck
= clk_get(NULL
, "dpll3_m2_ck");
317 if (IS_ERR(dpll3_m2_ck
))
320 rate
= clk_get_rate(dpll3_m2_ck
);
321 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate
);
322 v
= clk_set_rate(dpll3_m2_ck
, rate
);
324 pr_err("dpll3_m2_clk rate change failed: %d\n", v
);
326 clk_put(dpll3_m2_ck
);
331 static int _set_hwmod_postsetup_state(struct omap_hwmod
*oh
, void *data
)
333 return omap_hwmod_set_postsetup_state(oh
, *(u8
*)data
);
336 /* See irq.c, omap4-common.c and entry-macro.S */
337 void __iomem
*omap_irq_base
;
339 void __init
omap2_init_common_infrastructure(void)
343 if (cpu_is_omap242x()) {
344 omap2xxx_powerdomains_init();
345 omap2xxx_clockdomains_init();
346 omap2420_hwmod_init();
347 } else if (cpu_is_omap243x()) {
348 omap2xxx_powerdomains_init();
349 omap2xxx_clockdomains_init();
350 omap2430_hwmod_init();
351 } else if (cpu_is_omap34xx()) {
352 omap3xxx_powerdomains_init();
353 omap3xxx_clockdomains_init();
354 omap3xxx_hwmod_init();
355 } else if (cpu_is_omap44xx()) {
356 omap44xx_powerdomains_init();
357 omap44xx_clockdomains_init();
358 omap44xx_hwmod_init();
360 pr_err("Could not init hwmod data - unknown SoC\n");
363 /* Set the default postsetup state for all hwmods */
364 #ifdef CONFIG_PM_RUNTIME
365 postsetup_state
= _HWMOD_STATE_IDLE
;
367 postsetup_state
= _HWMOD_STATE_ENABLED
;
369 omap_hwmod_for_each(_set_hwmod_postsetup_state
, &postsetup_state
);
372 * Set the default postsetup state for unusual modules (like
375 * The postsetup_state is not actually used until
376 * omap_hwmod_late_init(), so boards that desire full watchdog
377 * coverage of kernel initialization can reprogram the
378 * postsetup_state between the calls to
379 * omap2_init_common_infra() and omap_sdrc_init().
381 * XXX ideally we could detect whether the MPU WDT was currently
382 * enabled here and make this conditional
384 postsetup_state
= _HWMOD_STATE_DISABLED
;
385 omap_hwmod_for_each_by_class("wd_timer",
386 _set_hwmod_postsetup_state
,
389 omap_pm_if_early_init();
391 if (cpu_is_omap2420())
393 else if (cpu_is_omap2430())
395 else if (cpu_is_omap34xx())
397 else if (cpu_is_omap44xx())
400 pr_err("Could not init clock framework - unknown SoC\n");
403 void __init
omap_sdrc_init(struct omap_sdrc_params
*sdrc_cs0
,
404 struct omap_sdrc_params
*sdrc_cs1
)
406 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
407 omap2_sdrc_init(sdrc_cs0
, sdrc_cs1
);
408 _omap2_init_reprogram_sdrc();
414 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
417 u8
omap_readb(u32 pa
)
419 return __raw_readb(OMAP2_L4_IO_ADDRESS(pa
));
421 EXPORT_SYMBOL(omap_readb
);
423 u16
omap_readw(u32 pa
)
425 return __raw_readw(OMAP2_L4_IO_ADDRESS(pa
));
427 EXPORT_SYMBOL(omap_readw
);
429 u32
omap_readl(u32 pa
)
431 return __raw_readl(OMAP2_L4_IO_ADDRESS(pa
));
433 EXPORT_SYMBOL(omap_readl
);
435 void omap_writeb(u8 v
, u32 pa
)
437 __raw_writeb(v
, OMAP2_L4_IO_ADDRESS(pa
));
439 EXPORT_SYMBOL(omap_writeb
);
441 void omap_writew(u16 v
, u32 pa
)
443 __raw_writew(v
, OMAP2_L4_IO_ADDRESS(pa
));
445 EXPORT_SYMBOL(omap_writew
);
447 void omap_writel(u32 v
, u32 pa
)
449 __raw_writel(v
, OMAP2_L4_IO_ADDRESS(pa
));
451 EXPORT_SYMBOL(omap_writel
);