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1 /*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
12 *
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
24
25 #include <asm/tlb.h>
26 #include <asm/mach/map.h>
27
28 #include <plat/sram.h>
29 #include <plat/sdrc.h>
30 #include <plat/serial.h>
31 #include <plat/omap-pm.h>
32 #include <plat/omap_hwmod.h>
33 #include <plat/multi.h>
34 #include <plat/dma.h>
35
36 #include "iomap.h"
37 #include "voltage.h"
38 #include "powerdomain.h"
39 #include "clockdomain.h"
40 #include "common.h"
41 #include "clock2xxx.h"
42 #include "clock3xxx.h"
43 #include "clock44xx.h"
44
45 /*
46 * The machine specific code may provide the extra mapping besides the
47 * default mapping provided here.
48 */
49
50 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
51 static struct map_desc omap24xx_io_desc[] __initdata = {
52 {
53 .virtual = L3_24XX_VIRT,
54 .pfn = __phys_to_pfn(L3_24XX_PHYS),
55 .length = L3_24XX_SIZE,
56 .type = MT_DEVICE
57 },
58 {
59 .virtual = L4_24XX_VIRT,
60 .pfn = __phys_to_pfn(L4_24XX_PHYS),
61 .length = L4_24XX_SIZE,
62 .type = MT_DEVICE
63 },
64 };
65
66 #ifdef CONFIG_SOC_OMAP2420
67 static struct map_desc omap242x_io_desc[] __initdata = {
68 {
69 .virtual = DSP_MEM_2420_VIRT,
70 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
71 .length = DSP_MEM_2420_SIZE,
72 .type = MT_DEVICE
73 },
74 {
75 .virtual = DSP_IPI_2420_VIRT,
76 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
77 .length = DSP_IPI_2420_SIZE,
78 .type = MT_DEVICE
79 },
80 {
81 .virtual = DSP_MMU_2420_VIRT,
82 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
83 .length = DSP_MMU_2420_SIZE,
84 .type = MT_DEVICE
85 },
86 };
87
88 #endif
89
90 #ifdef CONFIG_SOC_OMAP2430
91 static struct map_desc omap243x_io_desc[] __initdata = {
92 {
93 .virtual = L4_WK_243X_VIRT,
94 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
95 .length = L4_WK_243X_SIZE,
96 .type = MT_DEVICE
97 },
98 {
99 .virtual = OMAP243X_GPMC_VIRT,
100 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
101 .length = OMAP243X_GPMC_SIZE,
102 .type = MT_DEVICE
103 },
104 {
105 .virtual = OMAP243X_SDRC_VIRT,
106 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
107 .length = OMAP243X_SDRC_SIZE,
108 .type = MT_DEVICE
109 },
110 {
111 .virtual = OMAP243X_SMS_VIRT,
112 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
113 .length = OMAP243X_SMS_SIZE,
114 .type = MT_DEVICE
115 },
116 };
117 #endif
118 #endif
119
120 #ifdef CONFIG_ARCH_OMAP3
121 static struct map_desc omap34xx_io_desc[] __initdata = {
122 {
123 .virtual = L3_34XX_VIRT,
124 .pfn = __phys_to_pfn(L3_34XX_PHYS),
125 .length = L3_34XX_SIZE,
126 .type = MT_DEVICE
127 },
128 {
129 .virtual = L4_34XX_VIRT,
130 .pfn = __phys_to_pfn(L4_34XX_PHYS),
131 .length = L4_34XX_SIZE,
132 .type = MT_DEVICE
133 },
134 {
135 .virtual = OMAP34XX_GPMC_VIRT,
136 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
137 .length = OMAP34XX_GPMC_SIZE,
138 .type = MT_DEVICE
139 },
140 {
141 .virtual = OMAP343X_SMS_VIRT,
142 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
143 .length = OMAP343X_SMS_SIZE,
144 .type = MT_DEVICE
145 },
146 {
147 .virtual = OMAP343X_SDRC_VIRT,
148 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
149 .length = OMAP343X_SDRC_SIZE,
150 .type = MT_DEVICE
151 },
152 {
153 .virtual = L4_PER_34XX_VIRT,
154 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
155 .length = L4_PER_34XX_SIZE,
156 .type = MT_DEVICE
157 },
158 {
159 .virtual = L4_EMU_34XX_VIRT,
160 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
161 .length = L4_EMU_34XX_SIZE,
162 .type = MT_DEVICE
163 },
164 #if defined(CONFIG_DEBUG_LL) && \
165 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
166 {
167 .virtual = ZOOM_UART_VIRT,
168 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
169 .length = SZ_1M,
170 .type = MT_DEVICE
171 },
172 #endif
173 };
174 #endif
175
176 #ifdef CONFIG_SOC_TI81XX
177 static struct map_desc omapti81xx_io_desc[] __initdata = {
178 {
179 .virtual = L4_34XX_VIRT,
180 .pfn = __phys_to_pfn(L4_34XX_PHYS),
181 .length = L4_34XX_SIZE,
182 .type = MT_DEVICE
183 }
184 };
185 #endif
186
187 #ifdef CONFIG_SOC_AM33XX
188 static struct map_desc omapam33xx_io_desc[] __initdata = {
189 {
190 .virtual = L4_34XX_VIRT,
191 .pfn = __phys_to_pfn(L4_34XX_PHYS),
192 .length = L4_34XX_SIZE,
193 .type = MT_DEVICE
194 },
195 {
196 .virtual = L4_WK_AM33XX_VIRT,
197 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
198 .length = L4_WK_AM33XX_SIZE,
199 .type = MT_DEVICE
200 }
201 };
202 #endif
203
204 #ifdef CONFIG_ARCH_OMAP4
205 static struct map_desc omap44xx_io_desc[] __initdata = {
206 {
207 .virtual = L3_44XX_VIRT,
208 .pfn = __phys_to_pfn(L3_44XX_PHYS),
209 .length = L3_44XX_SIZE,
210 .type = MT_DEVICE,
211 },
212 {
213 .virtual = L4_44XX_VIRT,
214 .pfn = __phys_to_pfn(L4_44XX_PHYS),
215 .length = L4_44XX_SIZE,
216 .type = MT_DEVICE,
217 },
218 {
219 .virtual = L4_PER_44XX_VIRT,
220 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
221 .length = L4_PER_44XX_SIZE,
222 .type = MT_DEVICE,
223 },
224 #ifdef CONFIG_OMAP4_ERRATA_I688
225 {
226 .virtual = OMAP4_SRAM_VA,
227 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
228 .length = PAGE_SIZE,
229 .type = MT_MEMORY_SO,
230 },
231 #endif
232
233 };
234 #endif
235
236 #ifdef CONFIG_SOC_OMAP2420
237 void __init omap242x_map_common_io(void)
238 {
239 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
240 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
241 }
242 #endif
243
244 #ifdef CONFIG_SOC_OMAP2430
245 void __init omap243x_map_common_io(void)
246 {
247 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
248 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
249 }
250 #endif
251
252 #ifdef CONFIG_ARCH_OMAP3
253 void __init omap34xx_map_common_io(void)
254 {
255 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
256 }
257 #endif
258
259 #ifdef CONFIG_SOC_TI81XX
260 void __init omapti81xx_map_common_io(void)
261 {
262 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
263 }
264 #endif
265
266 #ifdef CONFIG_SOC_AM33XX
267 void __init omapam33xx_map_common_io(void)
268 {
269 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
270 }
271 #endif
272
273 #ifdef CONFIG_ARCH_OMAP4
274 void __init omap44xx_map_common_io(void)
275 {
276 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
277 omap_barriers_init();
278 }
279 #endif
280
281 /*
282 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
283 *
284 * Sets the CORE DPLL3 M2 divider to the same value that it's at
285 * currently. This has the effect of setting the SDRC SDRAM AC timing
286 * registers to the values currently defined by the kernel. Currently
287 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
288 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
289 * or passes along the return value of clk_set_rate().
290 */
291 static int __init _omap2_init_reprogram_sdrc(void)
292 {
293 struct clk *dpll3_m2_ck;
294 int v = -EINVAL;
295 long rate;
296
297 if (!cpu_is_omap34xx())
298 return 0;
299
300 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
301 if (IS_ERR(dpll3_m2_ck))
302 return -EINVAL;
303
304 rate = clk_get_rate(dpll3_m2_ck);
305 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
306 v = clk_set_rate(dpll3_m2_ck, rate);
307 if (v)
308 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
309
310 clk_put(dpll3_m2_ck);
311
312 return v;
313 }
314
315 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
316 {
317 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
318 }
319
320 static void __init omap_common_init_early(void)
321 {
322 omap_init_consistent_dma_size();
323 }
324
325 static void __init omap_hwmod_init_postsetup(void)
326 {
327 u8 postsetup_state;
328
329 /* Set the default postsetup state for all hwmods */
330 #ifdef CONFIG_PM_RUNTIME
331 postsetup_state = _HWMOD_STATE_IDLE;
332 #else
333 postsetup_state = _HWMOD_STATE_ENABLED;
334 #endif
335 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
336
337 omap_pm_if_early_init();
338 }
339
340 #ifdef CONFIG_SOC_OMAP2420
341 void __init omap2420_init_early(void)
342 {
343 omap2_set_globals_242x();
344 omap2xxx_check_revision();
345 omap_common_init_early();
346 omap2xxx_voltagedomains_init();
347 omap242x_powerdomains_init();
348 omap242x_clockdomains_init();
349 omap2420_hwmod_init();
350 omap_hwmod_init_postsetup();
351 omap2420_clk_init();
352 }
353 #endif
354
355 #ifdef CONFIG_SOC_OMAP2430
356 void __init omap2430_init_early(void)
357 {
358 omap2_set_globals_243x();
359 omap2xxx_check_revision();
360 omap_common_init_early();
361 omap2xxx_voltagedomains_init();
362 omap243x_powerdomains_init();
363 omap243x_clockdomains_init();
364 omap2430_hwmod_init();
365 omap_hwmod_init_postsetup();
366 omap2430_clk_init();
367 }
368 #endif
369
370 /*
371 * Currently only board-omap3beagle.c should call this because of the
372 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
373 */
374 #ifdef CONFIG_ARCH_OMAP3
375 void __init omap3_init_early(void)
376 {
377 omap2_set_globals_3xxx();
378 omap3xxx_check_revision();
379 omap3xxx_check_features();
380 omap_common_init_early();
381 omap3xxx_voltagedomains_init();
382 omap3xxx_powerdomains_init();
383 omap3xxx_clockdomains_init();
384 omap3xxx_hwmod_init();
385 omap_hwmod_init_postsetup();
386 omap3xxx_clk_init();
387 }
388
389 void __init omap3430_init_early(void)
390 {
391 omap3_init_early();
392 }
393
394 void __init omap35xx_init_early(void)
395 {
396 omap3_init_early();
397 }
398
399 void __init omap3630_init_early(void)
400 {
401 omap3_init_early();
402 }
403
404 void __init am35xx_init_early(void)
405 {
406 omap3_init_early();
407 }
408
409 void __init ti81xx_init_early(void)
410 {
411 omap2_set_globals_ti81xx();
412 omap3xxx_check_revision();
413 ti81xx_check_features();
414 omap_common_init_early();
415 omap3xxx_voltagedomains_init();
416 omap3xxx_powerdomains_init();
417 omap3xxx_clockdomains_init();
418 omap3xxx_hwmod_init();
419 omap_hwmod_init_postsetup();
420 omap3xxx_clk_init();
421 }
422 #endif
423
424 #ifdef CONFIG_ARCH_OMAP4
425 void __init omap4430_init_early(void)
426 {
427 omap2_set_globals_443x();
428 omap4xxx_check_revision();
429 omap4xxx_check_features();
430 omap_common_init_early();
431 omap44xx_voltagedomains_init();
432 omap44xx_powerdomains_init();
433 omap44xx_clockdomains_init();
434 omap44xx_hwmod_init();
435 omap_hwmod_init_postsetup();
436 omap4xxx_clk_init();
437 }
438 #endif
439
440 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
441 struct omap_sdrc_params *sdrc_cs1)
442 {
443 omap_sram_init();
444
445 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
446 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
447 _omap2_init_reprogram_sdrc();
448 }
449 }