2 * linux/arch/arm/mach-omap2/io.c
4 * OMAP2 I/O mapping code
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
23 #include <linux/clk.h>
26 #include <asm/mach/map.h>
28 #include <linux/omap-dma.h>
30 #include "omap_hwmod.h"
34 #include "powerdomain.h"
35 #include "clockdomain.h"
38 #include "clock2xxx.h"
39 #include "clock3xxx.h"
50 #include "prcm_mpu44xx.h"
51 #include "prminst44xx.h"
59 * omap_clk_soc_init: points to a function that does the SoC-specific
60 * clock initializations
62 static int (*omap_clk_soc_init
)(void);
65 * The machine specific code may provide the extra mapping besides the
66 * default mapping provided here.
69 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
70 static struct map_desc omap24xx_io_desc
[] __initdata
= {
72 .virtual = L3_24XX_VIRT
,
73 .pfn
= __phys_to_pfn(L3_24XX_PHYS
),
74 .length
= L3_24XX_SIZE
,
78 .virtual = L4_24XX_VIRT
,
79 .pfn
= __phys_to_pfn(L4_24XX_PHYS
),
80 .length
= L4_24XX_SIZE
,
85 #ifdef CONFIG_SOC_OMAP2420
86 static struct map_desc omap242x_io_desc
[] __initdata
= {
88 .virtual = DSP_MEM_2420_VIRT
,
89 .pfn
= __phys_to_pfn(DSP_MEM_2420_PHYS
),
90 .length
= DSP_MEM_2420_SIZE
,
94 .virtual = DSP_IPI_2420_VIRT
,
95 .pfn
= __phys_to_pfn(DSP_IPI_2420_PHYS
),
96 .length
= DSP_IPI_2420_SIZE
,
100 .virtual = DSP_MMU_2420_VIRT
,
101 .pfn
= __phys_to_pfn(DSP_MMU_2420_PHYS
),
102 .length
= DSP_MMU_2420_SIZE
,
109 #ifdef CONFIG_SOC_OMAP2430
110 static struct map_desc omap243x_io_desc
[] __initdata
= {
112 .virtual = L4_WK_243X_VIRT
,
113 .pfn
= __phys_to_pfn(L4_WK_243X_PHYS
),
114 .length
= L4_WK_243X_SIZE
,
118 .virtual = OMAP243X_GPMC_VIRT
,
119 .pfn
= __phys_to_pfn(OMAP243X_GPMC_PHYS
),
120 .length
= OMAP243X_GPMC_SIZE
,
124 .virtual = OMAP243X_SDRC_VIRT
,
125 .pfn
= __phys_to_pfn(OMAP243X_SDRC_PHYS
),
126 .length
= OMAP243X_SDRC_SIZE
,
130 .virtual = OMAP243X_SMS_VIRT
,
131 .pfn
= __phys_to_pfn(OMAP243X_SMS_PHYS
),
132 .length
= OMAP243X_SMS_SIZE
,
139 #ifdef CONFIG_ARCH_OMAP3
140 static struct map_desc omap34xx_io_desc
[] __initdata
= {
142 .virtual = L3_34XX_VIRT
,
143 .pfn
= __phys_to_pfn(L3_34XX_PHYS
),
144 .length
= L3_34XX_SIZE
,
148 .virtual = L4_34XX_VIRT
,
149 .pfn
= __phys_to_pfn(L4_34XX_PHYS
),
150 .length
= L4_34XX_SIZE
,
154 .virtual = OMAP34XX_GPMC_VIRT
,
155 .pfn
= __phys_to_pfn(OMAP34XX_GPMC_PHYS
),
156 .length
= OMAP34XX_GPMC_SIZE
,
160 .virtual = OMAP343X_SMS_VIRT
,
161 .pfn
= __phys_to_pfn(OMAP343X_SMS_PHYS
),
162 .length
= OMAP343X_SMS_SIZE
,
166 .virtual = OMAP343X_SDRC_VIRT
,
167 .pfn
= __phys_to_pfn(OMAP343X_SDRC_PHYS
),
168 .length
= OMAP343X_SDRC_SIZE
,
172 .virtual = L4_PER_34XX_VIRT
,
173 .pfn
= __phys_to_pfn(L4_PER_34XX_PHYS
),
174 .length
= L4_PER_34XX_SIZE
,
178 .virtual = L4_EMU_34XX_VIRT
,
179 .pfn
= __phys_to_pfn(L4_EMU_34XX_PHYS
),
180 .length
= L4_EMU_34XX_SIZE
,
186 #ifdef CONFIG_SOC_TI81XX
187 static struct map_desc omapti81xx_io_desc
[] __initdata
= {
189 .virtual = L4_34XX_VIRT
,
190 .pfn
= __phys_to_pfn(L4_34XX_PHYS
),
191 .length
= L4_34XX_SIZE
,
197 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
198 static struct map_desc omapam33xx_io_desc
[] __initdata
= {
200 .virtual = L4_34XX_VIRT
,
201 .pfn
= __phys_to_pfn(L4_34XX_PHYS
),
202 .length
= L4_34XX_SIZE
,
206 .virtual = L4_WK_AM33XX_VIRT
,
207 .pfn
= __phys_to_pfn(L4_WK_AM33XX_PHYS
),
208 .length
= L4_WK_AM33XX_SIZE
,
214 #ifdef CONFIG_ARCH_OMAP4
215 static struct map_desc omap44xx_io_desc
[] __initdata
= {
217 .virtual = L3_44XX_VIRT
,
218 .pfn
= __phys_to_pfn(L3_44XX_PHYS
),
219 .length
= L3_44XX_SIZE
,
223 .virtual = L4_44XX_VIRT
,
224 .pfn
= __phys_to_pfn(L4_44XX_PHYS
),
225 .length
= L4_44XX_SIZE
,
229 .virtual = L4_PER_44XX_VIRT
,
230 .pfn
= __phys_to_pfn(L4_PER_44XX_PHYS
),
231 .length
= L4_PER_44XX_SIZE
,
237 #ifdef CONFIG_SOC_OMAP5
238 static struct map_desc omap54xx_io_desc
[] __initdata
= {
240 .virtual = L3_54XX_VIRT
,
241 .pfn
= __phys_to_pfn(L3_54XX_PHYS
),
242 .length
= L3_54XX_SIZE
,
246 .virtual = L4_54XX_VIRT
,
247 .pfn
= __phys_to_pfn(L4_54XX_PHYS
),
248 .length
= L4_54XX_SIZE
,
252 .virtual = L4_WK_54XX_VIRT
,
253 .pfn
= __phys_to_pfn(L4_WK_54XX_PHYS
),
254 .length
= L4_WK_54XX_SIZE
,
258 .virtual = L4_PER_54XX_VIRT
,
259 .pfn
= __phys_to_pfn(L4_PER_54XX_PHYS
),
260 .length
= L4_PER_54XX_SIZE
,
266 #ifdef CONFIG_SOC_DRA7XX
267 static struct map_desc dra7xx_io_desc
[] __initdata
= {
269 .virtual = L4_CFG_MPU_DRA7XX_VIRT
,
270 .pfn
= __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS
),
271 .length
= L4_CFG_MPU_DRA7XX_SIZE
,
275 .virtual = L3_MAIN_SN_DRA7XX_VIRT
,
276 .pfn
= __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS
),
277 .length
= L3_MAIN_SN_DRA7XX_SIZE
,
281 .virtual = L4_PER1_DRA7XX_VIRT
,
282 .pfn
= __phys_to_pfn(L4_PER1_DRA7XX_PHYS
),
283 .length
= L4_PER1_DRA7XX_SIZE
,
287 .virtual = L4_PER2_DRA7XX_VIRT
,
288 .pfn
= __phys_to_pfn(L4_PER2_DRA7XX_PHYS
),
289 .length
= L4_PER2_DRA7XX_SIZE
,
293 .virtual = L4_PER3_DRA7XX_VIRT
,
294 .pfn
= __phys_to_pfn(L4_PER3_DRA7XX_PHYS
),
295 .length
= L4_PER3_DRA7XX_SIZE
,
299 .virtual = L4_CFG_DRA7XX_VIRT
,
300 .pfn
= __phys_to_pfn(L4_CFG_DRA7XX_PHYS
),
301 .length
= L4_CFG_DRA7XX_SIZE
,
305 .virtual = L4_WKUP_DRA7XX_VIRT
,
306 .pfn
= __phys_to_pfn(L4_WKUP_DRA7XX_PHYS
),
307 .length
= L4_WKUP_DRA7XX_SIZE
,
313 #ifdef CONFIG_SOC_OMAP2420
314 void __init
omap242x_map_io(void)
316 iotable_init(omap24xx_io_desc
, ARRAY_SIZE(omap24xx_io_desc
));
317 iotable_init(omap242x_io_desc
, ARRAY_SIZE(omap242x_io_desc
));
321 #ifdef CONFIG_SOC_OMAP2430
322 void __init
omap243x_map_io(void)
324 iotable_init(omap24xx_io_desc
, ARRAY_SIZE(omap24xx_io_desc
));
325 iotable_init(omap243x_io_desc
, ARRAY_SIZE(omap243x_io_desc
));
329 #ifdef CONFIG_ARCH_OMAP3
330 void __init
omap3_map_io(void)
332 iotable_init(omap34xx_io_desc
, ARRAY_SIZE(omap34xx_io_desc
));
336 #ifdef CONFIG_SOC_TI81XX
337 void __init
ti81xx_map_io(void)
339 iotable_init(omapti81xx_io_desc
, ARRAY_SIZE(omapti81xx_io_desc
));
343 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
344 void __init
am33xx_map_io(void)
346 iotable_init(omapam33xx_io_desc
, ARRAY_SIZE(omapam33xx_io_desc
));
350 #ifdef CONFIG_ARCH_OMAP4
351 void __init
omap4_map_io(void)
353 iotable_init(omap44xx_io_desc
, ARRAY_SIZE(omap44xx_io_desc
));
354 omap_barriers_init();
358 #ifdef CONFIG_SOC_OMAP5
359 void __init
omap5_map_io(void)
361 iotable_init(omap54xx_io_desc
, ARRAY_SIZE(omap54xx_io_desc
));
362 omap_barriers_init();
366 #ifdef CONFIG_SOC_DRA7XX
367 void __init
dra7xx_map_io(void)
369 iotable_init(dra7xx_io_desc
, ARRAY_SIZE(dra7xx_io_desc
));
370 omap_barriers_init();
374 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
376 * Sets the CORE DPLL3 M2 divider to the same value that it's at
377 * currently. This has the effect of setting the SDRC SDRAM AC timing
378 * registers to the values currently defined by the kernel. Currently
379 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
380 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
381 * or passes along the return value of clk_set_rate().
383 static int __init
_omap2_init_reprogram_sdrc(void)
385 struct clk
*dpll3_m2_ck
;
389 if (!cpu_is_omap34xx())
392 dpll3_m2_ck
= clk_get(NULL
, "dpll3_m2_ck");
393 if (IS_ERR(dpll3_m2_ck
))
396 rate
= clk_get_rate(dpll3_m2_ck
);
397 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate
);
398 v
= clk_set_rate(dpll3_m2_ck
, rate
);
400 pr_err("dpll3_m2_clk rate change failed: %d\n", v
);
402 clk_put(dpll3_m2_ck
);
407 static int _set_hwmod_postsetup_state(struct omap_hwmod
*oh
, void *data
)
409 return omap_hwmod_set_postsetup_state(oh
, *(u8
*)data
);
412 static void __init __maybe_unused
omap_hwmod_init_postsetup(void)
414 u8 postsetup_state
= _HWMOD_STATE_DEFAULT
;
416 /* Set the default postsetup state for all hwmods */
417 omap_hwmod_for_each(_set_hwmod_postsetup_state
, &postsetup_state
);
420 #ifdef CONFIG_SOC_OMAP2420
421 void __init
omap2420_init_early(void)
423 omap2_set_globals_tap(OMAP242X_CLASS
, OMAP2_L4_IO_ADDRESS(0x48014000));
424 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE
),
425 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE
));
426 omap2_control_base_init();
427 omap2xxx_check_revision();
428 omap2_prcm_base_init();
429 omap2xxx_voltagedomains_init();
430 omap242x_powerdomains_init();
431 omap242x_clockdomains_init();
432 omap2420_hwmod_init();
433 omap_hwmod_init_postsetup();
434 omap_clk_soc_init
= omap2420_dt_clk_init
;
435 rate_table
= omap2420_rate_table
;
438 void __init
omap2420_init_late(void)
440 omap_pm_soc_init
= omap2_pm_init
;
444 #ifdef CONFIG_SOC_OMAP2430
445 void __init
omap2430_init_early(void)
447 omap2_set_globals_tap(OMAP243X_CLASS
, OMAP2_L4_IO_ADDRESS(0x4900a000));
448 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE
),
449 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE
));
450 omap2_control_base_init();
451 omap2xxx_check_revision();
452 omap2_prcm_base_init();
453 omap2xxx_voltagedomains_init();
454 omap243x_powerdomains_init();
455 omap243x_clockdomains_init();
456 omap2430_hwmod_init();
457 omap_hwmod_init_postsetup();
458 omap_clk_soc_init
= omap2430_dt_clk_init
;
459 rate_table
= omap2430_rate_table
;
462 void __init
omap2430_init_late(void)
464 omap_pm_soc_init
= omap2_pm_init
;
469 * Currently only board-omap3beagle.c should call this because of the
470 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
472 #ifdef CONFIG_ARCH_OMAP3
473 void __init
omap3_init_early(void)
475 omap2_set_globals_tap(OMAP343X_CLASS
, OMAP2_L4_IO_ADDRESS(0x4830A000));
476 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE
),
477 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE
));
478 omap2_control_base_init();
479 omap3xxx_check_revision();
480 omap3xxx_check_features();
481 omap2_prcm_base_init();
482 omap3xxx_voltagedomains_init();
483 omap3xxx_powerdomains_init();
484 omap3xxx_clockdomains_init();
485 omap3xxx_hwmod_init();
486 omap_hwmod_init_postsetup();
489 void __init
omap3430_init_early(void)
492 omap_clk_soc_init
= omap3430_dt_clk_init
;
495 void __init
omap35xx_init_early(void)
498 omap_clk_soc_init
= omap3430_dt_clk_init
;
501 void __init
omap3630_init_early(void)
504 omap_clk_soc_init
= omap3630_dt_clk_init
;
507 void __init
am35xx_init_early(void)
510 omap_clk_soc_init
= am35xx_dt_clk_init
;
513 void __init
omap3_init_late(void)
515 omap_pm_soc_init
= omap3_pm_init
;
518 void __init
ti81xx_init_late(void)
520 omap_pm_soc_init
= omap_pm_nop_init
;
524 #ifdef CONFIG_SOC_TI81XX
525 void __init
ti814x_init_early(void)
527 omap2_set_globals_tap(TI814X_CLASS
,
528 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE
));
529 omap2_control_base_init();
530 omap3xxx_check_revision();
531 ti81xx_check_features();
532 omap2_prcm_base_init();
533 omap3xxx_voltagedomains_init();
534 omap3xxx_powerdomains_init();
535 ti814x_clockdomains_init();
537 omap_hwmod_init_postsetup();
538 omap_clk_soc_init
= dm814x_dt_clk_init
;
541 void __init
ti816x_init_early(void)
543 omap2_set_globals_tap(TI816X_CLASS
,
544 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE
));
545 omap2_control_base_init();
546 omap3xxx_check_revision();
547 ti81xx_check_features();
548 omap2_prcm_base_init();
549 omap3xxx_voltagedomains_init();
550 omap3xxx_powerdomains_init();
551 ti816x_clockdomains_init();
553 omap_hwmod_init_postsetup();
554 omap_clk_soc_init
= dm816x_dt_clk_init
;
558 #ifdef CONFIG_SOC_AM33XX
559 void __init
am33xx_init_early(void)
561 omap2_set_globals_tap(AM335X_CLASS
,
562 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE
));
563 omap2_control_base_init();
564 omap3xxx_check_revision();
565 am33xx_check_features();
566 omap2_prcm_base_init();
567 am33xx_powerdomains_init();
568 am33xx_clockdomains_init();
570 omap_hwmod_init_postsetup();
571 omap_clk_soc_init
= am33xx_dt_clk_init
;
574 void __init
am33xx_init_late(void)
576 omap_pm_soc_init
= amx3_common_pm_init
;
580 #ifdef CONFIG_SOC_AM43XX
581 void __init
am43xx_init_early(void)
583 omap2_set_globals_tap(AM335X_CLASS
,
584 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE
));
585 omap2_control_base_init();
586 omap3xxx_check_revision();
587 am33xx_check_features();
588 omap2_prcm_base_init();
589 am43xx_powerdomains_init();
590 am43xx_clockdomains_init();
592 omap_hwmod_init_postsetup();
593 omap_l2_cache_init();
594 omap_clk_soc_init
= am43xx_dt_clk_init
;
597 void __init
am43xx_init_late(void)
599 omap_pm_soc_init
= amx3_common_pm_init
;
603 #ifdef CONFIG_ARCH_OMAP4
604 void __init
omap4430_init_early(void)
606 omap2_set_globals_tap(OMAP443X_CLASS
,
607 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE
));
608 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE
));
609 omap2_control_base_init();
610 omap4xxx_check_revision();
611 omap4xxx_check_features();
612 omap2_prcm_base_init();
613 omap4_sar_ram_init();
614 omap4_mpuss_early_init();
615 omap4_pm_init_early();
616 omap44xx_voltagedomains_init();
617 omap44xx_powerdomains_init();
618 omap44xx_clockdomains_init();
619 omap44xx_hwmod_init();
620 omap_hwmod_init_postsetup();
621 omap_l2_cache_init();
622 omap_clk_soc_init
= omap4xxx_dt_clk_init
;
625 void __init
omap4430_init_late(void)
627 omap_pm_soc_init
= omap4_pm_init
;
631 #ifdef CONFIG_SOC_OMAP5
632 void __init
omap5_init_early(void)
634 omap2_set_globals_tap(OMAP54XX_CLASS
,
635 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE
));
636 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE
));
637 omap2_control_base_init();
638 omap2_prcm_base_init();
639 omap5xxx_check_revision();
640 omap4_sar_ram_init();
641 omap4_mpuss_early_init();
642 omap4_pm_init_early();
643 omap54xx_voltagedomains_init();
644 omap54xx_powerdomains_init();
645 omap54xx_clockdomains_init();
646 omap54xx_hwmod_init();
647 omap_hwmod_init_postsetup();
648 omap_clk_soc_init
= omap5xxx_dt_clk_init
;
651 void __init
omap5_init_late(void)
653 omap_pm_soc_init
= omap4_pm_init
;
657 #ifdef CONFIG_SOC_DRA7XX
658 void __init
dra7xx_init_early(void)
660 omap2_set_globals_tap(DRA7XX_CLASS
,
661 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE
));
662 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE
));
663 omap2_control_base_init();
664 omap4_pm_init_early();
665 omap2_prcm_base_init();
666 dra7xxx_check_revision();
667 dra7xx_powerdomains_init();
668 dra7xx_clockdomains_init();
670 omap_hwmod_init_postsetup();
671 omap_clk_soc_init
= dra7xx_dt_clk_init
;
674 void __init
dra7xx_init_late(void)
676 omap_pm_soc_init
= omap4_pm_init
;
681 void __init
omap_sdrc_init(struct omap_sdrc_params
*sdrc_cs0
,
682 struct omap_sdrc_params
*sdrc_cs1
)
686 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
687 omap2_sdrc_init(sdrc_cs0
, sdrc_cs1
);
688 _omap2_init_reprogram_sdrc();
692 int __init
omap_clk_init(void)
696 if (!omap_clk_soc_init
)
699 ti_clk_init_features();
701 omap2_clk_setup_ll_ops();
703 ret
= omap_control_init();
707 ret
= omap_prcm_init();
713 ti_dt_clk_init_retry_clks();
715 ti_dt_clockdomains_setup();
717 ret
= omap_clk_soc_init();