arch/arm/mach-omap2/omap-headsmp.S

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Secondary CPU startup routine source file.
   4  *
   5  * Copyright (C) 2009-2014 Texas Instruments, Inc.
   6  *
   7  * Author:
   8  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   9  *
  10  * Interface functions needed for the SMP. This file is based on arm
  11  * realview smp platform.
  12  * Copyright (c) 2003 ARM Limited.
  13  */
  14
  15 #include <linux/linkage.h>
  16 #include <linux/init.h>
  17 #include <asm/assembler.h>
  18
  19 #include "omap44xx.h"
  20
  21 /* Physical address needed since MMU not enabled yet on secondary core */
  22 #define AUX_CORE_BOOT0_PA                       0x48281800
  23 #define API_HYP_ENTRY                           0x102
  24
  25 ENTRY(omap_secondary_startup)
  26 #ifdef CONFIG_SMP
  27         b       secondary_startup
  28 #else
  29 /* Should never get here */
  30 again:  wfi
  31         b       again
  32 #endif
  33 #ENDPROC(omap_secondary_startup)
  34
  35 /*
  36  * OMAP5 specific entry point for secondary CPU to jump from ROM
  37  * code.  This routine also provides a holding flag into which
  38  * secondary core is held until we're ready for it to initialise.
  39  * The primary core will update this flag using a hardware
  40  * register AuxCoreBoot0.
  41  */
  42 ENTRY(omap5_secondary_startup)
  43 wait:   ldr     r2, =AUX_CORE_BOOT0_PA  @ read from AuxCoreBoot0
  44         ldr     r0, [r2]
  45         mov     r0, r0, lsr #5
  46         mrc     p15, 0, r4, c0, c0, 5
  47         and     r4, r4, #0x0f
  48         cmp     r0, r4
  49         bne     wait
  50         b       omap_secondary_startup
  51 ENDPROC(omap5_secondary_startup)
  52 /*
  53  * Same as omap5_secondary_startup except we call into the ROM to
  54  * enable HYP mode first.  This is called instead of
  55  * omap5_secondary_startup if the primary CPU was put into HYP mode by
  56  * the boot loader.
  57  */
  58 ENTRY(omap5_secondary_hyp_startup)
  59 wait_2: ldr     r2, =AUX_CORE_BOOT0_PA  @ read from AuxCoreBoot0
  60         ldr     r0, [r2]
  61         mov     r0, r0, lsr #5
  62         mrc     p15, 0, r4, c0, c0, 5
  63         and     r4, r4, #0x0f
  64         cmp     r0, r4
  65         bne     wait_2
  66         ldr     r12, =API_HYP_ENTRY
  67         badr    r0, hyp_boot
  68         smc     #0
  69 hyp_boot:
  70         b       omap_secondary_startup
  71 ENDPROC(omap5_secondary_hyp_startup)
  72 /*
  73  * OMAP4 specific entry point for secondary CPU to jump from ROM
  74  * code.  This routine also provides a holding flag into which
  75  * secondary core is held until we're ready for it to initialise.
  76  * The primary core will update this flag using a hardware
  77  * register AuxCoreBoot0.
  78  */
  79 ENTRY(omap4_secondary_startup)
  80 hold:   ldr     r12,=0x103
  81         dsb
  82         smc     #0                      @ read from AuxCoreBoot0
  83         mov     r0, r0, lsr #9
  84         mrc     p15, 0, r4, c0, c0, 5
  85         and     r4, r4, #0x0f
  86         cmp     r0, r4
  87         bne     hold
  88
  89         /*
  90          * we've been released from the wait loop,secondary_stack
  91          * should now contain the SVC stack for this core
  92          */
  93         b       omap_secondary_startup
  94 ENDPROC(omap4_secondary_startup)
  95
  96 ENTRY(omap4460_secondary_startup)
  97 hold_2: ldr     r12,=0x103
  98         dsb
  99         smc     #0                      @ read from AuxCoreBoot0
 100         mov     r0, r0, lsr #9
 101         mrc     p15, 0, r4, c0, c0, 5
 102         and     r4, r4, #0x0f
 103         cmp     r0, r4
 104         bne     hold_2
 105
 106         /*
 107          * GIC distributor control register has changed between
 108          * CortexA9 r1pX and r2pX. The Control Register secure
 109          * banked version is now composed of 2 bits:
 110          * bit 0 == Secure Enable
 111          * bit 1 == Non-Secure Enable
 112          * The Non-Secure banked register has not changed
 113          * Because the ROM Code is based on the r1pX GIC, the CPU1
 114          * GIC restoration will cause a problem to CPU0 Non-Secure SW.
 115          * The workaround must be:
 116          * 1) Before doing the CPU1 wakeup, CPU0 must disable
 117          * the GIC distributor
 118          * 2) CPU1 must re-enable the GIC distributor on
 119          * it's wakeup path.
 120          */
 121         ldr     r1, =OMAP44XX_GIC_DIST_BASE
 122         ldr     r0, [r1]
 123         orr     r0, #1
 124         str     r0, [r1]
 125
 126         /*
 127          * we've been released from the wait loop,secondary_stack
 128          * should now contain the SVC stack for this core
 129          */
 130         b       omap_secondary_startup
 131 ENDPROC(omap4460_secondary_startup)