arch/arm/mach-omap2/omap-mpuss-lowpower.c

   1 /*
   2  * OMAP MPUSS low power code
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   6  *
   7  * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
   8  * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
   9  * CPU0 and CPU1 LPRM modules.
  10  * CPU0, CPU1 and MPUSS each have there own power domain and
  11  * hence multiple low power combinations of MPUSS are possible.
  12  *
  13  * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
  14  * because the mode is not supported by hw constraints of dormant
  15  * mode. While waking up from the dormant mode, a reset  signal
  16  * to the Cortex-A9 processor must be asserted by the external
  17  * power controller.
  18  *
  19  * With architectural inputs and hardware recommendations, only
  20  * below modes are supported from power gain vs latency point of view.
  21  *
  22  *      CPU0            CPU1            MPUSS
  23  *      ----------------------------------------------
  24  *      ON              ON              ON
  25  *      ON(Inactive)    OFF             ON(Inactive)
  26  *      OFF             OFF             CSWR
  27  *      OFF             OFF             OSWR
  28  *      OFF             OFF             OFF(Device OFF *TBD)
  29  *      ----------------------------------------------
  30  *
  31  * Note: CPU0 is the master core and it is the last CPU to go down
  32  * and first to wake-up when MPUSS low power states are excercised
  33  *
  34  *
  35  * This program is free software; you can redistribute it and/or modify
  36  * it under the terms of the GNU General Public License version 2 as
  37  * published by the Free Software Foundation.
  38  */
  39
  40 #include <linux/kernel.h>
  41 #include <linux/io.h>
  42 #include <linux/errno.h>
  43 #include <linux/linkage.h>
  44 #include <linux/smp.h>
  45
  46 #include <asm/cacheflush.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/smp_scu.h>
  49 #include <asm/pgalloc.h>
  50 #include <asm/suspend.h>
  51 #include <asm/hardware/cache-l2x0.h>
  52
  53 #include "soc.h"
  54 #include "common.h"
  55 #include "omap44xx.h"
  56 #include "omap4-sar-layout.h"
  57 #include "pm.h"
  58 #include "prcm_mpu44xx.h"
  59 #include "prcm_mpu54xx.h"
  60 #include "prminst44xx.h"
  61 #include "prcm44xx.h"
  62 #include "prm44xx.h"
  63 #include "prm-regbits-44xx.h"
  64
  65 static void __iomem *sar_base;
  66
  67 #if defined(CONFIG_PM) && defined(CONFIG_SMP)
  68
  69 struct omap4_cpu_pm_info {
  70         struct powerdomain *pwrdm;
  71         void __iomem *scu_sar_addr;
  72         void __iomem *wkup_sar_addr;
  73         void __iomem *l2x0_sar_addr;
  74 };
  75
  76 /**
  77  * struct cpu_pm_ops - CPU pm operations
  78  * @finish_suspend:     CPU suspend finisher function pointer
  79  * @resume:             CPU resume function pointer
  80  * @scu_prepare:        CPU Snoop Control program function pointer
  81  * @hotplug_restart:    CPU restart function pointer
  82  *
  83  * Structure holds functions pointer for CPU low power operations like
  84  * suspend, resume and scu programming.
  85  */
  86 struct cpu_pm_ops {
  87         int (*finish_suspend)(unsigned long cpu_state);
  88         void (*resume)(void);
  89         void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
  90         void (*hotplug_restart)(void);
  91 };
  92
  93 static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
  94 static struct powerdomain *mpuss_pd;
  95 static u32 cpu_context_offset;
  96
  97 static int default_finish_suspend(unsigned long cpu_state)
  98 {
  99         omap_do_wfi();
 100         return 0;
 101 }
 102
 103 static void dummy_cpu_resume(void)
 104 {}
 105
 106 static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
 107 {}
 108
 109 static struct cpu_pm_ops omap_pm_ops = {
 110         .finish_suspend         = default_finish_suspend,
 111         .resume                 = dummy_cpu_resume,
 112         .scu_prepare            = dummy_scu_prepare,
 113         .hotplug_restart        = dummy_cpu_resume,
 114 };
 115
 116 /*
 117  * Program the wakeup routine address for the CPU0 and CPU1
 118  * used for OFF or DORMANT wakeup.
 119  */
 120 static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
 121 {
 122         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 123
 124         if (pm_info->wkup_sar_addr)
 125                 writel_relaxed(addr, pm_info->wkup_sar_addr);
 126 }
 127
 128 /*
 129  * Store the SCU power status value to scratchpad memory
 130  */
 131 static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
 132 {
 133         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 134         u32 scu_pwr_st;
 135
 136         switch (cpu_state) {
 137         case PWRDM_POWER_RET:
 138                 scu_pwr_st = SCU_PM_DORMANT;
 139                 break;
 140         case PWRDM_POWER_OFF:
 141                 scu_pwr_st = SCU_PM_POWEROFF;
 142                 break;
 143         case PWRDM_POWER_ON:
 144         case PWRDM_POWER_INACTIVE:
 145         default:
 146                 scu_pwr_st = SCU_PM_NORMAL;
 147                 break;
 148         }
 149
 150         if (pm_info->scu_sar_addr)
 151                 writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
 152 }
 153
 154 /* Helper functions for MPUSS OSWR */
 155 static inline void mpuss_clear_prev_logic_pwrst(void)
 156 {
 157         u32 reg;
 158
 159         reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 160                 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
 161         omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
 162                 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
 163 }
 164
 165 static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
 166 {
 167         u32 reg;
 168
 169         if (cpu_id) {
 170                 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
 171                                         cpu_context_offset);
 172                 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
 173                                         cpu_context_offset);
 174         } else {
 175                 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
 176                                         cpu_context_offset);
 177                 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
 178                                         cpu_context_offset);
 179         }
 180 }
 181
 182 /*
 183  * Store the CPU cluster state for L2X0 low power operations.
 184  */
 185 static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
 186 {
 187         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 188
 189         if (pm_info->l2x0_sar_addr)
 190                 writel_relaxed(save_state, pm_info->l2x0_sar_addr);
 191 }
 192
 193 /*
 194  * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
 195  * in every restore MPUSS OFF path.
 196  */
 197 #ifdef CONFIG_CACHE_L2X0
 198 static void __init save_l2x0_context(void)
 199 {
 200         void __iomem *l2x0_base = omap4_get_l2cache_base();
 201
 202         if (l2x0_base && sar_base) {
 203                 writel_relaxed(l2x0_saved_regs.aux_ctrl,
 204                                sar_base + L2X0_AUXCTRL_OFFSET);
 205                 writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
 206                                sar_base + L2X0_PREFETCH_CTRL_OFFSET);
 207         }
 208 }
 209 #else
 210 static void __init save_l2x0_context(void)
 211 {}
 212 #endif
 213
 214 /**
 215  * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
 216  * The purpose of this function is to manage low power programming
 217  * of OMAP4 MPUSS subsystem
 218  * @cpu : CPU ID
 219  * @power_state: Low power state.
 220  *
 221  * MPUSS states for the context save:
 222  * save_state =
 223  *      0 - Nothing lost and no need to save: MPUSS INACTIVE
 224  *      1 - CPUx L1 and logic lost: MPUSS CSWR
 225  *      2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
 226  *      3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
 227  */
 228 int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 229 {
 230         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
 231         unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET;
 232         unsigned int wakeup_cpu;
 233
 234         if (omap_rev() == OMAP4430_REV_ES1_0)
 235                 return -ENXIO;
 236
 237         switch (power_state) {
 238         case PWRDM_POWER_ON:
 239         case PWRDM_POWER_INACTIVE:
 240                 save_state = 0;
 241                 break;
 242         case PWRDM_POWER_OFF:
 243                 cpu_logic_state = PWRDM_POWER_OFF;
 244                 save_state = 1;
 245                 break;
 246         case PWRDM_POWER_RET:
 247                 if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) {
 248                         save_state = 0;
 249                         break;
 250                 }
 251         default:
 252                 /*
 253                  * CPUx CSWR is invalid hardware state. Also CPUx OSWR
 254                  * doesn't make much scense, since logic is lost and $L1
 255                  * needs to be cleaned because of coherency. This makes
 256                  * CPUx OSWR equivalent to CPUX OFF and hence not supported
 257                  */
 258                 WARN_ON(1);
 259                 return -ENXIO;
 260         }
 261
 262         pwrdm_pre_transition(NULL);
 263
 264         /*
 265          * Check MPUSS next state and save interrupt controller if needed.
 266          * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
 267          */
 268         mpuss_clear_prev_logic_pwrst();
 269         if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
 270                 (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
 271                 save_state = 2;
 272
 273         cpu_clear_prev_logic_pwrst(cpu);
 274         pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
 275         pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
 276         set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
 277         omap_pm_ops.scu_prepare(cpu, power_state);
 278         l2x0_pwrst_prepare(cpu, save_state);
 279
 280         /*
 281          * Call low level function  with targeted low power state.
 282          */
 283         if (save_state)
 284                 cpu_suspend(save_state, omap_pm_ops.finish_suspend);
 285         else
 286                 omap_pm_ops.finish_suspend(save_state);
 287
 288         if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu)
 289                 gic_dist_enable();
 290
 291         /*
 292          * Restore the CPUx power state to ON otherwise CPUx
 293          * power domain can transitions to programmed low power
 294          * state while doing WFI outside the low powe code. On
 295          * secure devices, CPUx does WFI which can result in
 296          * domain transition
 297          */
 298         wakeup_cpu = smp_processor_id();
 299         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 300
 301         pwrdm_post_transition(NULL);
 302
 303         return 0;
 304 }
 305
 306 /**
 307  * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
 308  * @cpu : CPU ID
 309  * @power_state: CPU low power state.
 310  */
 311 int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 312 {
 313         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
 314         unsigned int cpu_state = 0;
 315
 316         if (omap_rev() == OMAP4430_REV_ES1_0)
 317                 return -ENXIO;
 318
 319         /* Use the achievable power state for the domain */
 320         power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm,
 321                                                false, power_state);
 322
 323         if (power_state == PWRDM_POWER_OFF)
 324                 cpu_state = 1;
 325
 326         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
 327         pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
 328         set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.hotplug_restart));
 329         omap_pm_ops.scu_prepare(cpu, power_state);
 330
 331         /*
 332          * CPU never retuns back if targeted power state is OFF mode.
 333          * CPU ONLINE follows normal CPU ONLINE ptah via
 334          * omap4_secondary_startup().
 335          */
 336         omap_pm_ops.finish_suspend(cpu_state);
 337
 338         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 339         return 0;
 340 }
 341
 342
 343 /*
 344  * Enable Mercury Fast HG retention mode by default.
 345  */
 346 static void enable_mercury_retention_mode(void)
 347 {
 348         u32 reg;
 349
 350         reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST,
 351                                   OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
 352         /* Enable HG_EN, HG_RAMPUP = fast mode */
 353         reg |= BIT(24) | BIT(25);
 354         omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST,
 355                                       OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
 356 }
 357
 358 /*
 359  * Initialise OMAP4 MPUSS
 360  */
 361 int __init omap4_mpuss_init(void)
 362 {
 363         struct omap4_cpu_pm_info *pm_info;
 364
 365         if (omap_rev() == OMAP4430_REV_ES1_0) {
 366                 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
 367                 return -ENODEV;
 368         }
 369
 370         /* Initilaise per CPU PM information */
 371         pm_info = &per_cpu(omap4_pm_info, 0x0);
 372         if (sar_base) {
 373                 pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
 374                 pm_info->wkup_sar_addr = sar_base +
 375                                         CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
 376                 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
 377         }
 378         pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
 379         if (!pm_info->pwrdm) {
 380                 pr_err("Lookup failed for CPU0 pwrdm\n");
 381                 return -ENODEV;
 382         }
 383
 384         /* Clear CPU previous power domain state */
 385         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
 386         cpu_clear_prev_logic_pwrst(0);
 387
 388         /* Initialise CPU0 power domain state to ON */
 389         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 390
 391         pm_info = &per_cpu(omap4_pm_info, 0x1);
 392         if (sar_base) {
 393                 pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
 394                 pm_info->wkup_sar_addr = sar_base +
 395                                         CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
 396                 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
 397         }
 398
 399         pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
 400         if (!pm_info->pwrdm) {
 401                 pr_err("Lookup failed for CPU1 pwrdm\n");
 402                 return -ENODEV;
 403         }
 404
 405         /* Clear CPU previous power domain state */
 406         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
 407         cpu_clear_prev_logic_pwrst(1);
 408
 409         /* Initialise CPU1 power domain state to ON */
 410         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 411
 412         mpuss_pd = pwrdm_lookup("mpu_pwrdm");
 413         if (!mpuss_pd) {
 414                 pr_err("Failed to lookup MPUSS power domain\n");
 415                 return -ENODEV;
 416         }
 417         pwrdm_clear_all_prev_pwrst(mpuss_pd);
 418         mpuss_clear_prev_logic_pwrst();
 419
 420         if (sar_base) {
 421                 /* Save device type on scratchpad for low level code to use */
 422                 writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0,
 423                                sar_base + OMAP_TYPE_OFFSET);
 424                 save_l2x0_context();
 425         }
 426
 427         if (cpu_is_omap44xx()) {
 428                 omap_pm_ops.finish_suspend = omap4_finish_suspend;
 429                 omap_pm_ops.resume = omap4_cpu_resume;
 430                 omap_pm_ops.scu_prepare = scu_pwrst_prepare;
 431                 omap_pm_ops.hotplug_restart = omap4_secondary_startup;
 432                 cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
 433         } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
 434                 cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
 435                 enable_mercury_retention_mode();
 436         }
 437
 438         if (cpu_is_omap446x())
 439                 omap_pm_ops.hotplug_restart = omap4460_secondary_startup;
 440
 441         return 0;
 442 }
 443
 444 #endif
 445
 446 /*
 447  * For kexec, we must set CPU1_WAKEUP_NS_PA_ADDR to point to
 448  * current kernel's secondary_startup() early before
 449  * clockdomains_init(). Otherwise clockdomain_init() can
 450  * wake CPU1 and cause a hang.
 451  */
 452 void __init omap4_mpuss_early_init(void)
 453 {
 454         unsigned long startup_pa;
 455
 456         if (!cpu_is_omap44xx())
 457                 return;
 458
 459         sar_base = omap4_get_sar_ram_base();
 460
 461         if (cpu_is_omap443x())
 462                 startup_pa = virt_to_phys(omap4_secondary_startup);
 463         else
 464                 startup_pa = virt_to_phys(omap4460_secondary_startup);
 465
 466         writel_relaxed(startup_pa, sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
 467 }