2 * OMAP WakeupGen Source file
4 * OMAP WakeupGen is the interrupt controller extension used along
5 * with ARM GIC to wake the CPU out from low power states on
6 * external interrupts. It is responsible for generating wakeup
7 * event from the incoming interrupts and enable bits. It is
8 * implemented in MPU always ON power domain. During normal operation,
9 * WakeupGen delivers external interrupts directly to the GIC.
11 * Copyright (C) 2011 Texas Instruments, Inc.
12 * Santosh Shilimkar <santosh.shilimkar@ti.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #include <linux/kernel.h>
20 #include <linux/init.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/of_address.h>
25 #include <linux/platform_device.h>
26 #include <linux/cpu.h>
27 #include <linux/notifier.h>
28 #include <linux/cpu_pm.h>
30 #include "omap-wakeupgen.h"
31 #include "omap-secure.h"
34 #include "omap4-sar-layout.h"
38 #define AM43XX_NR_REG_BANKS 7
39 #define AM43XX_IRQS 224
40 #define MAX_NR_REG_BANKS AM43XX_NR_REG_BANKS
41 #define MAX_IRQS AM43XX_IRQS
42 #define DEFAULT_NR_REG_BANKS 5
43 #define DEFAULT_IRQS 160
44 #define WKG_MASK_ALL 0x00000000
45 #define WKG_UNMASK_ALL 0xffffffff
46 #define CPU_ENA_OFFSET 0x400
49 #define OMAP4_NR_BANKS 4
50 #define OMAP4_NR_IRQS 128
52 static void __iomem
*wakeupgen_base
;
53 static void __iomem
*sar_base
;
54 static DEFINE_RAW_SPINLOCK(wakeupgen_lock
);
55 static unsigned int irq_target_cpu
[MAX_IRQS
];
56 static unsigned int irq_banks
= DEFAULT_NR_REG_BANKS
;
57 static unsigned int max_irqs
= DEFAULT_IRQS
;
58 static unsigned int omap_secure_apis
;
61 * Static helper functions.
63 static inline u32
wakeupgen_readl(u8 idx
, u32 cpu
)
65 return readl_relaxed(wakeupgen_base
+ OMAP_WKG_ENB_A_0
+
66 (cpu
* CPU_ENA_OFFSET
) + (idx
* 4));
69 static inline void wakeupgen_writel(u32 val
, u8 idx
, u32 cpu
)
71 writel_relaxed(val
, wakeupgen_base
+ OMAP_WKG_ENB_A_0
+
72 (cpu
* CPU_ENA_OFFSET
) + (idx
* 4));
75 static inline void sar_writel(u32 val
, u32 offset
, u8 idx
)
77 writel_relaxed(val
, sar_base
+ offset
+ (idx
* 4));
80 static inline int _wakeupgen_get_irq_info(u32 irq
, u32
*bit_posn
, u8
*reg_index
)
83 * Each WakeupGen register controls 32 interrupt.
84 * i.e. 1 bit per SPI IRQ
86 *reg_index
= irq
>> 5;
87 *bit_posn
= irq
%= 32;
92 static void _wakeupgen_clear(unsigned int irq
, unsigned int cpu
)
97 if (_wakeupgen_get_irq_info(irq
, &bit_number
, &i
))
100 val
= wakeupgen_readl(i
, cpu
);
101 val
&= ~BIT(bit_number
);
102 wakeupgen_writel(val
, i
, cpu
);
105 static void _wakeupgen_set(unsigned int irq
, unsigned int cpu
)
110 if (_wakeupgen_get_irq_info(irq
, &bit_number
, &i
))
113 val
= wakeupgen_readl(i
, cpu
);
114 val
|= BIT(bit_number
);
115 wakeupgen_writel(val
, i
, cpu
);
119 * Architecture specific Mask extension
121 static void wakeupgen_mask(struct irq_data
*d
)
125 raw_spin_lock_irqsave(&wakeupgen_lock
, flags
);
126 _wakeupgen_clear(d
->hwirq
, irq_target_cpu
[d
->hwirq
]);
127 raw_spin_unlock_irqrestore(&wakeupgen_lock
, flags
);
128 irq_chip_mask_parent(d
);
132 * Architecture specific Unmask extension
134 static void wakeupgen_unmask(struct irq_data
*d
)
138 raw_spin_lock_irqsave(&wakeupgen_lock
, flags
);
139 _wakeupgen_set(d
->hwirq
, irq_target_cpu
[d
->hwirq
]);
140 raw_spin_unlock_irqrestore(&wakeupgen_lock
, flags
);
141 irq_chip_unmask_parent(d
);
144 #ifdef CONFIG_HOTPLUG_CPU
145 static DEFINE_PER_CPU(u32
[MAX_NR_REG_BANKS
], irqmasks
);
147 static void _wakeupgen_save_masks(unsigned int cpu
)
151 for (i
= 0; i
< irq_banks
; i
++)
152 per_cpu(irqmasks
, cpu
)[i
] = wakeupgen_readl(i
, cpu
);
155 static void _wakeupgen_restore_masks(unsigned int cpu
)
159 for (i
= 0; i
< irq_banks
; i
++)
160 wakeupgen_writel(per_cpu(irqmasks
, cpu
)[i
], i
, cpu
);
163 static void _wakeupgen_set_all(unsigned int cpu
, unsigned int reg
)
167 for (i
= 0; i
< irq_banks
; i
++)
168 wakeupgen_writel(reg
, i
, cpu
);
172 * Mask or unmask all interrupts on given CPU.
173 * 0 = Mask all interrupts on the 'cpu'
174 * 1 = Unmask all interrupts on the 'cpu'
175 * Ensure that the initial mask is maintained. This is faster than
176 * iterating through GIC registers to arrive at the correct masks.
178 static void wakeupgen_irqmask_all(unsigned int cpu
, unsigned int set
)
182 raw_spin_lock_irqsave(&wakeupgen_lock
, flags
);
184 _wakeupgen_save_masks(cpu
);
185 _wakeupgen_set_all(cpu
, WKG_MASK_ALL
);
187 _wakeupgen_set_all(cpu
, WKG_UNMASK_ALL
);
188 _wakeupgen_restore_masks(cpu
);
190 raw_spin_unlock_irqrestore(&wakeupgen_lock
, flags
);
195 static inline void omap4_irq_save_context(void)
199 if (omap_rev() == OMAP4430_REV_ES1_0
)
202 for (i
= 0; i
< irq_banks
; i
++) {
203 /* Save the CPUx interrupt mask for IRQ 0 to 127 */
204 val
= wakeupgen_readl(i
, 0);
205 sar_writel(val
, WAKEUPGENENB_OFFSET_CPU0
, i
);
206 val
= wakeupgen_readl(i
, 1);
207 sar_writel(val
, WAKEUPGENENB_OFFSET_CPU1
, i
);
210 * Disable the secure interrupts for CPUx. The restore
211 * code blindly restores secure and non-secure interrupt
212 * masks from SAR RAM. Secure interrupts are not suppose
213 * to be enabled from HLOS. So overwrite the SAR location
214 * so that the secure interrupt remains disabled.
216 sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0
, i
);
217 sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1
, i
);
220 /* Save AuxBoot* registers */
221 val
= readl_relaxed(wakeupgen_base
+ OMAP_AUX_CORE_BOOT_0
);
222 writel_relaxed(val
, sar_base
+ AUXCOREBOOT0_OFFSET
);
223 val
= readl_relaxed(wakeupgen_base
+ OMAP_AUX_CORE_BOOT_1
);
224 writel_relaxed(val
, sar_base
+ AUXCOREBOOT1_OFFSET
);
226 /* Save SyncReq generation logic */
227 val
= readl_relaxed(wakeupgen_base
+ OMAP_PTMSYNCREQ_MASK
);
228 writel_relaxed(val
, sar_base
+ PTMSYNCREQ_MASK_OFFSET
);
229 val
= readl_relaxed(wakeupgen_base
+ OMAP_PTMSYNCREQ_EN
);
230 writel_relaxed(val
, sar_base
+ PTMSYNCREQ_EN_OFFSET
);
232 /* Set the Backup Bit Mask status */
233 val
= readl_relaxed(sar_base
+ SAR_BACKUP_STATUS_OFFSET
);
234 val
|= SAR_BACKUP_STATUS_WAKEUPGEN
;
235 writel_relaxed(val
, sar_base
+ SAR_BACKUP_STATUS_OFFSET
);
239 static inline void omap5_irq_save_context(void)
243 for (i
= 0; i
< irq_banks
; i
++) {
244 /* Save the CPUx interrupt mask for IRQ 0 to 159 */
245 val
= wakeupgen_readl(i
, 0);
246 sar_writel(val
, OMAP5_WAKEUPGENENB_OFFSET_CPU0
, i
);
247 val
= wakeupgen_readl(i
, 1);
248 sar_writel(val
, OMAP5_WAKEUPGENENB_OFFSET_CPU1
, i
);
249 sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0
, i
);
250 sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1
, i
);
253 /* Save AuxBoot* registers */
254 val
= readl_relaxed(wakeupgen_base
+ OMAP_AUX_CORE_BOOT_0
);
255 writel_relaxed(val
, sar_base
+ OMAP5_AUXCOREBOOT0_OFFSET
);
256 val
= readl_relaxed(wakeupgen_base
+ OMAP_AUX_CORE_BOOT_0
);
257 writel_relaxed(val
, sar_base
+ OMAP5_AUXCOREBOOT1_OFFSET
);
259 /* Set the Backup Bit Mask status */
260 val
= readl_relaxed(sar_base
+ OMAP5_SAR_BACKUP_STATUS_OFFSET
);
261 val
|= SAR_BACKUP_STATUS_WAKEUPGEN
;
262 writel_relaxed(val
, sar_base
+ OMAP5_SAR_BACKUP_STATUS_OFFSET
);
267 * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
268 * ROM code. WakeupGen IP is integrated along with GIC to manage the
269 * interrupt wakeups from CPU low power states. It manages
270 * masking/unmasking of Shared peripheral interrupts(SPI). So the
271 * interrupt enable/disable control should be in sync and consistent
272 * at WakeupGen and GIC so that interrupts are not lost.
274 static void irq_save_context(void)
277 sar_base
= omap4_get_sar_ram_base();
279 if (soc_is_omap54xx())
280 omap5_irq_save_context();
282 omap4_irq_save_context();
286 * Clear WakeupGen SAR backup status.
288 static void irq_sar_clear(void)
291 u32 offset
= SAR_BACKUP_STATUS_OFFSET
;
293 if (soc_is_omap54xx())
294 offset
= OMAP5_SAR_BACKUP_STATUS_OFFSET
;
296 val
= readl_relaxed(sar_base
+ offset
);
297 val
&= ~SAR_BACKUP_STATUS_WAKEUPGEN
;
298 writel_relaxed(val
, sar_base
+ offset
);
302 * Save GIC and Wakeupgen interrupt context using secure API
303 * for HS/EMU devices.
305 static void irq_save_secure_context(void)
308 ret
= omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX
,
311 if (ret
!= API_HAL_RET_VALUE_OK
)
312 pr_err("GIC and Wakeupgen context save failed\n");
316 #ifdef CONFIG_HOTPLUG_CPU
317 static int irq_cpu_hotplug_notify(struct notifier_block
*self
,
318 unsigned long action
, void *hcpu
)
320 unsigned int cpu
= (unsigned int)hcpu
;
324 wakeupgen_irqmask_all(cpu
, 0);
327 wakeupgen_irqmask_all(cpu
, 1);
333 static struct notifier_block __refdata irq_hotplug_notifier
= {
334 .notifier_call
= irq_cpu_hotplug_notify
,
337 static void __init
irq_hotplug_init(void)
339 register_hotcpu_notifier(&irq_hotplug_notifier
);
342 static void __init
irq_hotplug_init(void)
347 static int irq_notifier(struct notifier_block
*self
, unsigned long cmd
, void *v
)
350 case CPU_CLUSTER_PM_ENTER
:
351 if (omap_type() == OMAP2_DEVICE_TYPE_GP
)
354 irq_save_secure_context();
356 case CPU_CLUSTER_PM_EXIT
:
357 if (omap_type() == OMAP2_DEVICE_TYPE_GP
)
364 static struct notifier_block irq_notifier_block
= {
365 .notifier_call
= irq_notifier
,
368 static void __init
irq_pm_init(void)
370 /* FIXME: Remove this when MPU OSWR support is added */
371 if (!IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE
))
372 cpu_pm_register_notifier(&irq_notifier_block
);
375 static void __init
irq_pm_init(void)
379 void __iomem
*omap_get_wakeupgen_base(void)
381 return wakeupgen_base
;
384 int omap_secure_apis_support(void)
386 return omap_secure_apis
;
389 static struct irq_chip wakeupgen_chip
= {
391 .irq_eoi
= irq_chip_eoi_parent
,
392 .irq_mask
= wakeupgen_mask
,
393 .irq_unmask
= wakeupgen_unmask
,
394 .irq_retrigger
= irq_chip_retrigger_hierarchy
,
395 .flags
= IRQCHIP_SKIP_SET_WAKE
| IRQCHIP_MASK_ON_SUSPEND
,
397 .irq_set_affinity
= irq_chip_set_affinity_parent
,
401 static int wakeupgen_domain_xlate(struct irq_domain
*domain
,
402 struct device_node
*controller
,
404 unsigned int intsize
,
405 unsigned long *out_hwirq
,
406 unsigned int *out_type
)
408 if (domain
->of_node
!= controller
)
409 return -EINVAL
; /* Shouldn't happen, really... */
411 return -EINVAL
; /* Not GIC compliant */
413 return -EINVAL
; /* No PPI should point to this domain */
415 *out_hwirq
= intspec
[1];
416 *out_type
= intspec
[2];
420 static int wakeupgen_domain_alloc(struct irq_domain
*domain
,
422 unsigned int nr_irqs
, void *data
)
424 struct of_phandle_args
*args
= data
;
425 struct of_phandle_args parent_args
;
426 irq_hw_number_t hwirq
;
429 if (args
->args_count
!= 3)
430 return -EINVAL
; /* Not GIC compliant */
431 if (args
->args
[0] != 0)
432 return -EINVAL
; /* No PPI should point to this domain */
434 hwirq
= args
->args
[1];
435 if (hwirq
>= MAX_IRQS
)
436 return -EINVAL
; /* Can't deal with this */
438 for (i
= 0; i
< nr_irqs
; i
++)
439 irq_domain_set_hwirq_and_chip(domain
, virq
+ i
, hwirq
+ i
,
440 &wakeupgen_chip
, NULL
);
443 parent_args
.np
= domain
->parent
->of_node
;
444 return irq_domain_alloc_irqs_parent(domain
, virq
, nr_irqs
, &parent_args
);
447 static const struct irq_domain_ops wakeupgen_domain_ops
= {
448 .xlate
= wakeupgen_domain_xlate
,
449 .alloc
= wakeupgen_domain_alloc
,
450 .free
= irq_domain_free_irqs_common
,
454 * Initialise the wakeupgen module.
456 static int __init
wakeupgen_init(struct device_node
*node
,
457 struct device_node
*parent
)
459 struct irq_domain
*parent_domain
, *domain
;
461 unsigned int boot_cpu
= smp_processor_id();
465 pr_err("%s: no parent, giving up\n", node
->full_name
);
469 parent_domain
= irq_find_host(parent
);
470 if (!parent_domain
) {
471 pr_err("%s: unable to obtain parent domain\n", node
->full_name
);
474 /* Not supported on OMAP4 ES1.0 silicon */
475 if (omap_rev() == OMAP4430_REV_ES1_0
) {
476 WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
480 /* Static mapping, never released */
481 wakeupgen_base
= of_iomap(node
, 0);
482 if (WARN_ON(!wakeupgen_base
))
485 if (cpu_is_omap44xx()) {
486 irq_banks
= OMAP4_NR_BANKS
;
487 max_irqs
= OMAP4_NR_IRQS
;
488 omap_secure_apis
= 1;
489 } else if (soc_is_am43xx()) {
490 irq_banks
= AM43XX_NR_REG_BANKS
;
491 max_irqs
= AM43XX_IRQS
;
494 domain
= irq_domain_add_hierarchy(parent_domain
, 0, max_irqs
,
495 node
, &wakeupgen_domain_ops
,
498 iounmap(wakeupgen_base
);
502 /* Clear all IRQ bitmasks at wakeupGen level */
503 for (i
= 0; i
< irq_banks
; i
++) {
504 wakeupgen_writel(0, i
, CPU0_ID
);
505 if (!soc_is_am43xx())
506 wakeupgen_writel(0, i
, CPU1_ID
);
510 * FIXME: Add support to set_smp_affinity() once the core
511 * GIC code has necessary hooks in place.
514 /* Associate all the IRQs to boot CPU like GIC init does. */
515 for (i
= 0; i
< max_irqs
; i
++)
516 irq_target_cpu
[i
] = boot_cpu
;
519 * Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE
520 * 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together.
521 * 0x1: ES2 behavior, CPU cores are allowed to enter/exit OFF mode
523 * This needs to be set one time thanks to always ON domain.
525 * We do not support ES1 behavior anymore. OMAP5 is assumed to be
526 * ES2.0, and the same is applicable for DRA7.
528 if (soc_is_omap54xx() || soc_is_dra7xx()) {
529 val
= __raw_readl(wakeupgen_base
+ OMAP_AMBA_IF_MODE
);
531 omap_smc1(OMAP5_MON_AMBA_IF_INDEX
, val
);
541 * We cannot use the IRQCHIP_DECLARE macro that lives in
542 * drivers/irqchip, so we're forced to roll our own. Not very nice.
544 OF_DECLARE_2(irqchip
, ti_wakeupgen
, "ti,omap4-wugen-mpu", wakeupgen_init
);