arch/arm/mach-omap2/omap-wakeupgen.c

   1 /*
   2  * OMAP WakeupGen Source file
   3  *
   4  * OMAP WakeupGen is the interrupt controller extension used along
   5  * with ARM GIC to wake the CPU out from low power states on
   6  * external interrupts. It is responsible for generating wakeup
   7  * event from the incoming interrupts and enable bits. It is
   8  * implemented in MPU always ON power domain. During normal operation,
   9  * WakeupGen delivers external interrupts directly to the GIC.
  10  *
  11  * Copyright (C) 2011 Texas Instruments, Inc.
  12  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/irq.h>
  23 #include <linux/irqdomain.h>
  24 #include <linux/of_address.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/cpu.h>
  27 #include <linux/notifier.h>
  28 #include <linux/cpu_pm.h>
  29
  30 #include "omap-wakeupgen.h"
  31 #include "omap-secure.h"
  32
  33 #include "soc.h"
  34 #include "omap4-sar-layout.h"
  35 #include "common.h"
  36 #include "pm.h"
  37
  38 #define AM43XX_NR_REG_BANKS     7
  39 #define AM43XX_IRQS             224
  40 #define MAX_NR_REG_BANKS        AM43XX_NR_REG_BANKS
  41 #define MAX_IRQS                AM43XX_IRQS
  42 #define DEFAULT_NR_REG_BANKS    5
  43 #define DEFAULT_IRQS            160
  44 #define WKG_MASK_ALL            0x00000000
  45 #define WKG_UNMASK_ALL          0xffffffff
  46 #define CPU_ENA_OFFSET          0x400
  47 #define CPU0_ID                 0x0
  48 #define CPU1_ID                 0x1
  49 #define OMAP4_NR_BANKS          4
  50 #define OMAP4_NR_IRQS           128
  51
  52 static void __iomem *wakeupgen_base;
  53 static void __iomem *sar_base;
  54 static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
  55 static unsigned int irq_target_cpu[MAX_IRQS];
  56 static unsigned int irq_banks = DEFAULT_NR_REG_BANKS;
  57 static unsigned int max_irqs = DEFAULT_IRQS;
  58 static unsigned int omap_secure_apis;
  59
  60 /*
  61  * Static helper functions.
  62  */
  63 static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
  64 {
  65         return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 +
  66                                 (cpu * CPU_ENA_OFFSET) + (idx * 4));
  67 }
  68
  69 static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
  70 {
  71         writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
  72                                 (cpu * CPU_ENA_OFFSET) + (idx * 4));
  73 }
  74
  75 static inline void sar_writel(u32 val, u32 offset, u8 idx)
  76 {
  77         writel_relaxed(val, sar_base + offset + (idx * 4));
  78 }
  79
  80 static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
  81 {
  82         /*
  83          * Each WakeupGen register controls 32 interrupt.
  84          * i.e. 1 bit per SPI IRQ
  85          */
  86         *reg_index = irq >> 5;
  87         *bit_posn = irq %= 32;
  88
  89         return 0;
  90 }
  91
  92 static void _wakeupgen_clear(unsigned int irq, unsigned int cpu)
  93 {
  94         u32 val, bit_number;
  95         u8 i;
  96
  97         if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
  98                 return;
  99
 100         val = wakeupgen_readl(i, cpu);
 101         val &= ~BIT(bit_number);
 102         wakeupgen_writel(val, i, cpu);
 103 }
 104
 105 static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
 106 {
 107         u32 val, bit_number;
 108         u8 i;
 109
 110         if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
 111                 return;
 112
 113         val = wakeupgen_readl(i, cpu);
 114         val |= BIT(bit_number);
 115         wakeupgen_writel(val, i, cpu);
 116 }
 117
 118 /*
 119  * Architecture specific Mask extension
 120  */
 121 static void wakeupgen_mask(struct irq_data *d)
 122 {
 123         unsigned long flags;
 124
 125         raw_spin_lock_irqsave(&wakeupgen_lock, flags);
 126         _wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]);
 127         raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
 128         irq_chip_mask_parent(d);
 129 }
 130
 131 /*
 132  * Architecture specific Unmask extension
 133  */
 134 static void wakeupgen_unmask(struct irq_data *d)
 135 {
 136         unsigned long flags;
 137
 138         raw_spin_lock_irqsave(&wakeupgen_lock, flags);
 139         _wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
 140         raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
 141         irq_chip_unmask_parent(d);
 142 }
 143
 144 #ifdef CONFIG_HOTPLUG_CPU
 145 static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
 146
 147 static void _wakeupgen_save_masks(unsigned int cpu)
 148 {
 149         u8 i;
 150
 151         for (i = 0; i < irq_banks; i++)
 152                 per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
 153 }
 154
 155 static void _wakeupgen_restore_masks(unsigned int cpu)
 156 {
 157         u8 i;
 158
 159         for (i = 0; i < irq_banks; i++)
 160                 wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
 161 }
 162
 163 static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
 164 {
 165         u8 i;
 166
 167         for (i = 0; i < irq_banks; i++)
 168                 wakeupgen_writel(reg, i, cpu);
 169 }
 170
 171 /*
 172  * Mask or unmask all interrupts on given CPU.
 173  *      0 = Mask all interrupts on the 'cpu'
 174  *      1 = Unmask all interrupts on the 'cpu'
 175  * Ensure that the initial mask is maintained. This is faster than
 176  * iterating through GIC registers to arrive at the correct masks.
 177  */
 178 static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
 179 {
 180         unsigned long flags;
 181
 182         raw_spin_lock_irqsave(&wakeupgen_lock, flags);
 183         if (set) {
 184                 _wakeupgen_save_masks(cpu);
 185                 _wakeupgen_set_all(cpu, WKG_MASK_ALL);
 186         } else {
 187                 _wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
 188                 _wakeupgen_restore_masks(cpu);
 189         }
 190         raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
 191 }
 192 #endif
 193
 194 #ifdef CONFIG_CPU_PM
 195 static inline void omap4_irq_save_context(void)
 196 {
 197         u32 i, val;
 198
 199         if (omap_rev() == OMAP4430_REV_ES1_0)
 200                 return;
 201
 202         for (i = 0; i < irq_banks; i++) {
 203                 /* Save the CPUx interrupt mask for IRQ 0 to 127 */
 204                 val = wakeupgen_readl(i, 0);
 205                 sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
 206                 val = wakeupgen_readl(i, 1);
 207                 sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);
 208
 209                 /*
 210                  * Disable the secure interrupts for CPUx. The restore
 211                  * code blindly restores secure and non-secure interrupt
 212                  * masks from SAR RAM. Secure interrupts are not suppose
 213                  * to be enabled from HLOS. So overwrite the SAR location
 214                  * so that the secure interrupt remains disabled.
 215                  */
 216                 sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
 217                 sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
 218         }
 219
 220         /* Save AuxBoot* registers */
 221         val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
 222         writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);
 223         val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
 224         writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);
 225
 226         /* Save SyncReq generation logic */
 227         val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
 228         writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
 229         val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
 230         writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);
 231
 232         /* Set the Backup Bit Mask status */
 233         val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);
 234         val |= SAR_BACKUP_STATUS_WAKEUPGEN;
 235         writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
 236
 237 }
 238
 239 static inline void omap5_irq_save_context(void)
 240 {
 241         u32 i, val;
 242
 243         for (i = 0; i < irq_banks; i++) {
 244                 /* Save the CPUx interrupt mask for IRQ 0 to 159 */
 245                 val = wakeupgen_readl(i, 0);
 246                 sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
 247                 val = wakeupgen_readl(i, 1);
 248                 sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
 249                 sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
 250                 sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
 251         }
 252
 253         /* Save AuxBoot* registers */
 254         val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
 255         writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
 256         val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
 257         writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
 258
 259         /* Set the Backup Bit Mask status */
 260         val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
 261         val |= SAR_BACKUP_STATUS_WAKEUPGEN;
 262         writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
 263
 264 }
 265
 266 /*
 267  * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
 268  * ROM code. WakeupGen IP is integrated along with GIC to manage the
 269  * interrupt wakeups from CPU low power states. It manages
 270  * masking/unmasking of Shared peripheral interrupts(SPI). So the
 271  * interrupt enable/disable control should be in sync and consistent
 272  * at WakeupGen and GIC so that interrupts are not lost.
 273  */
 274 static void irq_save_context(void)
 275 {
 276         if (!sar_base)
 277                 sar_base = omap4_get_sar_ram_base();
 278
 279         if (soc_is_omap54xx())
 280                 omap5_irq_save_context();
 281         else
 282                 omap4_irq_save_context();
 283 }
 284
 285 /*
 286  * Clear WakeupGen SAR backup status.
 287  */
 288 static void irq_sar_clear(void)
 289 {
 290         u32 val;
 291         u32 offset = SAR_BACKUP_STATUS_OFFSET;
 292
 293         if (soc_is_omap54xx())
 294                 offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
 295
 296         val = readl_relaxed(sar_base + offset);
 297         val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
 298         writel_relaxed(val, sar_base + offset);
 299 }
 300
 301 /*
 302  * Save GIC and Wakeupgen interrupt context using secure API
 303  * for HS/EMU devices.
 304  */
 305 static void irq_save_secure_context(void)
 306 {
 307         u32 ret;
 308         ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
 309                                 FLAG_START_CRITICAL,
 310                                 0, 0, 0, 0, 0);
 311         if (ret != API_HAL_RET_VALUE_OK)
 312                 pr_err("GIC and Wakeupgen context save failed\n");
 313 }
 314 #endif
 315
 316 #ifdef CONFIG_HOTPLUG_CPU
 317 static int irq_cpu_hotplug_notify(struct notifier_block *self,
 318                                   unsigned long action, void *hcpu)
 319 {
 320         unsigned int cpu = (unsigned int)hcpu;
 321
 322         switch (action) {
 323         case CPU_ONLINE:
 324                 wakeupgen_irqmask_all(cpu, 0);
 325                 break;
 326         case CPU_DEAD:
 327                 wakeupgen_irqmask_all(cpu, 1);
 328                 break;
 329         }
 330         return NOTIFY_OK;
 331 }
 332
 333 static struct notifier_block __refdata irq_hotplug_notifier = {
 334         .notifier_call = irq_cpu_hotplug_notify,
 335 };
 336
 337 static void __init irq_hotplug_init(void)
 338 {
 339         register_hotcpu_notifier(&irq_hotplug_notifier);
 340 }
 341 #else
 342 static void __init irq_hotplug_init(void)
 343 {}
 344 #endif
 345
 346 #ifdef CONFIG_CPU_PM
 347 static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v)
 348 {
 349         switch (cmd) {
 350         case CPU_CLUSTER_PM_ENTER:
 351                 if (omap_type() == OMAP2_DEVICE_TYPE_GP)
 352                         irq_save_context();
 353                 else
 354                         irq_save_secure_context();
 355                 break;
 356         case CPU_CLUSTER_PM_EXIT:
 357                 if (omap_type() == OMAP2_DEVICE_TYPE_GP)
 358                         irq_sar_clear();
 359                 break;
 360         }
 361         return NOTIFY_OK;
 362 }
 363
 364 static struct notifier_block irq_notifier_block = {
 365         .notifier_call = irq_notifier,
 366 };
 367
 368 static void __init irq_pm_init(void)
 369 {
 370         /* FIXME: Remove this when MPU OSWR support is added */
 371         if (!IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
 372                 cpu_pm_register_notifier(&irq_notifier_block);
 373 }
 374 #else
 375 static void __init irq_pm_init(void)
 376 {}
 377 #endif
 378
 379 void __iomem *omap_get_wakeupgen_base(void)
 380 {
 381         return wakeupgen_base;
 382 }
 383
 384 int omap_secure_apis_support(void)
 385 {
 386         return omap_secure_apis;
 387 }
 388
 389 static struct irq_chip wakeupgen_chip = {
 390         .name                   = "WUGEN",
 391         .irq_eoi                = irq_chip_eoi_parent,
 392         .irq_mask               = wakeupgen_mask,
 393         .irq_unmask             = wakeupgen_unmask,
 394         .irq_retrigger          = irq_chip_retrigger_hierarchy,
 395         .irq_set_type           = irq_chip_set_type_parent,
 396         .flags                  = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
 397 #ifdef CONFIG_SMP
 398         .irq_set_affinity       = irq_chip_set_affinity_parent,
 399 #endif
 400 };
 401
 402 static int wakeupgen_domain_translate(struct irq_domain *d,
 403                                       struct irq_fwspec *fwspec,
 404                                       unsigned long *hwirq,
 405                                       unsigned int *type)
 406 {
 407         if (is_of_node(fwspec->fwnode)) {
 408                 if (fwspec->param_count != 3)
 409                         return -EINVAL;
 410
 411                 /* No PPI should point to this domain */
 412                 if (fwspec->param[0] != 0)
 413                         return -EINVAL;
 414
 415                 *hwirq = fwspec->param[1];
 416                 *type = fwspec->param[2];
 417                 return 0;
 418         }
 419
 420         return -EINVAL;
 421 }
 422
 423 static int wakeupgen_domain_alloc(struct irq_domain *domain,
 424                                   unsigned int virq,
 425                                   unsigned int nr_irqs, void *data)
 426 {
 427         struct irq_fwspec *fwspec = data;
 428         struct irq_fwspec parent_fwspec;
 429         irq_hw_number_t hwirq;
 430         int i;
 431
 432         if (fwspec->param_count != 3)
 433                 return -EINVAL; /* Not GIC compliant */
 434         if (fwspec->param[0] != 0)
 435                 return -EINVAL; /* No PPI should point to this domain */
 436
 437         hwirq = fwspec->param[1];
 438         if (hwirq >= MAX_IRQS)
 439                 return -EINVAL; /* Can't deal with this */
 440
 441         for (i = 0; i < nr_irqs; i++)
 442                 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
 443                                               &wakeupgen_chip, NULL);
 444
 445         parent_fwspec = *fwspec;
 446         parent_fwspec.fwnode = domain->parent->fwnode;
 447         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 448                                             &parent_fwspec);
 449 }
 450
 451 static const struct irq_domain_ops wakeupgen_domain_ops = {
 452         .translate      = wakeupgen_domain_translate,
 453         .alloc          = wakeupgen_domain_alloc,
 454         .free           = irq_domain_free_irqs_common,
 455 };
 456
 457 /*
 458  * Initialise the wakeupgen module.
 459  */
 460 static int __init wakeupgen_init(struct device_node *node,
 461                                  struct device_node *parent)
 462 {
 463         struct irq_domain *parent_domain, *domain;
 464         int i;
 465         unsigned int boot_cpu = smp_processor_id();
 466         u32 val;
 467
 468         if (!parent) {
 469                 pr_err("%s: no parent, giving up\n", node->full_name);
 470                 return -ENODEV;
 471         }
 472
 473         parent_domain = irq_find_host(parent);
 474         if (!parent_domain) {
 475                 pr_err("%s: unable to obtain parent domain\n", node->full_name);
 476                 return -ENXIO;
 477         }
 478         /* Not supported on OMAP4 ES1.0 silicon */
 479         if (omap_rev() == OMAP4430_REV_ES1_0) {
 480                 WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
 481                 return -EPERM;
 482         }
 483
 484         /* Static mapping, never released */
 485         wakeupgen_base = of_iomap(node, 0);
 486         if (WARN_ON(!wakeupgen_base))
 487                 return -ENOMEM;
 488
 489         if (cpu_is_omap44xx()) {
 490                 irq_banks = OMAP4_NR_BANKS;
 491                 max_irqs = OMAP4_NR_IRQS;
 492                 omap_secure_apis = 1;
 493         } else if (soc_is_am43xx()) {
 494                 irq_banks = AM43XX_NR_REG_BANKS;
 495                 max_irqs = AM43XX_IRQS;
 496         }
 497
 498         domain = irq_domain_add_hierarchy(parent_domain, 0, max_irqs,
 499                                           node, &wakeupgen_domain_ops,
 500                                           NULL);
 501         if (!domain) {
 502                 iounmap(wakeupgen_base);
 503                 return -ENOMEM;
 504         }
 505
 506         /* Clear all IRQ bitmasks at wakeupGen level */
 507         for (i = 0; i < irq_banks; i++) {
 508                 wakeupgen_writel(0, i, CPU0_ID);
 509                 if (!soc_is_am43xx())
 510                         wakeupgen_writel(0, i, CPU1_ID);
 511         }
 512
 513         /*
 514          * FIXME: Add support to set_smp_affinity() once the core
 515          * GIC code has necessary hooks in place.
 516          */
 517
 518         /* Associate all the IRQs to boot CPU like GIC init does. */
 519         for (i = 0; i < max_irqs; i++)
 520                 irq_target_cpu[i] = boot_cpu;
 521
 522         /*
 523          * Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE
 524          * 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together.
 525          * 0x1: ES2 behavior, CPU cores are allowed to enter/exit OFF mode
 526          * independently.
 527          * This needs to be set one time thanks to always ON domain.
 528          *
 529          * We do not support ES1 behavior anymore. OMAP5 is assumed to be
 530          * ES2.0, and the same is applicable for DRA7.
 531          */
 532         if (soc_is_omap54xx() || soc_is_dra7xx()) {
 533                 val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE);
 534                 val |= BIT(5);
 535                 omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val);
 536         }
 537
 538         irq_hotplug_init();
 539         irq_pm_init();
 540
 541         return 0;
 542 }
 543
 544 /*
 545  * We cannot use the IRQCHIP_DECLARE macro that lives in
 546  * drivers/irqchip, so we're forced to roll our own. Not very nice.
 547  */
 548 OF_DECLARE_2(irqchip, ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init);