2 * OMAP4 specific common source file.
4 * Copyright (C) 2010 Texas Instruments, Inc.
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
9 * This program is free software,you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
17 #include <linux/irq.h>
18 #include <linux/irqchip.h>
19 #include <linux/platform_device.h>
20 #include <linux/memblock.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/export.h>
24 #include <linux/irqchip/arm-gic.h>
25 #include <linux/irqchip/irq-crossbar.h>
26 #include <linux/of_address.h>
27 #include <linux/reboot.h>
28 #include <linux/genalloc.h>
30 #include <asm/hardware/cache-l2x0.h>
31 #include <asm/mach/map.h>
32 #include <asm/memblock.h>
33 #include <asm/smp_twd.h>
35 #include "omap-wakeupgen.h"
39 #include "prminst44xx.h"
40 #include "prcm_mpu44xx.h"
41 #include "omap4-sar-layout.h"
42 #include "omap-secure.h"
45 #ifdef CONFIG_CACHE_L2X0
46 static void __iomem
*l2cache_base
;
49 static void __iomem
*sar_ram_base
;
50 static void __iomem
*gic_dist_base_addr
;
51 static void __iomem
*twd_base
;
53 #define IRQ_LOCALTIMER 29
55 #ifdef CONFIG_OMAP4_ERRATA_I688
56 /* Used to implement memory barrier on DRAM path */
57 #define OMAP4_DRAM_BARRIER_VA 0xfe600000
59 void __iomem
*dram_sync
, *sram_sync
;
61 static phys_addr_t paddr
;
64 void omap_bus_sync(void)
66 if (dram_sync
&& sram_sync
) {
67 writel_relaxed(readl_relaxed(dram_sync
), dram_sync
);
68 writel_relaxed(readl_relaxed(sram_sync
), sram_sync
);
72 EXPORT_SYMBOL(omap_bus_sync
);
74 static int __init
omap4_sram_init(void)
76 struct device_node
*np
;
77 struct gen_pool
*sram_pool
;
79 np
= of_find_compatible_node(NULL
, NULL
, "ti,omap4-mpu");
81 pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
83 sram_pool
= of_get_named_gen_pool(np
, "sram", 0);
85 pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
88 sram_sync
= (void *)gen_pool_alloc(sram_pool
, PAGE_SIZE
);
92 omap_arch_initcall(omap4_sram_init
);
94 /* Steal one page physical memory for barrier implementation */
95 int __init
omap_barrier_reserve_memblock(void)
98 size
= ALIGN(PAGE_SIZE
, SZ_1M
);
99 paddr
= arm_memblock_steal(size
, SZ_1M
);
104 void __init
omap_barriers_init(void)
106 struct map_desc dram_io_desc
[1];
108 dram_io_desc
[0].virtual = OMAP4_DRAM_BARRIER_VA
;
109 dram_io_desc
[0].pfn
= __phys_to_pfn(paddr
);
110 dram_io_desc
[0].length
= size
;
111 dram_io_desc
[0].type
= MT_MEMORY_RW_SO
;
112 iotable_init(dram_io_desc
, ARRAY_SIZE(dram_io_desc
));
113 dram_sync
= (void __iomem
*) dram_io_desc
[0].virtual;
115 pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
116 (long long) paddr
, dram_io_desc
[0].virtual);
120 void __init
omap_barriers_init(void)
124 void gic_dist_disable(void)
126 if (gic_dist_base_addr
)
127 writel_relaxed(0x0, gic_dist_base_addr
+ GIC_DIST_CTRL
);
130 void gic_dist_enable(void)
132 if (gic_dist_base_addr
)
133 writel_relaxed(0x1, gic_dist_base_addr
+ GIC_DIST_CTRL
);
136 bool gic_dist_disabled(void)
138 return !(readl_relaxed(gic_dist_base_addr
+ GIC_DIST_CTRL
) & 0x1);
141 void gic_timer_retrigger(void)
143 u32 twd_int
= readl_relaxed(twd_base
+ TWD_TIMER_INTSTAT
);
144 u32 gic_int
= readl_relaxed(gic_dist_base_addr
+ GIC_DIST_PENDING_SET
);
145 u32 twd_ctrl
= readl_relaxed(twd_base
+ TWD_TIMER_CONTROL
);
147 if (twd_int
&& !(gic_int
& BIT(IRQ_LOCALTIMER
))) {
149 * The local timer interrupt got lost while the distributor was
150 * disabled. Ack the pending interrupt, and retrigger it.
152 pr_warn("%s: lost localtimer interrupt\n", __func__
);
153 writel_relaxed(1, twd_base
+ TWD_TIMER_INTSTAT
);
154 if (!(twd_ctrl
& TWD_TIMER_CONTROL_PERIODIC
)) {
155 writel_relaxed(1, twd_base
+ TWD_TIMER_COUNTER
);
156 twd_ctrl
|= TWD_TIMER_CONTROL_ENABLE
;
157 writel_relaxed(twd_ctrl
, twd_base
+ TWD_TIMER_CONTROL
);
162 #ifdef CONFIG_CACHE_L2X0
164 void __iomem
*omap4_get_l2cache_base(void)
169 void omap4_l2c310_write_sec(unsigned long val
, unsigned reg
)
175 smc_op
= OMAP4_MON_L2X0_CTRL_INDEX
;
179 smc_op
= OMAP4_MON_L2X0_AUXCTRL_INDEX
;
182 case L2X0_DEBUG_CTRL
:
183 smc_op
= OMAP4_MON_L2X0_DBG_CTRL_INDEX
;
186 case L310_PREFETCH_CTRL
:
187 smc_op
= OMAP4_MON_L2X0_PREFETCH_INDEX
;
190 case L310_POWER_CTRL
:
191 pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
195 WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg
);
199 omap_smc1(smc_op
, val
);
202 int __init
omap_l2_cache_init(void)
204 /* Static mapping, never released */
205 l2cache_base
= ioremap(OMAP44XX_L2CACHE_BASE
, SZ_4K
);
206 if (WARN_ON(!l2cache_base
))
212 void __iomem
*omap4_get_sar_ram_base(void)
218 * SAR RAM used to save and restore the HW
219 * context in low power modes
221 static int __init
omap4_sar_ram_init(void)
223 unsigned long sar_base
;
226 * To avoid code running on other OMAPs in
229 if (cpu_is_omap44xx())
230 sar_base
= OMAP44XX_SAR_RAM_BASE
;
231 else if (soc_is_omap54xx())
232 sar_base
= OMAP54XX_SAR_RAM_BASE
;
236 /* Static mapping, never released */
237 sar_ram_base
= ioremap(sar_base
, SZ_16K
);
238 if (WARN_ON(!sar_ram_base
))
243 omap_early_initcall(omap4_sar_ram_init
);
245 static struct of_device_id gic_match
[] = {
246 { .compatible
= "arm,cortex-a9-gic", },
247 { .compatible
= "arm,cortex-a15-gic", },
251 static struct device_node
*gic_node
;
253 unsigned int omap4_xlate_irq(unsigned int hwirq
)
255 struct of_phandle_args irq_data
;
259 gic_node
= of_find_matching_node(NULL
, gic_match
);
261 if (WARN_ON(!gic_node
))
264 irq_data
.np
= gic_node
;
265 irq_data
.args_count
= 3;
266 irq_data
.args
[0] = 0;
267 irq_data
.args
[1] = hwirq
- OMAP44XX_IRQ_GIC_START
;
268 irq_data
.args
[2] = IRQ_TYPE_LEVEL_HIGH
;
270 irq
= irq_create_of_mapping(&irq_data
);
277 void __init
omap_gic_of_init(void)
279 struct device_node
*np
;
281 /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
282 if (!cpu_is_omap446x())
283 goto skip_errata_init
;
285 np
= of_find_compatible_node(NULL
, NULL
, "arm,cortex-a9-gic");
286 gic_dist_base_addr
= of_iomap(np
, 0);
287 WARN_ON(!gic_dist_base_addr
);
289 np
= of_find_compatible_node(NULL
, NULL
, "arm,cortex-a9-twd-timer");
290 twd_base
= of_iomap(np
, 0);
294 omap_wakeupgen_init();
295 #ifdef CONFIG_IRQ_CROSSBAR