arch/arm/mach-omap2/omap_hwmod.h

   1 /*
   2  * omap_hwmod macros, structures
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2011-2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * Created in collaboration with (alphabetical order): Benoît Cousson,
   9  * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
  10  * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  *
  16  * These headers and macros are used to define OMAP on-chip module
  17  * data and their integration with other OMAP modules and Linux.
  18  * Copious documentation and references can also be found in the
  19  * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
  20  * writing).
  21  *
  22  * To do:
  23  * - add interconnect error log structures
  24  * - init_conn_id_bit (CONNID_BIT_VECTOR)
  25  * - implement default hwmod SMS/SDRC flags?
  26  * - move Linux-specific data ("non-ROM data") out
  27  *
  28  */
  29 #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
  30 #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
  31
  32 #include <linux/kernel.h>
  33 #include <linux/init.h>
  34 #include <linux/list.h>
  35 #include <linux/ioport.h>
  36 #include <linux/spinlock.h>
  37
  38 struct omap_device;
  39
  40 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
  41 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
  42 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
  43
  44 /*
  45  * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
  46  * with the original PRCM protocol defined for OMAP2420
  47  */
  48 #define SYSC_TYPE1_MIDLEMODE_SHIFT      12
  49 #define SYSC_TYPE1_MIDLEMODE_MASK       (0x3 << SYSC_TYPE1_MIDLEMODE_SHIFT)
  50 #define SYSC_TYPE1_CLOCKACTIVITY_SHIFT  8
  51 #define SYSC_TYPE1_CLOCKACTIVITY_MASK   (0x3 << SYSC_TYPE1_CLOCKACTIVITY_SHIFT)
  52 #define SYSC_TYPE1_SIDLEMODE_SHIFT      3
  53 #define SYSC_TYPE1_SIDLEMODE_MASK       (0x3 << SYSC_TYPE1_SIDLEMODE_SHIFT)
  54 #define SYSC_TYPE1_ENAWAKEUP_SHIFT      2
  55 #define SYSC_TYPE1_ENAWAKEUP_MASK       (1 << SYSC_TYPE1_ENAWAKEUP_SHIFT)
  56 #define SYSC_TYPE1_SOFTRESET_SHIFT      1
  57 #define SYSC_TYPE1_SOFTRESET_MASK       (1 << SYSC_TYPE1_SOFTRESET_SHIFT)
  58 #define SYSC_TYPE1_AUTOIDLE_SHIFT       0
  59 #define SYSC_TYPE1_AUTOIDLE_MASK        (1 << SYSC_TYPE1_AUTOIDLE_SHIFT)
  60
  61 /*
  62  * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant
  63  * with the new PRCM protocol defined for new OMAP4 IPs.
  64  */
  65 #define SYSC_TYPE2_SOFTRESET_SHIFT      0
  66 #define SYSC_TYPE2_SOFTRESET_MASK       (1 << SYSC_TYPE2_SOFTRESET_SHIFT)
  67 #define SYSC_TYPE2_SIDLEMODE_SHIFT      2
  68 #define SYSC_TYPE2_SIDLEMODE_MASK       (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT)
  69 #define SYSC_TYPE2_MIDLEMODE_SHIFT      4
  70 #define SYSC_TYPE2_MIDLEMODE_MASK       (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)
  71 #define SYSC_TYPE2_DMADISABLE_SHIFT     16
  72 #define SYSC_TYPE2_DMADISABLE_MASK      (0x1 << SYSC_TYPE2_DMADISABLE_SHIFT)
  73
  74 /*
  75  * OCP SYSCONFIG bit shifts/masks TYPE3.
  76  * This is applicable for some IPs present in AM33XX
  77  */
  78 #define SYSC_TYPE3_SIDLEMODE_SHIFT      0
  79 #define SYSC_TYPE3_SIDLEMODE_MASK       (0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT)
  80 #define SYSC_TYPE3_MIDLEMODE_SHIFT      2
  81 #define SYSC_TYPE3_MIDLEMODE_MASK       (0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT)
  82
  83 /* OCP SYSSTATUS bit shifts/masks */
  84 #define SYSS_RESETDONE_SHIFT            0
  85 #define SYSS_RESETDONE_MASK             (1 << SYSS_RESETDONE_SHIFT)
  86
  87 /* Master standby/slave idle mode flags */
  88 #define HWMOD_IDLEMODE_FORCE            (1 << 0)
  89 #define HWMOD_IDLEMODE_NO               (1 << 1)
  90 #define HWMOD_IDLEMODE_SMART            (1 << 2)
  91 #define HWMOD_IDLEMODE_SMART_WKUP       (1 << 3)
  92
  93 /* modulemode control type (SW or HW) */
  94 #define MODULEMODE_HWCTRL               1
  95 #define MODULEMODE_SWCTRL               2
  96
  97 #define DEBUG_OMAP2UART1_FLAGS  0
  98 #define DEBUG_OMAP2UART2_FLAGS  0
  99 #define DEBUG_OMAP2UART3_FLAGS  0
 100 #define DEBUG_OMAP3UART3_FLAGS  0
 101 #define DEBUG_OMAP3UART4_FLAGS  0
 102 #define DEBUG_OMAP4UART3_FLAGS  0
 103 #define DEBUG_OMAP4UART4_FLAGS  0
 104 #define DEBUG_TI81XXUART1_FLAGS 0
 105 #define DEBUG_TI81XXUART2_FLAGS 0
 106 #define DEBUG_TI81XXUART3_FLAGS 0
 107 #define DEBUG_AM33XXUART1_FLAGS 0
 108
 109 #define DEBUG_OMAPUART_FLAGS    (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET)
 110
 111 #ifdef CONFIG_OMAP_GPMC_DEBUG
 112 #define DEBUG_OMAP_GPMC_HWMOD_FLAGS     HWMOD_INIT_NO_RESET
 113 #else
 114 #define DEBUG_OMAP_GPMC_HWMOD_FLAGS     0
 115 #endif
 116
 117 #if defined(CONFIG_DEBUG_OMAP2UART1)
 118 #undef DEBUG_OMAP2UART1_FLAGS
 119 #define DEBUG_OMAP2UART1_FLAGS DEBUG_OMAPUART_FLAGS
 120 #elif defined(CONFIG_DEBUG_OMAP2UART2)
 121 #undef DEBUG_OMAP2UART2_FLAGS
 122 #define DEBUG_OMAP2UART2_FLAGS DEBUG_OMAPUART_FLAGS
 123 #elif defined(CONFIG_DEBUG_OMAP2UART3)
 124 #undef DEBUG_OMAP2UART3_FLAGS
 125 #define DEBUG_OMAP2UART3_FLAGS DEBUG_OMAPUART_FLAGS
 126 #elif defined(CONFIG_DEBUG_OMAP3UART3)
 127 #undef DEBUG_OMAP3UART3_FLAGS
 128 #define DEBUG_OMAP3UART3_FLAGS DEBUG_OMAPUART_FLAGS
 129 #elif defined(CONFIG_DEBUG_OMAP3UART4)
 130 #undef DEBUG_OMAP3UART4_FLAGS
 131 #define DEBUG_OMAP3UART4_FLAGS DEBUG_OMAPUART_FLAGS
 132 #elif defined(CONFIG_DEBUG_OMAP4UART3)
 133 #undef DEBUG_OMAP4UART3_FLAGS
 134 #define DEBUG_OMAP4UART3_FLAGS DEBUG_OMAPUART_FLAGS
 135 #elif defined(CONFIG_DEBUG_OMAP4UART4)
 136 #undef DEBUG_OMAP4UART4_FLAGS
 137 #define DEBUG_OMAP4UART4_FLAGS DEBUG_OMAPUART_FLAGS
 138 #elif defined(CONFIG_DEBUG_TI81XXUART1)
 139 #undef DEBUG_TI81XXUART1_FLAGS
 140 #define DEBUG_TI81XXUART1_FLAGS DEBUG_OMAPUART_FLAGS
 141 #elif defined(CONFIG_DEBUG_TI81XXUART2)
 142 #undef DEBUG_TI81XXUART2_FLAGS
 143 #define DEBUG_TI81XXUART2_FLAGS DEBUG_OMAPUART_FLAGS
 144 #elif defined(CONFIG_DEBUG_TI81XXUART3)
 145 #undef DEBUG_TI81XXUART3_FLAGS
 146 #define DEBUG_TI81XXUART3_FLAGS DEBUG_OMAPUART_FLAGS
 147 #elif defined(CONFIG_DEBUG_AM33XXUART1)
 148 #undef DEBUG_AM33XXUART1_FLAGS
 149 #define DEBUG_AM33XXUART1_FLAGS DEBUG_OMAPUART_FLAGS
 150 #endif
 151
 152 /**
 153  * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
 154  * @name: name of the reset line (module local name)
 155  * @rst_shift: Offset of the reset bit
 156  * @st_shift: Offset of the reset status bit (OMAP2/3 only)
 157  *
 158  * @name should be something short, e.g., "cpu0" or "rst". It is defined
 159  * locally to the hwmod.
 160  */
 161 struct omap_hwmod_rst_info {
 162         const char      *name;
 163         u8              rst_shift;
 164         u8              st_shift;
 165 };
 166
 167 /**
 168  * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
 169  * @role: "sys", "32k", "tv", etc -- for use in clk_get()
 170  * @clk: opt clock: OMAP clock name
 171  * @_clk: pointer to the struct clk (filled in at runtime)
 172  *
 173  * The module's interface clock and main functional clock should not
 174  * be added as optional clocks.
 175  */
 176 struct omap_hwmod_opt_clk {
 177         const char      *role;
 178         const char      *clk;
 179         struct clk      *_clk;
 180 };
 181
 182
 183 /* omap_hwmod_omap2_firewall.flags bits */
 184 #define OMAP_FIREWALL_L3                (1 << 0)
 185 #define OMAP_FIREWALL_L4                (1 << 1)
 186
 187 /**
 188  * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
 189  * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
 190  * @l4_fw_region: L4 firewall region ID
 191  * @l4_prot_group: L4 protection group ID
 192  * @flags: (see omap_hwmod_omap2_firewall.flags macros above)
 193  */
 194 struct omap_hwmod_omap2_firewall {
 195         u8 l3_perm_bit;
 196         u8 l4_fw_region;
 197         u8 l4_prot_group;
 198         u8 flags;
 199 };
 200
 201 /*
 202  * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
 203  * interface to interact with the hwmod.  Used to add sleep dependencies
 204  * when the module is enabled or disabled.
 205  */
 206 #define OCP_USER_MPU                    (1 << 0)
 207 #define OCP_USER_SDMA                   (1 << 1)
 208 #define OCP_USER_DSP                    (1 << 2)
 209 #define OCP_USER_IVA                    (1 << 3)
 210
 211 /* omap_hwmod_ocp_if.flags bits */
 212 #define OCPIF_SWSUP_IDLE                (1 << 0)
 213 #define OCPIF_CAN_BURST                 (1 << 1)
 214
 215 /* omap_hwmod_ocp_if._int_flags possibilities */
 216 #define _OCPIF_INT_FLAGS_REGISTERED     (1 << 0)
 217
 218
 219 /**
 220  * struct omap_hwmod_ocp_if - OCP interface data
 221  * @master: struct omap_hwmod that initiates OCP transactions on this link
 222  * @slave: struct omap_hwmod that responds to OCP transactions on this link
 223  * @addr: address space associated with this link
 224  * @clk: interface clock: OMAP clock name
 225  * @_clk: pointer to the interface struct clk (filled in at runtime)
 226  * @fw: interface firewall data
 227  * @width: OCP data width
 228  * @user: initiators using this interface (see OCP_USER_* macros above)
 229  * @flags: OCP interface flags (see OCPIF_* macros above)
 230  * @_int_flags: internal flags (see _OCPIF_INT_FLAGS* macros above)
 231  *
 232  * It may also be useful to add a tag_cnt field for OCP2.x devices.
 233  *
 234  * Parameter names beginning with an underscore are managed internally by
 235  * the omap_hwmod code and should not be set during initialization.
 236  */
 237 struct omap_hwmod_ocp_if {
 238         struct omap_hwmod               *master;
 239         struct omap_hwmod               *slave;
 240         struct omap_hwmod_addr_space    *addr;
 241         const char                      *clk;
 242         struct clk                      *_clk;
 243         struct list_head                node;
 244         union {
 245                 struct omap_hwmod_omap2_firewall omap2;
 246         }                               fw;
 247         u8                              width;
 248         u8                              user;
 249         u8                              flags;
 250         u8                              _int_flags;
 251 };
 252
 253
 254 /* Macros for use in struct omap_hwmod_sysconfig */
 255
 256 /* Flags for use in omap_hwmod_sysconfig.idlemodes */
 257 #define MASTER_STANDBY_SHIFT    4
 258 #define SLAVE_IDLE_SHIFT        0
 259 #define SIDLE_FORCE             (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
 260 #define SIDLE_NO                (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
 261 #define SIDLE_SMART             (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
 262 #define SIDLE_SMART_WKUP        (HWMOD_IDLEMODE_SMART_WKUP << SLAVE_IDLE_SHIFT)
 263 #define MSTANDBY_FORCE          (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
 264 #define MSTANDBY_NO             (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
 265 #define MSTANDBY_SMART          (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
 266 #define MSTANDBY_SMART_WKUP     (HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT)
 267
 268 /* omap_hwmod_sysconfig.sysc_flags capability flags */
 269 #define SYSC_HAS_AUTOIDLE       (1 << 0)
 270 #define SYSC_HAS_SOFTRESET      (1 << 1)
 271 #define SYSC_HAS_ENAWAKEUP      (1 << 2)
 272 #define SYSC_HAS_EMUFREE        (1 << 3)
 273 #define SYSC_HAS_CLOCKACTIVITY  (1 << 4)
 274 #define SYSC_HAS_SIDLEMODE      (1 << 5)
 275 #define SYSC_HAS_MIDLEMODE      (1 << 6)
 276 #define SYSS_HAS_RESET_STATUS   (1 << 7)
 277 #define SYSC_NO_CACHE           (1 << 8)  /* XXX SW flag, belongs elsewhere */
 278 #define SYSC_HAS_RESET_STATUS   (1 << 9)
 279 #define SYSC_HAS_DMADISABLE     (1 << 10)
 280
 281 /* omap_hwmod_sysconfig.clockact flags */
 282 #define CLOCKACT_TEST_BOTH      0x0
 283 #define CLOCKACT_TEST_MAIN      0x1
 284 #define CLOCKACT_TEST_ICLK      0x2
 285 #define CLOCKACT_TEST_NONE      0x3
 286
 287 /**
 288  * struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets.
 289  * @midle_shift: Offset of the midle bit
 290  * @clkact_shift: Offset of the clockactivity bit
 291  * @sidle_shift: Offset of the sidle bit
 292  * @enwkup_shift: Offset of the enawakeup bit
 293  * @srst_shift: Offset of the softreset bit
 294  * @autoidle_shift: Offset of the autoidle bit
 295  * @dmadisable_shift: Offset of the dmadisable bit
 296  */
 297 struct omap_hwmod_sysc_fields {
 298         u8 midle_shift;
 299         u8 clkact_shift;
 300         u8 sidle_shift;
 301         u8 enwkup_shift;
 302         u8 srst_shift;
 303         u8 autoidle_shift;
 304         u8 dmadisable_shift;
 305 };
 306
 307 /**
 308  * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data
 309  * @rev_offs: IP block revision register offset (from module base addr)
 310  * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
 311  * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
 312  * @srst_udelay: Delay needed after doing a softreset in usecs
 313  * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
 314  * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
 315  * @clockact: the default value of the module CLOCKACTIVITY bits
 316  *
 317  * @clockact describes to the module which clocks are likely to be
 318  * disabled when the PRCM issues its idle request to the module.  Some
 319  * modules have separate clockdomains for the interface clock and main
 320  * functional clock, and can check whether they should acknowledge the
 321  * idle request based on the internal module functionality that has
 322  * been associated with the clocks marked in @clockact.  This field is
 323  * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
 324  *
 325  * @sysc_fields: structure containing the offset positions of various bits in
 326  * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or
 327  * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on
 328  * whether the device ip is compliant with the original PRCM protocol
 329  * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs.
 330  * If the device follows a different scheme for the sysconfig register ,
 331  * then this field has to be populated with the correct offset structure.
 332  */
 333 struct omap_hwmod_class_sysconfig {
 334         u32 rev_offs;
 335         u32 sysc_offs;
 336         u32 syss_offs;
 337         u16 sysc_flags;
 338         struct omap_hwmod_sysc_fields *sysc_fields;
 339         u8 srst_udelay;
 340         u8 idlemodes;
 341 };
 342
 343 /**
 344  * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
 345  * @module_offs: PRCM submodule offset from the start of the PRM/CM
 346  * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
 347  * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
 348  * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
 349  * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
 350  * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
 351  *
 352  * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
 353  * WKEN, GRPSEL registers.  In an ideal world, no extra information
 354  * would be needed for IDLEST information, but alas, there are some
 355  * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
 356  * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
 357  */
 358 struct omap_hwmod_omap2_prcm {
 359         s16 module_offs;
 360         u8 prcm_reg_id;
 361         u8 module_bit;
 362         u8 idlest_reg_id;
 363         u8 idlest_idle_bit;
 364         u8 idlest_stdby_bit;
 365 };
 366
 367 /*
 368  * Possible values for struct omap_hwmod_omap4_prcm.flags
 369  *
 370  * HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT: Some IP blocks don't have a PRCM
 371  *     module-level context loss register associated with them; this
 372  *     flag bit should be set in those cases
 373  * HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET: Some IP blocks have a valid CLKCTRL
 374  *      offset of zero; this flag bit should be set in those cases to
 375  *      distinguish from hwmods that have no clkctrl offset.
 376  * HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK: Module clockctrl clock is managed
 377  *      by the common clock framework and not hwmod.
 378  */
 379 #define HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT         (1 << 0)
 380 #define HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET         (1 << 1)
 381 #define HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK         (1 << 2)
 382
 383 /**
 384  * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
 385  * @clkctrl_offs: offset of the PRCM clock control register
 386  * @rstctrl_offs: offset of the XXX_RSTCTRL register located in the PRM
 387  * @context_offs: offset of the RM_*_CONTEXT register
 388  * @lostcontext_mask: bitmask for selecting bits from RM_*_CONTEXT register
 389  * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM
 390  * @submodule_wkdep_bit: bit shift of the WKDEP range
 391  * @flags: PRCM register capabilities for this IP block
 392  * @modulemode: allowable modulemodes
 393  * @context_lost_counter: Count of module level context lost
 394  *
 395  * If @lostcontext_mask is not defined, context loss check code uses
 396  * whole register without masking. @lostcontext_mask should only be
 397  * defined in cases where @context_offs register is shared by two or
 398  * more hwmods.
 399  */
 400 struct omap_hwmod_omap4_prcm {
 401         u16             clkctrl_offs;
 402         u16             rstctrl_offs;
 403         u16             rstst_offs;
 404         u16             context_offs;
 405         u32             lostcontext_mask;
 406         u8              submodule_wkdep_bit;
 407         u8              modulemode;
 408         u8              flags;
 409         int             context_lost_counter;
 410 };
 411
 412
 413 /*
 414  * omap_hwmod.flags definitions
 415  *
 416  * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
 417  *     of idle, rather than relying on module smart-idle
 418  * HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and
 419  *     out of standby, rather than relying on module smart-standby
 420  * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
 421  *     SDRAM controller, etc. XXX probably belongs outside the main hwmod file
 422  *     XXX Should be HWMOD_SETUP_NO_RESET
 423  * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
 424  *     controller, etc. XXX probably belongs outside the main hwmod file
 425  *     XXX Should be HWMOD_SETUP_NO_IDLE
 426  * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
 427  *     when module is enabled, rather than the default, which is to
 428  *     enable autoidle
 429  * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
 430  * HWMOD_NO_IDLEST: this module does not have idle status - this is the case
 431  *     only for few initiator modules on OMAP2 & 3.
 432  * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset.
 433  *     This is needed for devices like DSS that require optional clocks enabled
 434  *     in order to complete the reset. Optional clocks will be disabled
 435  *     again after the reset.
 436  * HWMOD_16BIT_REG: Module has 16bit registers
 437  * HWMOD_EXT_OPT_MAIN_CLK: The only main functional clock source for
 438  *     this IP block comes from an off-chip source and is not always
 439  *     enabled.  This prevents the hwmod code from being able to
 440  *     enable and reset the IP block early.  XXX Eventually it should
 441  *     be possible to query the clock framework for this information.
 442  * HWMOD_BLOCK_WFI: Some OMAP peripherals apparently don't work
 443  *     correctly if the MPU is allowed to go idle while the
 444  *     peripherals are active.  This is apparently true for the I2C on
 445  *     OMAP2420, and also the EMAC on AM3517/3505.  It's unlikely that
 446  *     this is really true -- we're probably not configuring something
 447  *     correctly, or this is being abused to deal with some PM latency
 448  *     issues -- but we're currently suffering from a shortage of
 449  *     folks who are able to track these issues down properly.
 450  * HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device
 451  *     is kept in force-standby mode. Failing to do so causes PM problems
 452  *     with musb on OMAP3630 at least. Note that musb has a dedicated register
 453  *     to control MSTANDBY signal when MIDLEMODE is set to force-standby.
 454  * HWMOD_SWSUP_SIDLE_ACT: omap_hwmod code should manually bring the module
 455  *     out of idle, but rely on smart-idle to the put it back in idle,
 456  *     so the wakeups are still functional (Only known case for now is UART)
 457  * HWMOD_RECONFIG_IO_CHAIN: omap_hwmod code needs to reconfigure wake-up
 458  *     events by calling _reconfigure_io_chain() when a device is enabled
 459  *     or idled.
 460  * HWMOD_OPT_CLKS_NEEDED: The optional clocks are needed for the module to
 461  *     operate and they need to be handled at the same time as the main_clk.
 462  * HWMOD_NO_IDLE: Do not idle the hwmod at all. Useful to handle certain
 463  *     IPs like CPSW on DRA7, where clocks to this module cannot be disabled.
 464  * HWMOD_CLKDM_NOAUTO: Allows the hwmod's clockdomain to be prevented from
 465  *     entering HW_AUTO while hwmod is active. This is needed to workaround
 466  *     some modules which don't function correctly with HW_AUTO. For example,
 467  *     DCAN on DRA7x SoC needs this to workaround errata i893.
 468  */
 469 #define HWMOD_SWSUP_SIDLE                       (1 << 0)
 470 #define HWMOD_SWSUP_MSTANDBY                    (1 << 1)
 471 #define HWMOD_INIT_NO_RESET                     (1 << 2)
 472 #define HWMOD_INIT_NO_IDLE                      (1 << 3)
 473 #define HWMOD_NO_OCP_AUTOIDLE                   (1 << 4)
 474 #define HWMOD_SET_DEFAULT_CLOCKACT              (1 << 5)
 475 #define HWMOD_NO_IDLEST                         (1 << 6)
 476 #define HWMOD_CONTROL_OPT_CLKS_IN_RESET         (1 << 7)
 477 #define HWMOD_16BIT_REG                         (1 << 8)
 478 #define HWMOD_EXT_OPT_MAIN_CLK                  (1 << 9)
 479 #define HWMOD_BLOCK_WFI                         (1 << 10)
 480 #define HWMOD_FORCE_MSTANDBY                    (1 << 11)
 481 #define HWMOD_SWSUP_SIDLE_ACT                   (1 << 12)
 482 #define HWMOD_RECONFIG_IO_CHAIN                 (1 << 13)
 483 #define HWMOD_OPT_CLKS_NEEDED                   (1 << 14)
 484 #define HWMOD_NO_IDLE                           (1 << 15)
 485 #define HWMOD_CLKDM_NOAUTO                      (1 << 16)
 486
 487 /*
 488  * omap_hwmod._int_flags definitions
 489  * These are for internal use only and are managed by the omap_hwmod code.
 490  *
 491  * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
 492  * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
 493  * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) -
 494  *     causes the first call to _enable() to only update the pinmux
 495  */
 496 #define _HWMOD_NO_MPU_PORT                      (1 << 0)
 497 #define _HWMOD_SYSCONFIG_LOADED                 (1 << 1)
 498 #define _HWMOD_SKIP_ENABLE                      (1 << 2)
 499
 500 /*
 501  * omap_hwmod._state definitions
 502  *
 503  * INITIALIZED: reset (optionally), initialized, enabled, disabled
 504  *              (optionally)
 505  *
 506  *
 507  */
 508 #define _HWMOD_STATE_UNKNOWN                    0
 509 #define _HWMOD_STATE_REGISTERED                 1
 510 #define _HWMOD_STATE_CLKS_INITED                2
 511 #define _HWMOD_STATE_INITIALIZED                3
 512 #define _HWMOD_STATE_ENABLED                    4
 513 #define _HWMOD_STATE_IDLE                       5
 514 #define _HWMOD_STATE_DISABLED                   6
 515
 516 /**
 517  * struct omap_hwmod_class - the type of an IP block
 518  * @name: name of the hwmod_class
 519  * @sysc: device SYSCONFIG/SYSSTATUS register data
 520  * @rev: revision of the IP class
 521  * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
 522  * @reset: ptr to fn to be executed in place of the standard hwmod reset fn
 523  * @enable_preprogram:  ptr to fn to be executed during device enable
 524  * @lock: ptr to fn to be executed to lock IP registers
 525  * @unlock: ptr to fn to be executed to unlock IP registers
 526  *
 527  * Represent the class of a OMAP hardware "modules" (e.g. timer,
 528  * smartreflex, gpio, uart...)
 529  *
 530  * @pre_shutdown is a function that will be run immediately before
 531  * hwmod clocks are disabled, etc.  It is intended for use for hwmods
 532  * like the MPU watchdog, which cannot be disabled with the standard
 533  * omap_hwmod_shutdown().  The function should return 0 upon success,
 534  * or some negative error upon failure.  Returning an error will cause
 535  * omap_hwmod_shutdown() to abort the device shutdown and return an
 536  * error.
 537  *
 538  * If @reset is defined, then the function it points to will be
 539  * executed in place of the standard hwmod _reset() code in
 540  * mach-omap2/omap_hwmod.c.  This is needed for IP blocks which have
 541  * unusual reset sequences - usually processor IP blocks like the IVA.
 542  */
 543 struct omap_hwmod_class {
 544         const char                              *name;
 545         struct omap_hwmod_class_sysconfig       *sysc;
 546         u32                                     rev;
 547         int                                     (*pre_shutdown)(struct omap_hwmod *oh);
 548         int                                     (*reset)(struct omap_hwmod *oh);
 549         int                                     (*enable_preprogram)(struct omap_hwmod *oh);
 550         void                                    (*lock)(struct omap_hwmod *oh);
 551         void                                    (*unlock)(struct omap_hwmod *oh);
 552 };
 553
 554 /**
 555  * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
 556  * @name: name of the hwmod
 557  * @class: struct omap_hwmod_class * to the class of this hwmod
 558  * @od: struct omap_device currently associated with this hwmod (internal use)
 559  * @prcm: PRCM data pertaining to this hwmod
 560  * @main_clk: main clock: OMAP clock name
 561  * @_clk: pointer to the main struct clk (filled in at runtime)
 562  * @opt_clks: other device clocks that drivers can request (0..*)
 563  * @voltdm: pointer to voltage domain (filled in at runtime)
 564  * @dev_attr: arbitrary device attributes that can be passed to the driver
 565  * @_sysc_cache: internal-use hwmod flags
 566  * @mpu_rt_idx: index of device address space for register target (for DT boot)
 567  * @_mpu_rt_va: cached register target start address (internal use)
 568  * @_mpu_port: cached MPU register target slave (internal use)
 569  * @opt_clks_cnt: number of @opt_clks
 570  * @master_cnt: number of @master entries
 571  * @slaves_cnt: number of @slave entries
 572  * @response_lat: device OCP response latency (in interface clock cycles)
 573  * @_int_flags: internal-use hwmod flags
 574  * @_state: internal-use hwmod state
 575  * @_postsetup_state: internal-use state to leave the hwmod in after _setup()
 576  * @flags: hwmod flags (documented below)
 577  * @_lock: spinlock serializing operations on this hwmod
 578  * @node: list node for hwmod list (internal use)
 579  * @parent_hwmod: (temporary) a pointer to the hierarchical parent of this hwmod
 580  *
 581  * @main_clk refers to this module's "main clock," which for our
 582  * purposes is defined as "the functional clock needed for register
 583  * accesses to complete."  Modules may not have a main clock if the
 584  * interface clock also serves as a main clock.
 585  *
 586  * Parameter names beginning with an underscore are managed internally by
 587  * the omap_hwmod code and should not be set during initialization.
 588  *
 589  * @masters and @slaves are now deprecated.
 590  *
 591  * @parent_hwmod is temporary; there should be no need for it, as this
 592  * information should already be expressed in the OCP interface
 593  * structures.  @parent_hwmod is present as a workaround until we improve
 594  * handling for hwmods with multiple parents (e.g., OMAP4+ DSS with
 595  * multiple register targets across different interconnects).
 596  */
 597 struct omap_hwmod {
 598         const char                      *name;
 599         struct omap_hwmod_class         *class;
 600         struct omap_device              *od;
 601         struct omap_hwmod_rst_info      *rst_lines;
 602         union {
 603                 struct omap_hwmod_omap2_prcm omap2;
 604                 struct omap_hwmod_omap4_prcm omap4;
 605         }                               prcm;
 606         const char                      *main_clk;
 607         struct clk                      *_clk;
 608         struct omap_hwmod_opt_clk       *opt_clks;
 609         const char                      *clkdm_name;
 610         struct clockdomain              *clkdm;
 611         struct list_head                slave_ports; /* connect to *_TA */
 612         void                            *dev_attr;
 613         u32                             _sysc_cache;
 614         void __iomem                    *_mpu_rt_va;
 615         spinlock_t                      _lock;
 616         struct lock_class_key           hwmod_key; /* unique lock class */
 617         struct list_head                node;
 618         struct omap_hwmod_ocp_if        *_mpu_port;
 619         u32                             flags;
 620         u8                              mpu_rt_idx;
 621         u8                              response_lat;
 622         u8                              rst_lines_cnt;
 623         u8                              opt_clks_cnt;
 624         u8                              slaves_cnt;
 625         u8                              hwmods_cnt;
 626         u8                              _int_flags;
 627         u8                              _state;
 628         u8                              _postsetup_state;
 629         struct omap_hwmod               *parent_hwmod;
 630 };
 631
 632 struct device_node;
 633
 634 struct omap_hwmod *omap_hwmod_lookup(const char *name);
 635 int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
 636                         void *data);
 637
 638 int __init omap_hwmod_setup_one(const char *name);
 639 int omap_hwmod_parse_module_range(struct omap_hwmod *oh,
 640                                   struct device_node *np,
 641                                   struct resource *res);
 642
 643 int omap_hwmod_enable(struct omap_hwmod *oh);
 644 int omap_hwmod_idle(struct omap_hwmod *oh);
 645 int omap_hwmod_shutdown(struct omap_hwmod *oh);
 646
 647 int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
 648 int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name);
 649
 650 void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
 651 u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
 652 int omap_hwmod_softreset(struct omap_hwmod *oh);
 653
 654 int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags);
 655 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
 656 int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
 657                                    const char *name, struct resource *res);
 658
 659 struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
 660 void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
 661
 662 int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
 663 int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
 664
 665 int omap_hwmod_for_each_by_class(const char *classname,
 666                                  int (*fn)(struct omap_hwmod *oh,
 667                                            void *user),
 668                                  void *user);
 669
 670 int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
 671 int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
 672
 673 extern void __init omap_hwmod_init(void);
 674
 675 const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
 676
 677 /*
 678  *
 679  */
 680
 681 extern int omap_hwmod_aess_preprogram(struct omap_hwmod *oh);
 682 void omap_hwmod_rtc_unlock(struct omap_hwmod *oh);
 683 void omap_hwmod_rtc_lock(struct omap_hwmod *oh);
 684
 685 /*
 686  * Chip variant-specific hwmod init routines - XXX should be converted
 687  * to use initcalls once the initial boot ordering is straightened out
 688  */
 689 extern int omap2420_hwmod_init(void);
 690 extern int omap2430_hwmod_init(void);
 691 extern int omap3xxx_hwmod_init(void);
 692 extern int omap44xx_hwmod_init(void);
 693 extern int omap54xx_hwmod_init(void);
 694 extern int am33xx_hwmod_init(void);
 695 extern int dm814x_hwmod_init(void);
 696 extern int dm816x_hwmod_init(void);
 697 extern int dra7xx_hwmod_init(void);
 698 int am43xx_hwmod_init(void);
 699
 700 extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
 701
 702 #endif