arch/arm/mach-omap2/omap_hwmod_2420_data.c

   1 /*
   2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * XXX handle crossbar/shared link difference for L3?
  13  * XXX these should be marked initdata for multi-OMAP kernels
  14  */
  15
  16 #include <linux/i2c-omap.h>
  17 #include <linux/platform_data/spi-omap2-mcspi.h>
  18 #include <linux/omap-dma.h>
  19 #include <plat/dmtimer.h>
  20
  21 #include "omap_hwmod.h"
  22 #include "l3_2xxx.h"
  23 #include "l4_2xxx.h"
  24
  25 #include "omap_hwmod_common_data.h"
  26
  27 #include "cm-regbits-24xx.h"
  28 #include "prm-regbits-24xx.h"
  29 #include "i2c.h"
  30 #include "mmc.h"
  31 #include "serial.h"
  32 #include "wd_timer.h"
  33
  34 /*
  35  * OMAP2420 hardware module integration data
  36  *
  37  * All of the data in this section should be autogeneratable from the
  38  * TI hardware database or other technical documentation.  Data that
  39  * is driver-specific or driver-kernel integration-specific belongs
  40  * elsewhere.
  41  */
  42
  43 /*
  44  * IP blocks
  45  */
  46
  47 /* IVA1 (IVA1) */
  48 static struct omap_hwmod_class iva1_hwmod_class = {
  49         .name           = "iva1",
  50 };
  51
  52 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
  53         { .name = "iva", .rst_shift = 8 },
  54 };
  55
  56 static struct omap_hwmod omap2420_iva_hwmod = {
  57         .name           = "iva",
  58         .class          = &iva1_hwmod_class,
  59         .clkdm_name     = "iva1_clkdm",
  60         .rst_lines      = omap2420_iva_resets,
  61         .rst_lines_cnt  = ARRAY_SIZE(omap2420_iva_resets),
  62         .main_clk       = "iva1_ifck",
  63 };
  64
  65 /* DSP */
  66 static struct omap_hwmod_class dsp_hwmod_class = {
  67         .name           = "dsp",
  68 };
  69
  70 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
  71         { .name = "logic", .rst_shift = 0 },
  72         { .name = "mmu", .rst_shift = 1 },
  73 };
  74
  75 static struct omap_hwmod omap2420_dsp_hwmod = {
  76         .name           = "dsp",
  77         .class          = &dsp_hwmod_class,
  78         .clkdm_name     = "dsp_clkdm",
  79         .rst_lines      = omap2420_dsp_resets,
  80         .rst_lines_cnt  = ARRAY_SIZE(omap2420_dsp_resets),
  81         .main_clk       = "dsp_fck",
  82 };
  83
  84 /* I2C common */
  85 static struct omap_hwmod_class_sysconfig i2c_sysc = {
  86         .rev_offs       = 0x00,
  87         .sysc_offs      = 0x20,
  88         .syss_offs      = 0x10,
  89         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  90         .sysc_fields    = &omap_hwmod_sysc_type1,
  91 };
  92
  93 static struct omap_hwmod_class i2c_class = {
  94         .name           = "i2c",
  95         .sysc           = &i2c_sysc,
  96         .rev            = OMAP_I2C_IP_VERSION_1,
  97         .reset          = &omap_i2c_reset,
  98 };
  99
 100 static struct omap_i2c_dev_attr i2c_dev_attr = {
 101         .flags          = OMAP_I2C_FLAG_NO_FIFO |
 102                           OMAP_I2C_FLAG_SIMPLE_CLOCK |
 103                           OMAP_I2C_FLAG_16BIT_DATA_REG |
 104                           OMAP_I2C_FLAG_BUS_SHIFT_2,
 105 };
 106
 107 /* I2C1 */
 108 static struct omap_hwmod omap2420_i2c1_hwmod = {
 109         .name           = "i2c1",
 110         .main_clk       = "i2c1_fck",
 111         .prcm           = {
 112                 .omap2 = {
 113                         .module_offs = CORE_MOD,
 114                         .prcm_reg_id = 1,
 115                         .module_bit = OMAP2420_EN_I2C1_SHIFT,
 116                         .idlest_reg_id = 1,
 117                         .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
 118                 },
 119         },
 120         .class          = &i2c_class,
 121         .dev_attr       = &i2c_dev_attr,
 122         /*
 123          * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
 124          * while a transfer is active seems to cause the I2C block to
 125          * timeout. Why? Good question."
 126          */
 127         .flags          = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
 128 };
 129
 130 /* I2C2 */
 131 static struct omap_hwmod omap2420_i2c2_hwmod = {
 132         .name           = "i2c2",
 133         .main_clk       = "i2c2_fck",
 134         .prcm           = {
 135                 .omap2 = {
 136                         .module_offs = CORE_MOD,
 137                         .prcm_reg_id = 1,
 138                         .module_bit = OMAP2420_EN_I2C2_SHIFT,
 139                         .idlest_reg_id = 1,
 140                         .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
 141                 },
 142         },
 143         .class          = &i2c_class,
 144         .dev_attr       = &i2c_dev_attr,
 145         .flags          = HWMOD_16BIT_REG,
 146 };
 147
 148 /* dma attributes */
 149 static struct omap_dma_dev_attr dma_dev_attr = {
 150         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 151                                                 IS_CSSA_32 | IS_CDSA_32,
 152         .lch_count = 32,
 153 };
 154
 155 static struct omap_hwmod omap2420_dma_system_hwmod = {
 156         .name           = "dma",
 157         .class          = &omap2xxx_dma_hwmod_class,
 158         .main_clk       = "core_l3_ck",
 159         .dev_attr       = &dma_dev_attr,
 160         .flags          = HWMOD_NO_IDLEST,
 161 };
 162
 163 /* mailbox */
 164 static struct omap_hwmod omap2420_mailbox_hwmod = {
 165         .name           = "mailbox",
 166         .class          = &omap2xxx_mailbox_hwmod_class,
 167         .main_clk       = "mailboxes_ick",
 168         .prcm           = {
 169                 .omap2 = {
 170                         .prcm_reg_id = 1,
 171                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
 172                         .module_offs = CORE_MOD,
 173                         .idlest_reg_id = 1,
 174                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
 175                 },
 176         },
 177 };
 178
 179 /*
 180  * 'mcbsp' class
 181  * multi channel buffered serial port controller
 182  */
 183
 184 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
 185         .name = "mcbsp",
 186 };
 187
 188 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
 189         { .role = "pad_fck", .clk = "mcbsp_clks" },
 190         { .role = "prcm_fck", .clk = "func_96m_ck" },
 191 };
 192
 193 /* mcbsp1 */
 194 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
 195         .name           = "mcbsp1",
 196         .class          = &omap2420_mcbsp_hwmod_class,
 197         .main_clk       = "mcbsp1_fck",
 198         .prcm           = {
 199                 .omap2 = {
 200                         .prcm_reg_id = 1,
 201                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
 202                         .module_offs = CORE_MOD,
 203                         .idlest_reg_id = 1,
 204                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
 205                 },
 206         },
 207         .opt_clks       = mcbsp_opt_clks,
 208         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 209 };
 210
 211 /* mcbsp2 */
 212 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
 213         .name           = "mcbsp2",
 214         .class          = &omap2420_mcbsp_hwmod_class,
 215         .main_clk       = "mcbsp2_fck",
 216         .prcm           = {
 217                 .omap2 = {
 218                         .prcm_reg_id = 1,
 219                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
 220                         .module_offs = CORE_MOD,
 221                         .idlest_reg_id = 1,
 222                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
 223                 },
 224         },
 225         .opt_clks       = mcbsp_opt_clks,
 226         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 227 };
 228
 229 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
 230         .rev_offs       = 0x3c,
 231         .sysc_offs      = 0x64,
 232         .syss_offs      = 0x68,
 233         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 234         .sysc_fields    = &omap_hwmod_sysc_type1,
 235 };
 236
 237 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
 238         .name   = "msdi",
 239         .sysc   = &omap2420_msdi_sysc,
 240         .reset  = &omap_msdi_reset,
 241 };
 242
 243 /* msdi1 */
 244 static struct omap_hwmod omap2420_msdi1_hwmod = {
 245         .name           = "msdi1",
 246         .class          = &omap2420_msdi_hwmod_class,
 247         .main_clk       = "mmc_fck",
 248         .prcm           = {
 249                 .omap2 = {
 250                         .prcm_reg_id = 1,
 251                         .module_bit = OMAP2420_EN_MMC_SHIFT,
 252                         .module_offs = CORE_MOD,
 253                         .idlest_reg_id = 1,
 254                         .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
 255                 },
 256         },
 257         .flags          = HWMOD_16BIT_REG,
 258 };
 259
 260 /* HDQ1W/1-wire */
 261 static struct omap_hwmod omap2420_hdq1w_hwmod = {
 262         .name           = "hdq1w",
 263         .main_clk       = "hdq_fck",
 264         .prcm           = {
 265                 .omap2 = {
 266                         .module_offs = CORE_MOD,
 267                         .prcm_reg_id = 1,
 268                         .module_bit = OMAP24XX_EN_HDQ_SHIFT,
 269                         .idlest_reg_id = 1,
 270                         .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
 271                 },
 272         },
 273         .class          = &omap2_hdq1w_class,
 274 };
 275
 276 /*
 277  * interfaces
 278  */
 279
 280 /* L4 CORE -> I2C1 interface */
 281 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
 282         .master         = &omap2xxx_l4_core_hwmod,
 283         .slave          = &omap2420_i2c1_hwmod,
 284         .clk            = "i2c1_ick",
 285         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 286 };
 287
 288 /* L4 CORE -> I2C2 interface */
 289 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
 290         .master         = &omap2xxx_l4_core_hwmod,
 291         .slave          = &omap2420_i2c2_hwmod,
 292         .clk            = "i2c2_ick",
 293         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 294 };
 295
 296 /* IVA <- L3 interface */
 297 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
 298         .master         = &omap2xxx_l3_main_hwmod,
 299         .slave          = &omap2420_iva_hwmod,
 300         .clk            = "core_l3_ck",
 301         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 302 };
 303
 304 /* DSP <- L3 interface */
 305 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
 306         .master         = &omap2xxx_l3_main_hwmod,
 307         .slave          = &omap2420_dsp_hwmod,
 308         .clk            = "dsp_ick",
 309         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 310 };
 311
 312 /* l4_wkup -> timer1 */
 313 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
 314         .master         = &omap2xxx_l4_wkup_hwmod,
 315         .slave          = &omap2xxx_timer1_hwmod,
 316         .clk            = "gpt1_ick",
 317         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 318 };
 319
 320 /* l4_wkup -> wd_timer2 */
 321 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 322         .master         = &omap2xxx_l4_wkup_hwmod,
 323         .slave          = &omap2xxx_wd_timer2_hwmod,
 324         .clk            = "mpu_wdt_ick",
 325         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 326 };
 327
 328 /* l4_wkup -> gpio1 */
 329 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
 330         .master         = &omap2xxx_l4_wkup_hwmod,
 331         .slave          = &omap2xxx_gpio1_hwmod,
 332         .clk            = "gpios_ick",
 333         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 334 };
 335
 336 /* l4_wkup -> gpio2 */
 337 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
 338         .master         = &omap2xxx_l4_wkup_hwmod,
 339         .slave          = &omap2xxx_gpio2_hwmod,
 340         .clk            = "gpios_ick",
 341         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 342 };
 343
 344 /* l4_wkup -> gpio3 */
 345 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
 346         .master         = &omap2xxx_l4_wkup_hwmod,
 347         .slave          = &omap2xxx_gpio3_hwmod,
 348         .clk            = "gpios_ick",
 349         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 350 };
 351
 352 /* l4_wkup -> gpio4 */
 353 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
 354         .master         = &omap2xxx_l4_wkup_hwmod,
 355         .slave          = &omap2xxx_gpio4_hwmod,
 356         .clk            = "gpios_ick",
 357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 358 };
 359
 360 /* dma_system -> L3 */
 361 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
 362         .master         = &omap2420_dma_system_hwmod,
 363         .slave          = &omap2xxx_l3_main_hwmod,
 364         .clk            = "core_l3_ck",
 365         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 366 };
 367
 368 /* l4_core -> dma_system */
 369 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
 370         .master         = &omap2xxx_l4_core_hwmod,
 371         .slave          = &omap2420_dma_system_hwmod,
 372         .clk            = "sdma_ick",
 373         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 374 };
 375
 376 /* l4_core -> mailbox */
 377 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
 378         .master         = &omap2xxx_l4_core_hwmod,
 379         .slave          = &omap2420_mailbox_hwmod,
 380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 381 };
 382
 383 /* l4_core -> mcbsp1 */
 384 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
 385         .master         = &omap2xxx_l4_core_hwmod,
 386         .slave          = &omap2420_mcbsp1_hwmod,
 387         .clk            = "mcbsp1_ick",
 388         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 389 };
 390
 391 /* l4_core -> mcbsp2 */
 392 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
 393         .master         = &omap2xxx_l4_core_hwmod,
 394         .slave          = &omap2420_mcbsp2_hwmod,
 395         .clk            = "mcbsp2_ick",
 396         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 397 };
 398
 399 /* l4_core -> msdi1 */
 400 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
 401         .master         = &omap2xxx_l4_core_hwmod,
 402         .slave          = &omap2420_msdi1_hwmod,
 403         .clk            = "mmc_ick",
 404         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 405 };
 406
 407 /* l4_core -> hdq1w interface */
 408 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
 409         .master         = &omap2xxx_l4_core_hwmod,
 410         .slave          = &omap2420_hdq1w_hwmod,
 411         .clk            = "hdq_ick",
 412         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 413         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
 414 };
 415
 416
 417 /* l4_wkup -> 32ksync_counter */
 418 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
 419         .master         = &omap2xxx_l4_wkup_hwmod,
 420         .slave          = &omap2xxx_counter_32k_hwmod,
 421         .clk            = "sync_32k_ick",
 422         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 423 };
 424
 425 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
 426         .master         = &omap2xxx_l3_main_hwmod,
 427         .slave          = &omap2xxx_gpmc_hwmod,
 428         .clk            = "core_l3_ck",
 429         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 430 };
 431
 432 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
 433         &omap2xxx_l3_main__l4_core,
 434         &omap2xxx_mpu__l3_main,
 435         &omap2xxx_dss__l3,
 436         &omap2xxx_l4_core__mcspi1,
 437         &omap2xxx_l4_core__mcspi2,
 438         &omap2xxx_l4_core__l4_wkup,
 439         &omap2_l4_core__uart1,
 440         &omap2_l4_core__uart2,
 441         &omap2_l4_core__uart3,
 442         &omap2420_l4_core__i2c1,
 443         &omap2420_l4_core__i2c2,
 444         &omap2420_l3__iva,
 445         &omap2420_l3__dsp,
 446         &omap2420_l4_wkup__timer1,
 447         &omap2xxx_l4_core__timer2,
 448         &omap2xxx_l4_core__timer3,
 449         &omap2xxx_l4_core__timer4,
 450         &omap2xxx_l4_core__timer5,
 451         &omap2xxx_l4_core__timer6,
 452         &omap2xxx_l4_core__timer7,
 453         &omap2xxx_l4_core__timer8,
 454         &omap2xxx_l4_core__timer9,
 455         &omap2xxx_l4_core__timer10,
 456         &omap2xxx_l4_core__timer11,
 457         &omap2xxx_l4_core__timer12,
 458         &omap2420_l4_wkup__wd_timer2,
 459         &omap2xxx_l4_core__dss,
 460         &omap2xxx_l4_core__dss_dispc,
 461         &omap2xxx_l4_core__dss_rfbi,
 462         &omap2xxx_l4_core__dss_venc,
 463         &omap2420_l4_wkup__gpio1,
 464         &omap2420_l4_wkup__gpio2,
 465         &omap2420_l4_wkup__gpio3,
 466         &omap2420_l4_wkup__gpio4,
 467         &omap2420_dma_system__l3,
 468         &omap2420_l4_core__dma_system,
 469         &omap2420_l4_core__mailbox,
 470         &omap2420_l4_core__mcbsp1,
 471         &omap2420_l4_core__mcbsp2,
 472         &omap2420_l4_core__msdi1,
 473         &omap2xxx_l4_core__rng,
 474         &omap2xxx_l4_core__sham,
 475         &omap2xxx_l4_core__aes,
 476         &omap2420_l4_core__hdq1w,
 477         &omap2420_l4_wkup__counter_32k,
 478         &omap2420_l3__gpmc,
 479         NULL,
 480 };
 481
 482 int __init omap2420_hwmod_init(void)
 483 {
 484         omap_hwmod_init();
 485         return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
 486 }