arch/arm/mach-omap2/omap_hwmod_2420_data.c

   1 /*
   2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * XXX handle crossbar/shared link difference for L3?
  13  * XXX these should be marked initdata for multi-OMAP kernels
  14  */
  15 #include <plat/omap_hwmod.h>
  16 #include <mach/irqs.h>
  17 #include <plat/cpu.h>
  18 #include <plat/dma.h>
  19 #include <plat/serial.h>
  20 #include <plat/i2c.h>
  21 #include <plat/gpio.h>
  22 #include <plat/mcspi.h>
  23 #include <plat/dmtimer.h>
  24 #include <plat/l3_2xxx.h>
  25 #include <plat/l4_2xxx.h>
  26 #include <plat/mmc.h>
  27
  28 #include "omap_hwmod_common_data.h"
  29
  30 #include "cm-regbits-24xx.h"
  31 #include "prm-regbits-24xx.h"
  32 #include "wd_timer.h"
  33
  34 /*
  35  * OMAP2420 hardware module integration data
  36  *
  37  * All of the data in this section should be autogeneratable from the
  38  * TI hardware database or other technical documentation.  Data that
  39  * is driver-specific or driver-kernel integration-specific belongs
  40  * elsewhere.
  41  */
  42
  43 /*
  44  * IP blocks
  45  */
  46
  47 /* IVA1 (IVA1) */
  48 static struct omap_hwmod_class iva1_hwmod_class = {
  49         .name           = "iva1",
  50 };
  51
  52 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
  53         { .name = "iva", .rst_shift = 8 },
  54 };
  55
  56 static struct omap_hwmod omap2420_iva_hwmod = {
  57         .name           = "iva",
  58         .class          = &iva1_hwmod_class,
  59         .clkdm_name     = "iva1_clkdm",
  60         .rst_lines      = omap2420_iva_resets,
  61         .rst_lines_cnt  = ARRAY_SIZE(omap2420_iva_resets),
  62         .main_clk       = "iva1_ifck",
  63 };
  64
  65 /* DSP */
  66 static struct omap_hwmod_class dsp_hwmod_class = {
  67         .name           = "dsp",
  68 };
  69
  70 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
  71         { .name = "logic", .rst_shift = 0 },
  72         { .name = "mmu", .rst_shift = 1 },
  73 };
  74
  75 static struct omap_hwmod omap2420_dsp_hwmod = {
  76         .name           = "dsp",
  77         .class          = &dsp_hwmod_class,
  78         .clkdm_name     = "dsp_clkdm",
  79         .rst_lines      = omap2420_dsp_resets,
  80         .rst_lines_cnt  = ARRAY_SIZE(omap2420_dsp_resets),
  81         .main_clk       = "dsp_fck",
  82 };
  83
  84 /* I2C common */
  85 static struct omap_hwmod_class_sysconfig i2c_sysc = {
  86         .rev_offs       = 0x00,
  87         .sysc_offs      = 0x20,
  88         .syss_offs      = 0x10,
  89         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  90         .sysc_fields    = &omap_hwmod_sysc_type1,
  91 };
  92
  93 static struct omap_hwmod_class i2c_class = {
  94         .name           = "i2c",
  95         .sysc           = &i2c_sysc,
  96         .rev            = OMAP_I2C_IP_VERSION_1,
  97         .reset          = &omap_i2c_reset,
  98 };
  99
 100 static struct omap_i2c_dev_attr i2c_dev_attr = {
 101         .flags          = OMAP_I2C_FLAG_NO_FIFO |
 102                           OMAP_I2C_FLAG_SIMPLE_CLOCK |
 103                           OMAP_I2C_FLAG_16BIT_DATA_REG |
 104                           OMAP_I2C_FLAG_BUS_SHIFT_2,
 105 };
 106
 107 /* I2C1 */
 108 static struct omap_hwmod omap2420_i2c1_hwmod = {
 109         .name           = "i2c1",
 110         .mpu_irqs       = omap2_i2c1_mpu_irqs,
 111         .sdma_reqs      = omap2_i2c1_sdma_reqs,
 112         .main_clk       = "i2c1_fck",
 113         .prcm           = {
 114                 .omap2 = {
 115                         .module_offs = CORE_MOD,
 116                         .prcm_reg_id = 1,
 117                         .module_bit = OMAP2420_EN_I2C1_SHIFT,
 118                         .idlest_reg_id = 1,
 119                         .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
 120                 },
 121         },
 122         .class          = &i2c_class,
 123         .dev_attr       = &i2c_dev_attr,
 124         .flags          = HWMOD_16BIT_REG,
 125 };
 126
 127 /* I2C2 */
 128 static struct omap_hwmod omap2420_i2c2_hwmod = {
 129         .name           = "i2c2",
 130         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 131         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 132         .main_clk       = "i2c2_fck",
 133         .prcm           = {
 134                 .omap2 = {
 135                         .module_offs = CORE_MOD,
 136                         .prcm_reg_id = 1,
 137                         .module_bit = OMAP2420_EN_I2C2_SHIFT,
 138                         .idlest_reg_id = 1,
 139                         .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
 140                 },
 141         },
 142         .class          = &i2c_class,
 143         .dev_attr       = &i2c_dev_attr,
 144         .flags          = HWMOD_16BIT_REG,
 145 };
 146
 147 /* dma attributes */
 148 static struct omap_dma_dev_attr dma_dev_attr = {
 149         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 150                                                 IS_CSSA_32 | IS_CDSA_32,
 151         .lch_count = 32,
 152 };
 153
 154 static struct omap_hwmod omap2420_dma_system_hwmod = {
 155         .name           = "dma",
 156         .class          = &omap2xxx_dma_hwmod_class,
 157         .mpu_irqs       = omap2_dma_system_irqs,
 158         .main_clk       = "core_l3_ck",
 159         .dev_attr       = &dma_dev_attr,
 160         .flags          = HWMOD_NO_IDLEST,
 161 };
 162
 163 /* mailbox */
 164 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
 165         { .name = "dsp", .irq = 26 },
 166         { .name = "iva", .irq = 34 },
 167         { .irq = -1 }
 168 };
 169
 170 static struct omap_hwmod omap2420_mailbox_hwmod = {
 171         .name           = "mailbox",
 172         .class          = &omap2xxx_mailbox_hwmod_class,
 173         .mpu_irqs       = omap2420_mailbox_irqs,
 174         .main_clk       = "mailboxes_ick",
 175         .prcm           = {
 176                 .omap2 = {
 177                         .prcm_reg_id = 1,
 178                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
 179                         .module_offs = CORE_MOD,
 180                         .idlest_reg_id = 1,
 181                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
 182                 },
 183         },
 184 };
 185
 186 /*
 187  * 'mcbsp' class
 188  * multi channel buffered serial port controller
 189  */
 190
 191 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
 192         .name = "mcbsp",
 193 };
 194
 195 /* mcbsp1 */
 196 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
 197         { .name = "tx", .irq = 59 },
 198         { .name = "rx", .irq = 60 },
 199         { .irq = -1 }
 200 };
 201
 202 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
 203         .name           = "mcbsp1",
 204         .class          = &omap2420_mcbsp_hwmod_class,
 205         .mpu_irqs       = omap2420_mcbsp1_irqs,
 206         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
 207         .main_clk       = "mcbsp1_fck",
 208         .prcm           = {
 209                 .omap2 = {
 210                         .prcm_reg_id = 1,
 211                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
 212                         .module_offs = CORE_MOD,
 213                         .idlest_reg_id = 1,
 214                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
 215                 },
 216         },
 217 };
 218
 219 /* mcbsp2 */
 220 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
 221         { .name = "tx", .irq = 62 },
 222         { .name = "rx", .irq = 63 },
 223         { .irq = -1 }
 224 };
 225
 226 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
 227         .name           = "mcbsp2",
 228         .class          = &omap2420_mcbsp_hwmod_class,
 229         .mpu_irqs       = omap2420_mcbsp2_irqs,
 230         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
 231         .main_clk       = "mcbsp2_fck",
 232         .prcm           = {
 233                 .omap2 = {
 234                         .prcm_reg_id = 1,
 235                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
 236                         .module_offs = CORE_MOD,
 237                         .idlest_reg_id = 1,
 238                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
 239                 },
 240         },
 241 };
 242
 243 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
 244         .rev_offs       = 0x3c,
 245         .sysc_offs      = 0x64,
 246         .syss_offs      = 0x68,
 247         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 248         .sysc_fields    = &omap_hwmod_sysc_type1,
 249 };
 250
 251 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
 252         .name   = "msdi",
 253         .sysc   = &omap2420_msdi_sysc,
 254         .reset  = &omap_msdi_reset,
 255 };
 256
 257 /* msdi1 */
 258 static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
 259         { .irq = 83 },
 260         { .irq = -1 }
 261 };
 262
 263 static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
 264         { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
 265         { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
 266         { .dma_req = -1 }
 267 };
 268
 269 static struct omap_hwmod omap2420_msdi1_hwmod = {
 270         .name           = "msdi1",
 271         .class          = &omap2420_msdi_hwmod_class,
 272         .mpu_irqs       = omap2420_msdi1_irqs,
 273         .sdma_reqs      = omap2420_msdi1_sdma_reqs,
 274         .main_clk       = "mmc_fck",
 275         .prcm           = {
 276                 .omap2 = {
 277                         .prcm_reg_id = 1,
 278                         .module_bit = OMAP2420_EN_MMC_SHIFT,
 279                         .module_offs = CORE_MOD,
 280                         .idlest_reg_id = 1,
 281                         .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
 282                 },
 283         },
 284         .flags          = HWMOD_16BIT_REG,
 285 };
 286
 287 /* HDQ1W/1-wire */
 288 static struct omap_hwmod omap2420_hdq1w_hwmod = {
 289         .name           = "hdq1w",
 290         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
 291         .main_clk       = "hdq_fck",
 292         .prcm           = {
 293                 .omap2 = {
 294                         .module_offs = CORE_MOD,
 295                         .prcm_reg_id = 1,
 296                         .module_bit = OMAP24XX_EN_HDQ_SHIFT,
 297                         .idlest_reg_id = 1,
 298                         .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
 299                 },
 300         },
 301         .class          = &omap2_hdq1w_class,
 302 };
 303
 304 /*
 305  * interfaces
 306  */
 307
 308 /* L4 CORE -> I2C1 interface */
 309 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
 310         .master         = &omap2xxx_l4_core_hwmod,
 311         .slave          = &omap2420_i2c1_hwmod,
 312         .clk            = "i2c1_ick",
 313         .addr           = omap2_i2c1_addr_space,
 314         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 315 };
 316
 317 /* L4 CORE -> I2C2 interface */
 318 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
 319         .master         = &omap2xxx_l4_core_hwmod,
 320         .slave          = &omap2420_i2c2_hwmod,
 321         .clk            = "i2c2_ick",
 322         .addr           = omap2_i2c2_addr_space,
 323         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 324 };
 325
 326 /* IVA <- L3 interface */
 327 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
 328         .master         = &omap2xxx_l3_main_hwmod,
 329         .slave          = &omap2420_iva_hwmod,
 330         .clk            = "core_l3_ck",
 331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 332 };
 333
 334 /* DSP <- L3 interface */
 335 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
 336         .master         = &omap2xxx_l3_main_hwmod,
 337         .slave          = &omap2420_dsp_hwmod,
 338         .clk            = "dsp_ick",
 339         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 340 };
 341
 342 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
 343         {
 344                 .pa_start       = 0x48028000,
 345                 .pa_end         = 0x48028000 + SZ_1K - 1,
 346                 .flags          = ADDR_TYPE_RT
 347         },
 348         { }
 349 };
 350
 351 /* l4_wkup -> timer1 */
 352 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
 353         .master         = &omap2xxx_l4_wkup_hwmod,
 354         .slave          = &omap2xxx_timer1_hwmod,
 355         .clk            = "gpt1_ick",
 356         .addr           = omap2420_timer1_addrs,
 357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 358 };
 359
 360 /* l4_wkup -> wd_timer2 */
 361 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 362         {
 363                 .pa_start       = 0x48022000,
 364                 .pa_end         = 0x4802207f,
 365                 .flags          = ADDR_TYPE_RT
 366         },
 367         { }
 368 };
 369
 370 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 371         .master         = &omap2xxx_l4_wkup_hwmod,
 372         .slave          = &omap2xxx_wd_timer2_hwmod,
 373         .clk            = "mpu_wdt_ick",
 374         .addr           = omap2420_wd_timer2_addrs,
 375         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 376 };
 377
 378 /* l4_wkup -> gpio1 */
 379 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
 380         {
 381                 .pa_start       = 0x48018000,
 382                 .pa_end         = 0x480181ff,
 383                 .flags          = ADDR_TYPE_RT
 384         },
 385         { }
 386 };
 387
 388 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
 389         .master         = &omap2xxx_l4_wkup_hwmod,
 390         .slave          = &omap2xxx_gpio1_hwmod,
 391         .clk            = "gpios_ick",
 392         .addr           = omap2420_gpio1_addr_space,
 393         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 394 };
 395
 396 /* l4_wkup -> gpio2 */
 397 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
 398         {
 399                 .pa_start       = 0x4801a000,
 400                 .pa_end         = 0x4801a1ff,
 401                 .flags          = ADDR_TYPE_RT
 402         },
 403         { }
 404 };
 405
 406 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
 407         .master         = &omap2xxx_l4_wkup_hwmod,
 408         .slave          = &omap2xxx_gpio2_hwmod,
 409         .clk            = "gpios_ick",
 410         .addr           = omap2420_gpio2_addr_space,
 411         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 412 };
 413
 414 /* l4_wkup -> gpio3 */
 415 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
 416         {
 417                 .pa_start       = 0x4801c000,
 418                 .pa_end         = 0x4801c1ff,
 419                 .flags          = ADDR_TYPE_RT
 420         },
 421         { }
 422 };
 423
 424 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
 425         .master         = &omap2xxx_l4_wkup_hwmod,
 426         .slave          = &omap2xxx_gpio3_hwmod,
 427         .clk            = "gpios_ick",
 428         .addr           = omap2420_gpio3_addr_space,
 429         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 430 };
 431
 432 /* l4_wkup -> gpio4 */
 433 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
 434         {
 435                 .pa_start       = 0x4801e000,
 436                 .pa_end         = 0x4801e1ff,
 437                 .flags          = ADDR_TYPE_RT
 438         },
 439         { }
 440 };
 441
 442 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
 443         .master         = &omap2xxx_l4_wkup_hwmod,
 444         .slave          = &omap2xxx_gpio4_hwmod,
 445         .clk            = "gpios_ick",
 446         .addr           = omap2420_gpio4_addr_space,
 447         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 448 };
 449
 450 /* dma_system -> L3 */
 451 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
 452         .master         = &omap2420_dma_system_hwmod,
 453         .slave          = &omap2xxx_l3_main_hwmod,
 454         .clk            = "core_l3_ck",
 455         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 456 };
 457
 458 /* l4_core -> dma_system */
 459 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
 460         .master         = &omap2xxx_l4_core_hwmod,
 461         .slave          = &omap2420_dma_system_hwmod,
 462         .clk            = "sdma_ick",
 463         .addr           = omap2_dma_system_addrs,
 464         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 465 };
 466
 467 /* l4_core -> mailbox */
 468 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
 469         .master         = &omap2xxx_l4_core_hwmod,
 470         .slave          = &omap2420_mailbox_hwmod,
 471         .addr           = omap2_mailbox_addrs,
 472         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 473 };
 474
 475 /* l4_core -> mcbsp1 */
 476 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
 477         .master         = &omap2xxx_l4_core_hwmod,
 478         .slave          = &omap2420_mcbsp1_hwmod,
 479         .clk            = "mcbsp1_ick",
 480         .addr           = omap2_mcbsp1_addrs,
 481         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 482 };
 483
 484 /* l4_core -> mcbsp2 */
 485 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
 486         .master         = &omap2xxx_l4_core_hwmod,
 487         .slave          = &omap2420_mcbsp2_hwmod,
 488         .clk            = "mcbsp2_ick",
 489         .addr           = omap2xxx_mcbsp2_addrs,
 490         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 491 };
 492
 493 static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
 494         {
 495                 .pa_start       = 0x4809c000,
 496                 .pa_end         = 0x4809c000 + SZ_128 - 1,
 497                 .flags          = ADDR_TYPE_RT,
 498         },
 499         { }
 500 };
 501
 502 /* l4_core -> msdi1 */
 503 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
 504         .master         = &omap2xxx_l4_core_hwmod,
 505         .slave          = &omap2420_msdi1_hwmod,
 506         .clk            = "mmc_ick",
 507         .addr           = omap2420_msdi1_addrs,
 508         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 509 };
 510
 511 /* l4_core -> hdq1w interface */
 512 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
 513         .master         = &omap2xxx_l4_core_hwmod,
 514         .slave          = &omap2420_hdq1w_hwmod,
 515         .clk            = "hdq_ick",
 516         .addr           = omap2_hdq1w_addr_space,
 517         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 518         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
 519 };
 520
 521
 522 /* l4_wkup -> 32ksync_counter */
 523 static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
 524         {
 525                 .pa_start       = 0x48004000,
 526                 .pa_end         = 0x4800401f,
 527                 .flags          = ADDR_TYPE_RT
 528         },
 529         { }
 530 };
 531
 532 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
 533         .master         = &omap2xxx_l4_wkup_hwmod,
 534         .slave          = &omap2xxx_counter_32k_hwmod,
 535         .clk            = "sync_32k_ick",
 536         .addr           = omap2420_counter_32k_addrs,
 537         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 538 };
 539
 540 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
 541         &omap2xxx_l3_main__l4_core,
 542         &omap2xxx_mpu__l3_main,
 543         &omap2xxx_dss__l3,
 544         &omap2xxx_l4_core__mcspi1,
 545         &omap2xxx_l4_core__mcspi2,
 546         &omap2xxx_l4_core__l4_wkup,
 547         &omap2_l4_core__uart1,
 548         &omap2_l4_core__uart2,
 549         &omap2_l4_core__uart3,
 550         &omap2420_l4_core__i2c1,
 551         &omap2420_l4_core__i2c2,
 552         &omap2420_l3__iva,
 553         &omap2420_l3__dsp,
 554         &omap2420_l4_wkup__timer1,
 555         &omap2xxx_l4_core__timer2,
 556         &omap2xxx_l4_core__timer3,
 557         &omap2xxx_l4_core__timer4,
 558         &omap2xxx_l4_core__timer5,
 559         &omap2xxx_l4_core__timer6,
 560         &omap2xxx_l4_core__timer7,
 561         &omap2xxx_l4_core__timer8,
 562         &omap2xxx_l4_core__timer9,
 563         &omap2xxx_l4_core__timer10,
 564         &omap2xxx_l4_core__timer11,
 565         &omap2xxx_l4_core__timer12,
 566         &omap2420_l4_wkup__wd_timer2,
 567         &omap2xxx_l4_core__dss,
 568         &omap2xxx_l4_core__dss_dispc,
 569         &omap2xxx_l4_core__dss_rfbi,
 570         &omap2xxx_l4_core__dss_venc,
 571         &omap2420_l4_wkup__gpio1,
 572         &omap2420_l4_wkup__gpio2,
 573         &omap2420_l4_wkup__gpio3,
 574         &omap2420_l4_wkup__gpio4,
 575         &omap2420_dma_system__l3,
 576         &omap2420_l4_core__dma_system,
 577         &omap2420_l4_core__mailbox,
 578         &omap2420_l4_core__mcbsp1,
 579         &omap2420_l4_core__mcbsp2,
 580         &omap2420_l4_core__msdi1,
 581         &omap2420_l4_core__hdq1w,
 582         &omap2420_l4_wkup__counter_32k,
 583         NULL,
 584 };
 585
 586 int __init omap2420_hwmod_init(void)
 587 {
 588         return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
 589 }