arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c

   1 /*
   2  *
   3  * Copyright (C) 2013 Texas Instruments Incorporated
   4  *
   5  * Interconnects common for AM335x and AM43x
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/sizes.h>
  18 #include "omap_hwmod.h"
  19 #include "omap_hwmod_33xx_43xx_common_data.h"
  20
  21 /* mpu -> l3 main */
  22 struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
  23         .master         = &am33xx_mpu_hwmod,
  24         .slave          = &am33xx_l3_main_hwmod,
  25         .clk            = "dpll_mpu_m2_ck",
  26         .user           = OCP_USER_MPU,
  27 };
  28
  29 /* l3 main -> l3 s */
  30 struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
  31         .master         = &am33xx_l3_main_hwmod,
  32         .slave          = &am33xx_l3_s_hwmod,
  33         .clk            = "l3s_gclk",
  34         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  35 };
  36
  37 /* l3 s -> l4 per/ls */
  38 struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
  39         .master         = &am33xx_l3_s_hwmod,
  40         .slave          = &am33xx_l4_ls_hwmod,
  41         .clk            = "l3s_gclk",
  42         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  43 };
  44
  45 /* l3 s -> l4 wkup */
  46 struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
  47         .master         = &am33xx_l3_s_hwmod,
  48         .slave          = &am33xx_l4_wkup_hwmod,
  49         .clk            = "l3s_gclk",
  50         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  51 };
  52
  53 /* l3 main -> l3 instr */
  54 struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
  55         .master         = &am33xx_l3_main_hwmod,
  56         .slave          = &am33xx_l3_instr_hwmod,
  57         .clk            = "l3s_gclk",
  58         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  59 };
  60
  61 /* mpu -> prcm */
  62 struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
  63         .master         = &am33xx_mpu_hwmod,
  64         .slave          = &am33xx_prcm_hwmod,
  65         .clk            = "dpll_mpu_m2_ck",
  66         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  67 };
  68
  69 /* l3 s -> l3 main*/
  70 struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
  71         .master         = &am33xx_l3_s_hwmod,
  72         .slave          = &am33xx_l3_main_hwmod,
  73         .clk            = "l3s_gclk",
  74         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  75 };
  76
  77 /* pru-icss -> l3 main */
  78 struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
  79         .master         = &am33xx_pruss_hwmod,
  80         .slave          = &am33xx_l3_main_hwmod,
  81         .clk            = "l3_gclk",
  82         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  83 };
  84
  85 /* gfx -> l3 main */
  86 struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
  87         .master         = &am33xx_gfx_hwmod,
  88         .slave          = &am33xx_l3_main_hwmod,
  89         .clk            = "dpll_core_m4_ck",
  90         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  91 };
  92
  93 /* l3 main -> gfx */
  94 struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
  95         .master         = &am33xx_l3_main_hwmod,
  96         .slave          = &am33xx_gfx_hwmod,
  97         .clk            = "dpll_core_m4_ck",
  98         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  99 };
 100
 101 /* l4 wkup -> rtc */
 102 struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
 103         .master         = &am33xx_l4_wkup_hwmod,
 104         .slave          = &am33xx_rtc_hwmod,
 105         .clk            = "clkdiv32k_ick",
 106         .user           = OCP_USER_MPU,
 107 };
 108
 109 /* l4 per/ls -> DCAN0 */
 110 struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
 111         .master         = &am33xx_l4_ls_hwmod,
 112         .slave          = &am33xx_dcan0_hwmod,
 113         .clk            = "l4ls_gclk",
 114         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 115 };
 116
 117 /* l4 per/ls -> DCAN1 */
 118 struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
 119         .master         = &am33xx_l4_ls_hwmod,
 120         .slave          = &am33xx_dcan1_hwmod,
 121         .clk            = "l4ls_gclk",
 122         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 123 };
 124
 125 /* l4 per/ls -> GPIO2 */
 126 struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
 127         .master         = &am33xx_l4_ls_hwmod,
 128         .slave          = &am33xx_gpio1_hwmod,
 129         .clk            = "l4ls_gclk",
 130         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 131 };
 132
 133 /* l4 per/ls -> gpio3 */
 134 struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
 135         .master         = &am33xx_l4_ls_hwmod,
 136         .slave          = &am33xx_gpio2_hwmod,
 137         .clk            = "l4ls_gclk",
 138         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 139 };
 140
 141 /* l4 per/ls -> gpio4 */
 142 struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
 143         .master         = &am33xx_l4_ls_hwmod,
 144         .slave          = &am33xx_gpio3_hwmod,
 145         .clk            = "l4ls_gclk",
 146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 147 };
 148
 149 struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
 150         .master         = &am33xx_cpgmac0_hwmod,
 151         .slave          = &am33xx_mdio_hwmod,
 152         .user           = OCP_USER_MPU,
 153 };
 154
 155 struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
 156         .master         = &am33xx_l4_ls_hwmod,
 157         .slave          = &am33xx_elm_hwmod,
 158         .clk            = "l4ls_gclk",
 159         .user           = OCP_USER_MPU,
 160 };
 161
 162 static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
 163         {
 164                 .pa_start       = 0x48300000,
 165                 .pa_end         = 0x48300000 + SZ_16 - 1,
 166                 .flags          = ADDR_TYPE_RT
 167         },
 168         { }
 169 };
 170
 171 struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
 172         .master         = &am33xx_l4_ls_hwmod,
 173         .slave          = &am33xx_epwmss0_hwmod,
 174         .clk            = "l4ls_gclk",
 175         .addr           = am33xx_epwmss0_addr_space,
 176         .user           = OCP_USER_MPU,
 177 };
 178
 179 static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
 180         {
 181                 .pa_start       = 0x48302000,
 182                 .pa_end         = 0x48302000 + SZ_16 - 1,
 183                 .flags          = ADDR_TYPE_RT
 184         },
 185         { }
 186 };
 187
 188 struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
 189         .master         = &am33xx_l4_ls_hwmod,
 190         .slave          = &am33xx_epwmss1_hwmod,
 191         .clk            = "l4ls_gclk",
 192         .addr           = am33xx_epwmss1_addr_space,
 193         .user           = OCP_USER_MPU,
 194 };
 195
 196 static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
 197         {
 198                 .pa_start       = 0x48304000,
 199                 .pa_end         = 0x48304000 + SZ_16 - 1,
 200                 .flags          = ADDR_TYPE_RT
 201         },
 202         { }
 203 };
 204
 205 struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
 206         .master         = &am33xx_l4_ls_hwmod,
 207         .slave          = &am33xx_epwmss2_hwmod,
 208         .clk            = "l4ls_gclk",
 209         .addr           = am33xx_epwmss2_addr_space,
 210         .user           = OCP_USER_MPU,
 211 };
 212
 213 /* l3s cfg -> gpmc */
 214 struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
 215         .master         = &am33xx_l3_s_hwmod,
 216         .slave          = &am33xx_gpmc_hwmod,
 217         .clk            = "l3s_gclk",
 218         .user           = OCP_USER_MPU,
 219 };
 220
 221 /* i2c2 */
 222 struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
 223         .master         = &am33xx_l4_ls_hwmod,
 224         .slave          = &am33xx_i2c2_hwmod,
 225         .clk            = "l4ls_gclk",
 226         .user           = OCP_USER_MPU,
 227 };
 228
 229 struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
 230         .master         = &am33xx_l4_ls_hwmod,
 231         .slave          = &am33xx_i2c3_hwmod,
 232         .clk            = "l4ls_gclk",
 233         .user           = OCP_USER_MPU,
 234 };
 235
 236 /* l4 ls -> mailbox */
 237 struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
 238         .master         = &am33xx_l4_ls_hwmod,
 239         .slave          = &am33xx_mailbox_hwmod,
 240         .clk            = "l4ls_gclk",
 241         .user           = OCP_USER_MPU,
 242 };
 243
 244 /* l4 ls -> spinlock */
 245 struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
 246         .master         = &am33xx_l4_ls_hwmod,
 247         .slave          = &am33xx_spinlock_hwmod,
 248         .clk            = "l4ls_gclk",
 249         .user           = OCP_USER_MPU,
 250 };
 251
 252 /* l4 ls -> mcasp0 */
 253 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
 254         {
 255                 .pa_start       = 0x48038000,
 256                 .pa_end         = 0x48038000 + SZ_8K - 1,
 257                 .flags          = ADDR_TYPE_RT
 258         },
 259         { }
 260 };
 261
 262 struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
 263         .master         = &am33xx_l4_ls_hwmod,
 264         .slave          = &am33xx_mcasp0_hwmod,
 265         .clk            = "l4ls_gclk",
 266         .addr           = am33xx_mcasp0_addr_space,
 267         .user           = OCP_USER_MPU,
 268 };
 269
 270 /* l4 ls -> mcasp1 */
 271 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
 272         {
 273                 .pa_start       = 0x4803C000,
 274                 .pa_end         = 0x4803C000 + SZ_8K - 1,
 275                 .flags          = ADDR_TYPE_RT
 276         },
 277         { }
 278 };
 279
 280 struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
 281         .master         = &am33xx_l4_ls_hwmod,
 282         .slave          = &am33xx_mcasp1_hwmod,
 283         .clk            = "l4ls_gclk",
 284         .addr           = am33xx_mcasp1_addr_space,
 285         .user           = OCP_USER_MPU,
 286 };
 287
 288 /* l4 ls -> mmc0 */
 289 struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
 290         .master         = &am33xx_l4_ls_hwmod,
 291         .slave          = &am33xx_mmc0_hwmod,
 292         .clk            = "l4ls_gclk",
 293         .user           = OCP_USER_MPU,
 294 };
 295
 296 /* l4 ls -> mmc1 */
 297 struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
 298         .master         = &am33xx_l4_ls_hwmod,
 299         .slave          = &am33xx_mmc1_hwmod,
 300         .clk            = "l4ls_gclk",
 301         .user           = OCP_USER_MPU,
 302 };
 303
 304 /* l3 s -> mmc2 */
 305 struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
 306         .master         = &am33xx_l3_s_hwmod,
 307         .slave          = &am33xx_mmc2_hwmod,
 308         .clk            = "l3s_gclk",
 309         .user           = OCP_USER_MPU,
 310 };
 311
 312 /* l4 ls -> mcspi0 */
 313 struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
 314         .master         = &am33xx_l4_ls_hwmod,
 315         .slave          = &am33xx_spi0_hwmod,
 316         .clk            = "l4ls_gclk",
 317         .user           = OCP_USER_MPU,
 318 };
 319
 320 /* l4 ls -> mcspi1 */
 321 struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
 322         .master         = &am33xx_l4_ls_hwmod,
 323         .slave          = &am33xx_spi1_hwmod,
 324         .clk            = "l4ls_gclk",
 325         .user           = OCP_USER_MPU,
 326 };
 327
 328 /* l4 per -> timer2 */
 329 struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
 330         .master         = &am33xx_l4_ls_hwmod,
 331         .slave          = &am33xx_timer2_hwmod,
 332         .clk            = "l4ls_gclk",
 333         .user           = OCP_USER_MPU,
 334 };
 335
 336 /* l4 per -> timer3 */
 337 struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
 338         .master         = &am33xx_l4_ls_hwmod,
 339         .slave          = &am33xx_timer3_hwmod,
 340         .clk            = "l4ls_gclk",
 341         .user           = OCP_USER_MPU,
 342 };
 343
 344 /* l4 per -> timer4 */
 345 struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
 346         .master         = &am33xx_l4_ls_hwmod,
 347         .slave          = &am33xx_timer4_hwmod,
 348         .clk            = "l4ls_gclk",
 349         .user           = OCP_USER_MPU,
 350 };
 351
 352 /* l4 per -> timer5 */
 353 struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
 354         .master         = &am33xx_l4_ls_hwmod,
 355         .slave          = &am33xx_timer5_hwmod,
 356         .clk            = "l4ls_gclk",
 357         .user           = OCP_USER_MPU,
 358 };
 359
 360 /* l4 per -> timer6 */
 361 struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
 362         .master         = &am33xx_l4_ls_hwmod,
 363         .slave          = &am33xx_timer6_hwmod,
 364         .clk            = "l4ls_gclk",
 365         .user           = OCP_USER_MPU,
 366 };
 367
 368 /* l4 per -> timer7 */
 369 struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
 370         .master         = &am33xx_l4_ls_hwmod,
 371         .slave          = &am33xx_timer7_hwmod,
 372         .clk            = "l4ls_gclk",
 373         .user           = OCP_USER_MPU,
 374 };
 375
 376 /* l3 main -> tpcc */
 377 struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
 378         .master         = &am33xx_l3_main_hwmod,
 379         .slave          = &am33xx_tpcc_hwmod,
 380         .clk            = "l3_gclk",
 381         .user           = OCP_USER_MPU,
 382 };
 383
 384 /* l3 main -> tpcc0 */
 385 static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
 386         {
 387                 .pa_start       = 0x49800000,
 388                 .pa_end         = 0x49800000 + SZ_8K - 1,
 389                 .flags          = ADDR_TYPE_RT,
 390         },
 391         { }
 392 };
 393
 394 struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
 395         .master         = &am33xx_l3_main_hwmod,
 396         .slave          = &am33xx_tptc0_hwmod,
 397         .clk            = "l3_gclk",
 398         .addr           = am33xx_tptc0_addr_space,
 399         .user           = OCP_USER_MPU,
 400 };
 401
 402 /* l3 main -> tpcc1 */
 403 static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
 404         {
 405                 .pa_start       = 0x49900000,
 406                 .pa_end         = 0x49900000 + SZ_8K - 1,
 407                 .flags          = ADDR_TYPE_RT,
 408         },
 409         { }
 410 };
 411
 412 struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
 413         .master         = &am33xx_l3_main_hwmod,
 414         .slave          = &am33xx_tptc1_hwmod,
 415         .clk            = "l3_gclk",
 416         .addr           = am33xx_tptc1_addr_space,
 417         .user           = OCP_USER_MPU,
 418 };
 419
 420 /* l3 main -> tpcc2 */
 421 static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
 422         {
 423                 .pa_start       = 0x49a00000,
 424                 .pa_end         = 0x49a00000 + SZ_8K - 1,
 425                 .flags          = ADDR_TYPE_RT,
 426         },
 427         { }
 428 };
 429
 430 struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
 431         .master         = &am33xx_l3_main_hwmod,
 432         .slave          = &am33xx_tptc2_hwmod,
 433         .clk            = "l3_gclk",
 434         .addr           = am33xx_tptc2_addr_space,
 435         .user           = OCP_USER_MPU,
 436 };
 437
 438 /* l4 ls -> uart2 */
 439 struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
 440         .master         = &am33xx_l4_ls_hwmod,
 441         .slave          = &am33xx_uart2_hwmod,
 442         .clk            = "l4ls_gclk",
 443         .user           = OCP_USER_MPU,
 444 };
 445
 446 /* l4 ls -> uart3 */
 447 struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
 448         .master         = &am33xx_l4_ls_hwmod,
 449         .slave          = &am33xx_uart3_hwmod,
 450         .clk            = "l4ls_gclk",
 451         .user           = OCP_USER_MPU,
 452 };
 453
 454 /* l4 ls -> uart4 */
 455 struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
 456         .master         = &am33xx_l4_ls_hwmod,
 457         .slave          = &am33xx_uart4_hwmod,
 458         .clk            = "l4ls_gclk",
 459         .user           = OCP_USER_MPU,
 460 };
 461
 462 /* l4 ls -> uart5 */
 463 struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
 464         .master         = &am33xx_l4_ls_hwmod,
 465         .slave          = &am33xx_uart5_hwmod,
 466         .clk            = "l4ls_gclk",
 467         .user           = OCP_USER_MPU,
 468 };
 469
 470 /* l4 ls -> uart6 */
 471 struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
 472         .master         = &am33xx_l4_ls_hwmod,
 473         .slave          = &am33xx_uart6_hwmod,
 474         .clk            = "l4ls_gclk",
 475         .user           = OCP_USER_MPU,
 476 };
 477
 478 /* l3 main -> ocmc */
 479 struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
 480         .master         = &am33xx_l3_main_hwmod,
 481         .slave          = &am33xx_ocmcram_hwmod,
 482         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 483 };
 484
 485 /* l3 main -> sha0 HIB2 */
 486 static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
 487         {
 488                 .pa_start       = 0x53100000,
 489                 .pa_end         = 0x53100000 + SZ_512 - 1,
 490                 .flags          = ADDR_TYPE_RT
 491         },
 492         { }
 493 };
 494
 495 struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
 496         .master         = &am33xx_l3_main_hwmod,
 497         .slave          = &am33xx_sha0_hwmod,
 498         .clk            = "sha0_fck",
 499         .addr           = am33xx_sha0_addrs,
 500         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 501 };
 502
 503 /* l3 main -> AES0 HIB2 */
 504 static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
 505         {
 506                 .pa_start       = 0x53500000,
 507                 .pa_end         = 0x53500000 + SZ_1M - 1,
 508                 .flags          = ADDR_TYPE_RT
 509         },
 510         { }
 511 };
 512
 513 struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
 514         .master         = &am33xx_l3_main_hwmod,
 515         .slave          = &am33xx_aes0_hwmod,
 516         .clk            = "aes0_fck",
 517         .addr           = am33xx_aes0_addrs,
 518         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 519 };
 520
 521 /* l4 per -> rng */
 522 struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
 523         .master         = &am33xx_l4_ls_hwmod,
 524         .slave          = &am33xx_rng_hwmod,
 525         .clk            = "rng_fck",
 526         .user           = OCP_USER_MPU,
 527 };