arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

   1 /*
   2  *
   3  * Copyright (C) 2013 Texas Instruments Incorporated
   4  *
   5  * Hwmod common for AM335x and AM43x
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/platform_data/gpio-omap.h>
  18 #include <linux/platform_data/hsmmc-omap.h>
  19 #include <linux/platform_data/spi-omap2-mcspi.h>
  20 #include "omap_hwmod.h"
  21 #include "i2c.h"
  22 #include "wd_timer.h"
  23 #include "cm33xx.h"
  24 #include "prm33xx.h"
  25 #include "omap_hwmod_33xx_43xx_common_data.h"
  26 #include "prcm43xx.h"
  27 #include "common.h"
  28
  29 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
  30 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
  31 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
  32
  33 /*
  34  * 'l3' class
  35  * instance(s): l3_main, l3_s, l3_instr
  36  */
  37 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  38         .name           = "l3",
  39 };
  40
  41 struct omap_hwmod am33xx_l3_main_hwmod = {
  42         .name           = "l3_main",
  43         .class          = &am33xx_l3_hwmod_class,
  44         .clkdm_name     = "l3_clkdm",
  45         .flags          = HWMOD_INIT_NO_IDLE,
  46         .main_clk       = "l3_gclk",
  47         .prcm           = {
  48                 .omap4  = {
  49                         .modulemode     = MODULEMODE_SWCTRL,
  50                 },
  51         },
  52 };
  53
  54 /* l3_s */
  55 struct omap_hwmod am33xx_l3_s_hwmod = {
  56         .name           = "l3_s",
  57         .class          = &am33xx_l3_hwmod_class,
  58         .clkdm_name     = "l3s_clkdm",
  59 };
  60
  61 /* l3_instr */
  62 struct omap_hwmod am33xx_l3_instr_hwmod = {
  63         .name           = "l3_instr",
  64         .class          = &am33xx_l3_hwmod_class,
  65         .clkdm_name     = "l3_clkdm",
  66         .flags          = HWMOD_INIT_NO_IDLE,
  67         .main_clk       = "l3_gclk",
  68         .prcm           = {
  69                 .omap4  = {
  70                         .modulemode     = MODULEMODE_SWCTRL,
  71                 },
  72         },
  73 };
  74
  75 /*
  76  * 'l4' class
  77  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
  78  */
  79 struct omap_hwmod_class am33xx_l4_hwmod_class = {
  80         .name           = "l4",
  81 };
  82
  83 /* l4_ls */
  84 struct omap_hwmod am33xx_l4_ls_hwmod = {
  85         .name           = "l4_ls",
  86         .class          = &am33xx_l4_hwmod_class,
  87         .clkdm_name     = "l4ls_clkdm",
  88         .flags          = HWMOD_INIT_NO_IDLE,
  89         .main_clk       = "l4ls_gclk",
  90         .prcm           = {
  91                 .omap4  = {
  92                         .modulemode     = MODULEMODE_SWCTRL,
  93                 },
  94         },
  95 };
  96
  97 /* l4_wkup */
  98 struct omap_hwmod am33xx_l4_wkup_hwmod = {
  99         .name           = "l4_wkup",
 100         .class          = &am33xx_l4_hwmod_class,
 101         .clkdm_name     = "l4_wkup_clkdm",
 102         .flags          = HWMOD_INIT_NO_IDLE,
 103         .prcm           = {
 104                 .omap4  = {
 105                         .modulemode     = MODULEMODE_SWCTRL,
 106                 },
 107         },
 108 };
 109
 110 /*
 111  * 'mpu' class
 112  */
 113 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 114         .name   = "mpu",
 115 };
 116
 117 struct omap_hwmod am33xx_mpu_hwmod = {
 118         .name           = "mpu",
 119         .class          = &am33xx_mpu_hwmod_class,
 120         .clkdm_name     = "mpu_clkdm",
 121         .flags          = HWMOD_INIT_NO_IDLE,
 122         .main_clk       = "dpll_mpu_m2_ck",
 123         .prcm           = {
 124                 .omap4  = {
 125                         .modulemode     = MODULEMODE_SWCTRL,
 126                 },
 127         },
 128 };
 129
 130 /*
 131  * 'wakeup m3' class
 132  * Wakeup controller sub-system under wakeup domain
 133  */
 134 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 135         .name           = "wkup_m3",
 136 };
 137
 138 /*
 139  * 'pru-icss' class
 140  * Programmable Real-Time Unit and Industrial Communication Subsystem
 141  */
 142 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 143         .name   = "pruss",
 144 };
 145
 146 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 147         { .name = "pruss", .rst_shift = 1 },
 148 };
 149
 150 /* pru-icss */
 151 /* Pseudo hwmod for reset control purpose only */
 152 struct omap_hwmod am33xx_pruss_hwmod = {
 153         .name           = "pruss",
 154         .class          = &am33xx_pruss_hwmod_class,
 155         .clkdm_name     = "pruss_ocp_clkdm",
 156         .main_clk       = "pruss_ocp_gclk",
 157         .prcm           = {
 158                 .omap4  = {
 159                         .modulemode     = MODULEMODE_SWCTRL,
 160                 },
 161         },
 162         .rst_lines      = am33xx_pruss_resets,
 163         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 164 };
 165
 166 /* gfx */
 167 /* Pseudo hwmod for reset control purpose only */
 168 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 169         .name   = "gfx",
 170 };
 171
 172 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 173         { .name = "gfx", .rst_shift = 0, .st_shift = 0},
 174 };
 175
 176 struct omap_hwmod am33xx_gfx_hwmod = {
 177         .name           = "gfx",
 178         .class          = &am33xx_gfx_hwmod_class,
 179         .clkdm_name     = "gfx_l3_clkdm",
 180         .main_clk       = "gfx_fck_div_ck",
 181         .prcm           = {
 182                 .omap4  = {
 183                         .modulemode     = MODULEMODE_SWCTRL,
 184                 },
 185         },
 186         .rst_lines      = am33xx_gfx_resets,
 187         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 188 };
 189
 190 /*
 191  * 'prcm' class
 192  * power and reset manager (whole prcm infrastructure)
 193  */
 194 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 195         .name   = "prcm",
 196 };
 197
 198 /* prcm */
 199 struct omap_hwmod am33xx_prcm_hwmod = {
 200         .name           = "prcm",
 201         .class          = &am33xx_prcm_hwmod_class,
 202         .clkdm_name     = "l4_wkup_clkdm",
 203 };
 204
 205 /*
 206  * 'emif' class
 207  * instance(s): emif
 208  */
 209 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
 210         .rev_offs       = 0x0000,
 211 };
 212
 213 struct omap_hwmod_class am33xx_emif_hwmod_class = {
 214         .name           = "emif",
 215         .sysc           = &am33xx_emif_sysc,
 216 };
 217
 218 /*
 219  * 'aes0' class
 220  */
 221 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
 222         .rev_offs       = 0x80,
 223         .sysc_offs      = 0x84,
 224         .syss_offs      = 0x88,
 225         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 226 };
 227
 228 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
 229         .name           = "aes0",
 230         .sysc           = &am33xx_aes0_sysc,
 231 };
 232
 233 struct omap_hwmod am33xx_aes0_hwmod = {
 234         .name           = "aes",
 235         .class          = &am33xx_aes0_hwmod_class,
 236         .clkdm_name     = "l3_clkdm",
 237         .main_clk       = "aes0_fck",
 238         .prcm           = {
 239                 .omap4  = {
 240                         .modulemode     = MODULEMODE_SWCTRL,
 241                 },
 242         },
 243 };
 244
 245 /* sha0 HIB2 (the 'P' (public) device) */
 246 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
 247         .rev_offs       = 0x100,
 248         .sysc_offs      = 0x110,
 249         .syss_offs      = 0x114,
 250         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 251 };
 252
 253 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 254         .name           = "sha0",
 255         .sysc           = &am33xx_sha0_sysc,
 256 };
 257
 258 struct omap_hwmod am33xx_sha0_hwmod = {
 259         .name           = "sham",
 260         .class          = &am33xx_sha0_hwmod_class,
 261         .clkdm_name     = "l3_clkdm",
 262         .main_clk       = "l3_gclk",
 263         .prcm           = {
 264                 .omap4  = {
 265                         .modulemode     = MODULEMODE_SWCTRL,
 266                 },
 267         },
 268 };
 269
 270 /* ocmcram */
 271 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 272         .name = "ocmcram",
 273 };
 274
 275 struct omap_hwmod am33xx_ocmcram_hwmod = {
 276         .name           = "ocmcram",
 277         .class          = &am33xx_ocmcram_hwmod_class,
 278         .clkdm_name     = "l3_clkdm",
 279         .flags          = HWMOD_INIT_NO_IDLE,
 280         .main_clk       = "l3_gclk",
 281         .prcm           = {
 282                 .omap4  = {
 283                         .modulemode     = MODULEMODE_SWCTRL,
 284                 },
 285         },
 286 };
 287
 288 /* 'smartreflex' class */
 289 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 290         .name           = "smartreflex",
 291 };
 292
 293 /* smartreflex0 */
 294 struct omap_hwmod am33xx_smartreflex0_hwmod = {
 295         .name           = "smartreflex0",
 296         .class          = &am33xx_smartreflex_hwmod_class,
 297         .clkdm_name     = "l4_wkup_clkdm",
 298         .main_clk       = "smartreflex0_fck",
 299         .prcm           = {
 300                 .omap4  = {
 301                         .modulemode     = MODULEMODE_SWCTRL,
 302                 },
 303         },
 304 };
 305
 306 /* smartreflex1 */
 307 struct omap_hwmod am33xx_smartreflex1_hwmod = {
 308         .name           = "smartreflex1",
 309         .class          = &am33xx_smartreflex_hwmod_class,
 310         .clkdm_name     = "l4_wkup_clkdm",
 311         .main_clk       = "smartreflex1_fck",
 312         .prcm           = {
 313                 .omap4  = {
 314                         .modulemode     = MODULEMODE_SWCTRL,
 315                 },
 316         },
 317 };
 318
 319 /*
 320  * 'control' module class
 321  */
 322 struct omap_hwmod_class am33xx_control_hwmod_class = {
 323         .name           = "control",
 324 };
 325
 326 /*
 327  * 'cpgmac' class
 328  * cpsw/cpgmac sub system
 329  */
 330 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
 331         .rev_offs       = 0x0,
 332         .sysc_offs      = 0x8,
 333         .syss_offs      = 0x4,
 334         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 335                            SYSS_HAS_RESET_STATUS),
 336         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 337                            MSTANDBY_NO),
 338         .sysc_fields    = &omap_hwmod_sysc_type3,
 339 };
 340
 341 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
 342         .name           = "cpgmac0",
 343         .sysc           = &am33xx_cpgmac_sysc,
 344 };
 345
 346 struct omap_hwmod am33xx_cpgmac0_hwmod = {
 347         .name           = "cpgmac0",
 348         .class          = &am33xx_cpgmac0_hwmod_class,
 349         .clkdm_name     = "cpsw_125mhz_clkdm",
 350         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 351         .main_clk       = "cpsw_125mhz_gclk",
 352         .mpu_rt_idx     = 1,
 353         .prcm           = {
 354                 .omap4  = {
 355                         .modulemode     = MODULEMODE_SWCTRL,
 356                 },
 357         },
 358 };
 359
 360 /*
 361  * mdio class
 362  */
 363 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
 364         .name           = "davinci_mdio",
 365 };
 366
 367 struct omap_hwmod am33xx_mdio_hwmod = {
 368         .name           = "davinci_mdio",
 369         .class          = &am33xx_mdio_hwmod_class,
 370         .clkdm_name     = "cpsw_125mhz_clkdm",
 371         .main_clk       = "cpsw_125mhz_gclk",
 372 };
 373
 374 /*
 375  * dcan class
 376  */
 377 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 378         .name = "d_can",
 379 };
 380
 381 /* dcan0 */
 382 struct omap_hwmod am33xx_dcan0_hwmod = {
 383         .name           = "d_can0",
 384         .class          = &am33xx_dcan_hwmod_class,
 385         .clkdm_name     = "l4ls_clkdm",
 386         .main_clk       = "dcan0_fck",
 387         .prcm           = {
 388                 .omap4  = {
 389                         .modulemode     = MODULEMODE_SWCTRL,
 390                 },
 391         },
 392 };
 393
 394 /* dcan1 */
 395 struct omap_hwmod am33xx_dcan1_hwmod = {
 396         .name           = "d_can1",
 397         .class          = &am33xx_dcan_hwmod_class,
 398         .clkdm_name     = "l4ls_clkdm",
 399         .main_clk       = "dcan1_fck",
 400         .prcm           = {
 401                 .omap4  = {
 402                         .modulemode     = MODULEMODE_SWCTRL,
 403                 },
 404         },
 405 };
 406
 407 /* elm */
 408 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
 409         .rev_offs       = 0x0000,
 410         .sysc_offs      = 0x0010,
 411         .syss_offs      = 0x0014,
 412         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 413                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 414                         SYSS_HAS_RESET_STATUS),
 415         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 416         .sysc_fields    = &omap_hwmod_sysc_type1,
 417 };
 418
 419 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 420         .name           = "elm",
 421         .sysc           = &am33xx_elm_sysc,
 422 };
 423
 424 struct omap_hwmod am33xx_elm_hwmod = {
 425         .name           = "elm",
 426         .class          = &am33xx_elm_hwmod_class,
 427         .clkdm_name     = "l4ls_clkdm",
 428         .main_clk       = "l4ls_gclk",
 429         .prcm           = {
 430                 .omap4  = {
 431                         .modulemode     = MODULEMODE_SWCTRL,
 432                 },
 433         },
 434 };
 435
 436 /* pwmss  */
 437 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 438         .rev_offs       = 0x0,
 439         .sysc_offs      = 0x4,
 440         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 441         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 442                         SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 443                         MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 444         .sysc_fields    = &omap_hwmod_sysc_type2,
 445 };
 446
 447 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 448         .name           = "epwmss",
 449         .sysc           = &am33xx_epwmss_sysc,
 450 };
 451
 452 static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
 453         .name           = "ecap",
 454 };
 455
 456 static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
 457         .name           = "eqep",
 458 };
 459
 460 struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
 461         .name           = "ehrpwm",
 462 };
 463
 464 /* epwmss0 */
 465 struct omap_hwmod am33xx_epwmss0_hwmod = {
 466         .name           = "epwmss0",
 467         .class          = &am33xx_epwmss_hwmod_class,
 468         .clkdm_name     = "l4ls_clkdm",
 469         .main_clk       = "l4ls_gclk",
 470         .prcm           = {
 471                 .omap4  = {
 472                         .modulemode     = MODULEMODE_SWCTRL,
 473                 },
 474         },
 475 };
 476
 477 /* ecap0 */
 478 struct omap_hwmod am33xx_ecap0_hwmod = {
 479         .name           = "ecap0",
 480         .class          = &am33xx_ecap_hwmod_class,
 481         .clkdm_name     = "l4ls_clkdm",
 482         .main_clk       = "l4ls_gclk",
 483 };
 484
 485 /* eqep0 */
 486 struct omap_hwmod am33xx_eqep0_hwmod = {
 487         .name           = "eqep0",
 488         .class          = &am33xx_eqep_hwmod_class,
 489         .clkdm_name     = "l4ls_clkdm",
 490         .main_clk       = "l4ls_gclk",
 491 };
 492
 493 /* ehrpwm0 */
 494 struct omap_hwmod am33xx_ehrpwm0_hwmod = {
 495         .name           = "ehrpwm0",
 496         .class          = &am33xx_ehrpwm_hwmod_class,
 497         .clkdm_name     = "l4ls_clkdm",
 498         .main_clk       = "l4ls_gclk",
 499 };
 500
 501 /* epwmss1 */
 502 struct omap_hwmod am33xx_epwmss1_hwmod = {
 503         .name           = "epwmss1",
 504         .class          = &am33xx_epwmss_hwmod_class,
 505         .clkdm_name     = "l4ls_clkdm",
 506         .main_clk       = "l4ls_gclk",
 507         .prcm           = {
 508                 .omap4  = {
 509                         .modulemode     = MODULEMODE_SWCTRL,
 510                 },
 511         },
 512 };
 513
 514 /* ecap1 */
 515 struct omap_hwmod am33xx_ecap1_hwmod = {
 516         .name           = "ecap1",
 517         .class          = &am33xx_ecap_hwmod_class,
 518         .clkdm_name     = "l4ls_clkdm",
 519         .main_clk       = "l4ls_gclk",
 520 };
 521
 522 /* eqep1 */
 523 struct omap_hwmod am33xx_eqep1_hwmod = {
 524         .name           = "eqep1",
 525         .class          = &am33xx_eqep_hwmod_class,
 526         .clkdm_name     = "l4ls_clkdm",
 527         .main_clk       = "l4ls_gclk",
 528 };
 529
 530 /* ehrpwm1 */
 531 struct omap_hwmod am33xx_ehrpwm1_hwmod = {
 532         .name           = "ehrpwm1",
 533         .class          = &am33xx_ehrpwm_hwmod_class,
 534         .clkdm_name     = "l4ls_clkdm",
 535         .main_clk       = "l4ls_gclk",
 536 };
 537
 538 /* epwmss2 */
 539 struct omap_hwmod am33xx_epwmss2_hwmod = {
 540         .name           = "epwmss2",
 541         .class          = &am33xx_epwmss_hwmod_class,
 542         .clkdm_name     = "l4ls_clkdm",
 543         .main_clk       = "l4ls_gclk",
 544         .prcm           = {
 545                 .omap4  = {
 546                         .modulemode     = MODULEMODE_SWCTRL,
 547                 },
 548         },
 549 };
 550
 551 /* ecap2 */
 552 struct omap_hwmod am33xx_ecap2_hwmod = {
 553         .name           = "ecap2",
 554         .class          = &am33xx_ecap_hwmod_class,
 555         .clkdm_name     = "l4ls_clkdm",
 556         .main_clk       = "l4ls_gclk",
 557 };
 558
 559 /* eqep2 */
 560 struct omap_hwmod am33xx_eqep2_hwmod = {
 561         .name           = "eqep2",
 562         .class          = &am33xx_eqep_hwmod_class,
 563         .clkdm_name     = "l4ls_clkdm",
 564         .main_clk       = "l4ls_gclk",
 565 };
 566
 567 /* ehrpwm2 */
 568 struct omap_hwmod am33xx_ehrpwm2_hwmod = {
 569         .name           = "ehrpwm2",
 570         .class          = &am33xx_ehrpwm_hwmod_class,
 571         .clkdm_name     = "l4ls_clkdm",
 572         .main_clk       = "l4ls_gclk",
 573 };
 574
 575 /*
 576  * 'gpio' class: for gpio 0,1,2,3
 577  */
 578 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
 579         .rev_offs       = 0x0000,
 580         .sysc_offs      = 0x0010,
 581         .syss_offs      = 0x0114,
 582         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 583                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 584                           SYSS_HAS_RESET_STATUS),
 585         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 586                           SIDLE_SMART_WKUP),
 587         .sysc_fields    = &omap_hwmod_sysc_type1,
 588 };
 589
 590 struct omap_hwmod_class am33xx_gpio_hwmod_class = {
 591         .name           = "gpio",
 592         .sysc           = &am33xx_gpio_sysc,
 593         .rev            = 2,
 594 };
 595
 596 struct omap_gpio_dev_attr gpio_dev_attr = {
 597         .bank_width     = 32,
 598         .dbck_flag      = true,
 599 };
 600
 601 /* gpio1 */
 602 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 603         { .role = "dbclk", .clk = "gpio1_dbclk" },
 604 };
 605
 606 struct omap_hwmod am33xx_gpio1_hwmod = {
 607         .name           = "gpio2",
 608         .class          = &am33xx_gpio_hwmod_class,
 609         .clkdm_name     = "l4ls_clkdm",
 610         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 611         .main_clk       = "l4ls_gclk",
 612         .prcm           = {
 613                 .omap4  = {
 614                         .modulemode     = MODULEMODE_SWCTRL,
 615                 },
 616         },
 617         .opt_clks       = gpio1_opt_clks,
 618         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 619         .dev_attr       = &gpio_dev_attr,
 620 };
 621
 622 /* gpio2 */
 623 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 624         { .role = "dbclk", .clk = "gpio2_dbclk" },
 625 };
 626
 627 struct omap_hwmod am33xx_gpio2_hwmod = {
 628         .name           = "gpio3",
 629         .class          = &am33xx_gpio_hwmod_class,
 630         .clkdm_name     = "l4ls_clkdm",
 631         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 632         .main_clk       = "l4ls_gclk",
 633         .prcm           = {
 634                 .omap4  = {
 635                         .modulemode     = MODULEMODE_SWCTRL,
 636                 },
 637         },
 638         .opt_clks       = gpio2_opt_clks,
 639         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 640         .dev_attr       = &gpio_dev_attr,
 641 };
 642
 643 /* gpio3 */
 644 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 645         { .role = "dbclk", .clk = "gpio3_dbclk" },
 646 };
 647
 648 struct omap_hwmod am33xx_gpio3_hwmod = {
 649         .name           = "gpio4",
 650         .class          = &am33xx_gpio_hwmod_class,
 651         .clkdm_name     = "l4ls_clkdm",
 652         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 653         .main_clk       = "l4ls_gclk",
 654         .prcm           = {
 655                 .omap4  = {
 656                         .modulemode     = MODULEMODE_SWCTRL,
 657                 },
 658         },
 659         .opt_clks       = gpio3_opt_clks,
 660         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 661         .dev_attr       = &gpio_dev_attr,
 662 };
 663
 664 /* gpmc */
 665 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
 666         .rev_offs       = 0x0,
 667         .sysc_offs      = 0x10,
 668         .syss_offs      = 0x14,
 669         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 670                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 671         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 672         .sysc_fields    = &omap_hwmod_sysc_type1,
 673 };
 674
 675 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
 676         .name           = "gpmc",
 677         .sysc           = &gpmc_sysc,
 678 };
 679
 680 struct omap_hwmod am33xx_gpmc_hwmod = {
 681         .name           = "gpmc",
 682         .class          = &am33xx_gpmc_hwmod_class,
 683         .clkdm_name     = "l3s_clkdm",
 684         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 685         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 686         .main_clk       = "l3s_gclk",
 687         .prcm           = {
 688                 .omap4  = {
 689                         .modulemode     = MODULEMODE_SWCTRL,
 690                 },
 691         },
 692 };
 693
 694 /* 'i2c' class */
 695 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
 696         .sysc_offs      = 0x0010,
 697         .syss_offs      = 0x0090,
 698         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 699                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 700                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 701         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 702                           SIDLE_SMART_WKUP),
 703         .sysc_fields    = &omap_hwmod_sysc_type1,
 704 };
 705
 706 static struct omap_hwmod_class i2c_class = {
 707         .name           = "i2c",
 708         .sysc           = &am33xx_i2c_sysc,
 709         .rev            = OMAP_I2C_IP_VERSION_2,
 710         .reset          = &omap_i2c_reset,
 711 };
 712
 713 static struct omap_i2c_dev_attr i2c_dev_attr = {
 714         .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 715 };
 716
 717 /* i2c1 */
 718 struct omap_hwmod am33xx_i2c1_hwmod = {
 719         .name           = "i2c1",
 720         .class          = &i2c_class,
 721         .clkdm_name     = "l4_wkup_clkdm",
 722         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 723         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
 724         .prcm           = {
 725                 .omap4  = {
 726                         .modulemode     = MODULEMODE_SWCTRL,
 727                 },
 728         },
 729         .dev_attr       = &i2c_dev_attr,
 730 };
 731
 732 /* i2c1 */
 733 struct omap_hwmod am33xx_i2c2_hwmod = {
 734         .name           = "i2c2",
 735         .class          = &i2c_class,
 736         .clkdm_name     = "l4ls_clkdm",
 737         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 738         .main_clk       = "dpll_per_m2_div4_ck",
 739         .prcm           = {
 740                 .omap4 = {
 741                         .modulemode     = MODULEMODE_SWCTRL,
 742                 },
 743         },
 744         .dev_attr       = &i2c_dev_attr,
 745 };
 746
 747 /* i2c3 */
 748 struct omap_hwmod am33xx_i2c3_hwmod = {
 749         .name           = "i2c3",
 750         .class          = &i2c_class,
 751         .clkdm_name     = "l4ls_clkdm",
 752         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 753         .main_clk       = "dpll_per_m2_div4_ck",
 754         .prcm           = {
 755                 .omap4  = {
 756                         .modulemode     = MODULEMODE_SWCTRL,
 757                 },
 758         },
 759         .dev_attr       = &i2c_dev_attr,
 760 };
 761
 762 /*
 763  * 'mailbox' class
 764  * mailbox module allowing communication between the on-chip processors using a
 765  * queued mailbox-interrupt mechanism.
 766  */
 767 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
 768         .rev_offs       = 0x0000,
 769         .sysc_offs      = 0x0010,
 770         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 771                           SYSC_HAS_SOFTRESET),
 772         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 773         .sysc_fields    = &omap_hwmod_sysc_type2,
 774 };
 775
 776 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
 777         .name   = "mailbox",
 778         .sysc   = &am33xx_mailbox_sysc,
 779 };
 780
 781 struct omap_hwmod am33xx_mailbox_hwmod = {
 782         .name           = "mailbox",
 783         .class          = &am33xx_mailbox_hwmod_class,
 784         .clkdm_name     = "l4ls_clkdm",
 785         .main_clk       = "l4ls_gclk",
 786         .prcm = {
 787                 .omap4 = {
 788                         .modulemode     = MODULEMODE_SWCTRL,
 789                 },
 790         },
 791 };
 792
 793 /*
 794  * 'mcasp' class
 795  */
 796 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
 797         .rev_offs       = 0x0,
 798         .sysc_offs      = 0x4,
 799         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 800         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 801         .sysc_fields    = &omap_hwmod_sysc_type3,
 802 };
 803
 804 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
 805         .name           = "mcasp",
 806         .sysc           = &am33xx_mcasp_sysc,
 807 };
 808
 809 /* mcasp0 */
 810 struct omap_hwmod am33xx_mcasp0_hwmod = {
 811         .name           = "mcasp0",
 812         .class          = &am33xx_mcasp_hwmod_class,
 813         .clkdm_name     = "l3s_clkdm",
 814         .main_clk       = "mcasp0_fck",
 815         .prcm           = {
 816                 .omap4  = {
 817                         .modulemode     = MODULEMODE_SWCTRL,
 818                 },
 819         },
 820 };
 821
 822 /* mcasp1 */
 823 struct omap_hwmod am33xx_mcasp1_hwmod = {
 824         .name           = "mcasp1",
 825         .class          = &am33xx_mcasp_hwmod_class,
 826         .clkdm_name     = "l3s_clkdm",
 827         .main_clk       = "mcasp1_fck",
 828         .prcm           = {
 829                 .omap4  = {
 830                         .modulemode     = MODULEMODE_SWCTRL,
 831                 },
 832         },
 833 };
 834
 835 /* 'mmc' class */
 836 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
 837         .rev_offs       = 0x1fc,
 838         .sysc_offs      = 0x10,
 839         .syss_offs      = 0x14,
 840         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 841                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 842                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 843         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 844         .sysc_fields    = &omap_hwmod_sysc_type1,
 845 };
 846
 847 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
 848         .name           = "mmc",
 849         .sysc           = &am33xx_mmc_sysc,
 850 };
 851
 852 /* mmc0 */
 853 static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr = {
 854         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 855 };
 856
 857 struct omap_hwmod am33xx_mmc0_hwmod = {
 858         .name           = "mmc1",
 859         .class          = &am33xx_mmc_hwmod_class,
 860         .clkdm_name     = "l4ls_clkdm",
 861         .main_clk       = "mmc_clk",
 862         .prcm           = {
 863                 .omap4  = {
 864                         .modulemode     = MODULEMODE_SWCTRL,
 865                 },
 866         },
 867         .dev_attr       = &am33xx_mmc0_dev_attr,
 868 };
 869
 870 /* mmc1 */
 871 static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr = {
 872         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 873 };
 874
 875 struct omap_hwmod am33xx_mmc1_hwmod = {
 876         .name           = "mmc2",
 877         .class          = &am33xx_mmc_hwmod_class,
 878         .clkdm_name     = "l4ls_clkdm",
 879         .main_clk       = "mmc_clk",
 880         .prcm           = {
 881                 .omap4  = {
 882                         .modulemode     = MODULEMODE_SWCTRL,
 883                 },
 884         },
 885         .dev_attr       = &am33xx_mmc1_dev_attr,
 886 };
 887
 888 /* mmc2 */
 889 static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr = {
 890         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 891 };
 892 struct omap_hwmod am33xx_mmc2_hwmod = {
 893         .name           = "mmc3",
 894         .class          = &am33xx_mmc_hwmod_class,
 895         .clkdm_name     = "l3s_clkdm",
 896         .main_clk       = "mmc_clk",
 897         .prcm           = {
 898                 .omap4  = {
 899                         .modulemode     = MODULEMODE_SWCTRL,
 900                 },
 901         },
 902         .dev_attr       = &am33xx_mmc2_dev_attr,
 903 };
 904
 905 /*
 906  * 'rtc' class
 907  * rtc subsystem
 908  */
 909 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
 910         .rev_offs       = 0x0074,
 911         .sysc_offs      = 0x0078,
 912         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 913         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
 914                           SIDLE_SMART | SIDLE_SMART_WKUP),
 915         .sysc_fields    = &omap_hwmod_sysc_type3,
 916 };
 917
 918 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
 919         .name           = "rtc",
 920         .sysc           = &am33xx_rtc_sysc,
 921         .unlock         = &omap_hwmod_rtc_unlock,
 922         .lock           = &omap_hwmod_rtc_lock,
 923 };
 924
 925 struct omap_hwmod am33xx_rtc_hwmod = {
 926         .name           = "rtc",
 927         .class          = &am33xx_rtc_hwmod_class,
 928         .clkdm_name     = "l4_rtc_clkdm",
 929         .main_clk       = "clk_32768_ck",
 930         .prcm           = {
 931                 .omap4  = {
 932                         .modulemode     = MODULEMODE_SWCTRL,
 933                 },
 934         },
 935 };
 936
 937 /* 'spi' class */
 938 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
 939         .rev_offs       = 0x0000,
 940         .sysc_offs      = 0x0110,
 941         .syss_offs      = 0x0114,
 942         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 943                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 944                           SYSS_HAS_RESET_STATUS),
 945         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 946         .sysc_fields    = &omap_hwmod_sysc_type1,
 947 };
 948
 949 struct omap_hwmod_class am33xx_spi_hwmod_class = {
 950         .name           = "mcspi",
 951         .sysc           = &am33xx_mcspi_sysc,
 952         .rev            = OMAP4_MCSPI_REV,
 953 };
 954
 955 /* spi0 */
 956 struct omap2_mcspi_dev_attr mcspi_attrib = {
 957         .num_chipselect = 2,
 958 };
 959 struct omap_hwmod am33xx_spi0_hwmod = {
 960         .name           = "spi0",
 961         .class          = &am33xx_spi_hwmod_class,
 962         .clkdm_name     = "l4ls_clkdm",
 963         .main_clk       = "dpll_per_m2_div4_ck",
 964         .prcm           = {
 965                 .omap4  = {
 966                         .modulemode     = MODULEMODE_SWCTRL,
 967                 },
 968         },
 969         .dev_attr       = &mcspi_attrib,
 970 };
 971
 972 /* spi1 */
 973 struct omap_hwmod am33xx_spi1_hwmod = {
 974         .name           = "spi1",
 975         .class          = &am33xx_spi_hwmod_class,
 976         .clkdm_name     = "l4ls_clkdm",
 977         .main_clk       = "dpll_per_m2_div4_ck",
 978         .prcm           = {
 979                 .omap4  = {
 980                         .modulemode     = MODULEMODE_SWCTRL,
 981                 },
 982         },
 983         .dev_attr       = &mcspi_attrib,
 984 };
 985
 986 /*
 987  * 'spinlock' class
 988  * spinlock provides hardware assistance for synchronizing the
 989  * processes running on multiple processors
 990  */
 991
 992 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
 993         .rev_offs       = 0x0000,
 994         .sysc_offs      = 0x0010,
 995         .syss_offs      = 0x0014,
 996         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 997                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 998                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 999         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1000         .sysc_fields    = &omap_hwmod_sysc_type1,
1001 };
1002
1003 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1004         .name           = "spinlock",
1005         .sysc           = &am33xx_spinlock_sysc,
1006 };
1007
1008 struct omap_hwmod am33xx_spinlock_hwmod = {
1009         .name           = "spinlock",
1010         .class          = &am33xx_spinlock_hwmod_class,
1011         .clkdm_name     = "l4ls_clkdm",
1012         .main_clk       = "l4ls_gclk",
1013         .prcm           = {
1014                 .omap4  = {
1015                         .modulemode     = MODULEMODE_SWCTRL,
1016                 },
1017         },
1018 };
1019
1020 /* 'timer 2-7' class */
1021 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1022         .rev_offs       = 0x0000,
1023         .sysc_offs      = 0x0010,
1024         .syss_offs      = 0x0014,
1025         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1026         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1027                           SIDLE_SMART_WKUP),
1028         .sysc_fields    = &omap_hwmod_sysc_type2,
1029 };
1030
1031 struct omap_hwmod_class am33xx_timer_hwmod_class = {
1032         .name           = "timer",
1033         .sysc           = &am33xx_timer_sysc,
1034 };
1035
1036 /* timer1 1ms */
1037 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1038         .rev_offs       = 0x0000,
1039         .sysc_offs      = 0x0010,
1040         .syss_offs      = 0x0014,
1041         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1042                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1043                         SYSS_HAS_RESET_STATUS),
1044         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1045         .sysc_fields    = &omap_hwmod_sysc_type1,
1046 };
1047
1048 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1049         .name           = "timer",
1050         .sysc           = &am33xx_timer1ms_sysc,
1051 };
1052
1053 struct omap_hwmod am33xx_timer1_hwmod = {
1054         .name           = "timer1",
1055         .class          = &am33xx_timer1ms_hwmod_class,
1056         .clkdm_name     = "l4_wkup_clkdm",
1057         .main_clk       = "timer1_fck",
1058         .prcm           = {
1059                 .omap4  = {
1060                         .modulemode     = MODULEMODE_SWCTRL,
1061                 },
1062         },
1063 };
1064
1065 struct omap_hwmod am33xx_timer2_hwmod = {
1066         .name           = "timer2",
1067         .class          = &am33xx_timer_hwmod_class,
1068         .clkdm_name     = "l4ls_clkdm",
1069         .main_clk       = "timer2_fck",
1070         .prcm           = {
1071                 .omap4  = {
1072                         .modulemode     = MODULEMODE_SWCTRL,
1073                 },
1074         },
1075 };
1076
1077 struct omap_hwmod am33xx_timer3_hwmod = {
1078         .name           = "timer3",
1079         .class          = &am33xx_timer_hwmod_class,
1080         .clkdm_name     = "l4ls_clkdm",
1081         .main_clk       = "timer3_fck",
1082         .prcm           = {
1083                 .omap4  = {
1084                         .modulemode     = MODULEMODE_SWCTRL,
1085                 },
1086         },
1087 };
1088
1089 struct omap_hwmod am33xx_timer4_hwmod = {
1090         .name           = "timer4",
1091         .class          = &am33xx_timer_hwmod_class,
1092         .clkdm_name     = "l4ls_clkdm",
1093         .main_clk       = "timer4_fck",
1094         .prcm           = {
1095                 .omap4  = {
1096                         .modulemode     = MODULEMODE_SWCTRL,
1097                 },
1098         },
1099 };
1100
1101 struct omap_hwmod am33xx_timer5_hwmod = {
1102         .name           = "timer5",
1103         .class          = &am33xx_timer_hwmod_class,
1104         .clkdm_name     = "l4ls_clkdm",
1105         .main_clk       = "timer5_fck",
1106         .prcm           = {
1107                 .omap4  = {
1108                         .modulemode     = MODULEMODE_SWCTRL,
1109                 },
1110         },
1111 };
1112
1113 struct omap_hwmod am33xx_timer6_hwmod = {
1114         .name           = "timer6",
1115         .class          = &am33xx_timer_hwmod_class,
1116         .clkdm_name     = "l4ls_clkdm",
1117         .main_clk       = "timer6_fck",
1118         .prcm           = {
1119                 .omap4  = {
1120                         .modulemode     = MODULEMODE_SWCTRL,
1121                 },
1122         },
1123 };
1124
1125 struct omap_hwmod am33xx_timer7_hwmod = {
1126         .name           = "timer7",
1127         .class          = &am33xx_timer_hwmod_class,
1128         .clkdm_name     = "l4ls_clkdm",
1129         .main_clk       = "timer7_fck",
1130         .prcm           = {
1131                 .omap4  = {
1132                         .modulemode     = MODULEMODE_SWCTRL,
1133                 },
1134         },
1135 };
1136
1137 /* tpcc */
1138 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1139         .name           = "tpcc",
1140 };
1141
1142 struct omap_hwmod am33xx_tpcc_hwmod = {
1143         .name           = "tpcc",
1144         .class          = &am33xx_tpcc_hwmod_class,
1145         .clkdm_name     = "l3_clkdm",
1146         .main_clk       = "l3_gclk",
1147         .prcm           = {
1148                 .omap4  = {
1149                         .modulemode     = MODULEMODE_SWCTRL,
1150                 },
1151         },
1152 };
1153
1154 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1155         .rev_offs       = 0x0,
1156         .sysc_offs      = 0x10,
1157         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1158                           SYSC_HAS_MIDLEMODE),
1159         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1160         .sysc_fields    = &omap_hwmod_sysc_type2,
1161 };
1162
1163 /* 'tptc' class */
1164 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1165         .name           = "tptc",
1166         .sysc           = &am33xx_tptc_sysc,
1167 };
1168
1169 /* tptc0 */
1170 struct omap_hwmod am33xx_tptc0_hwmod = {
1171         .name           = "tptc0",
1172         .class          = &am33xx_tptc_hwmod_class,
1173         .clkdm_name     = "l3_clkdm",
1174         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1175         .main_clk       = "l3_gclk",
1176         .prcm           = {
1177                 .omap4  = {
1178                         .modulemode     = MODULEMODE_SWCTRL,
1179                 },
1180         },
1181 };
1182
1183 /* tptc1 */
1184 struct omap_hwmod am33xx_tptc1_hwmod = {
1185         .name           = "tptc1",
1186         .class          = &am33xx_tptc_hwmod_class,
1187         .clkdm_name     = "l3_clkdm",
1188         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1189         .main_clk       = "l3_gclk",
1190         .prcm           = {
1191                 .omap4  = {
1192                         .modulemode     = MODULEMODE_SWCTRL,
1193                 },
1194         },
1195 };
1196
1197 /* tptc2 */
1198 struct omap_hwmod am33xx_tptc2_hwmod = {
1199         .name           = "tptc2",
1200         .class          = &am33xx_tptc_hwmod_class,
1201         .clkdm_name     = "l3_clkdm",
1202         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1203         .main_clk       = "l3_gclk",
1204         .prcm           = {
1205                 .omap4  = {
1206                         .modulemode     = MODULEMODE_SWCTRL,
1207                 },
1208         },
1209 };
1210
1211 /* 'uart' class */
1212 static struct omap_hwmod_class_sysconfig uart_sysc = {
1213         .rev_offs       = 0x50,
1214         .sysc_offs      = 0x54,
1215         .syss_offs      = 0x58,
1216         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1217                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1218         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1219                           SIDLE_SMART_WKUP),
1220         .sysc_fields    = &omap_hwmod_sysc_type1,
1221 };
1222
1223 static struct omap_hwmod_class uart_class = {
1224         .name           = "uart",
1225         .sysc           = &uart_sysc,
1226 };
1227
1228 struct omap_hwmod am33xx_uart1_hwmod = {
1229         .name           = "uart1",
1230         .class          = &uart_class,
1231         .clkdm_name     = "l4_wkup_clkdm",
1232         .flags          = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1233         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
1234         .prcm           = {
1235                 .omap4  = {
1236                         .modulemode     = MODULEMODE_SWCTRL,
1237                 },
1238         },
1239 };
1240
1241 struct omap_hwmod am33xx_uart2_hwmod = {
1242         .name           = "uart2",
1243         .class          = &uart_class,
1244         .clkdm_name     = "l4ls_clkdm",
1245         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1246         .main_clk       = "dpll_per_m2_div4_ck",
1247         .prcm           = {
1248                 .omap4  = {
1249                         .modulemode     = MODULEMODE_SWCTRL,
1250                 },
1251         },
1252 };
1253
1254 /* uart3 */
1255 struct omap_hwmod am33xx_uart3_hwmod = {
1256         .name           = "uart3",
1257         .class          = &uart_class,
1258         .clkdm_name     = "l4ls_clkdm",
1259         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1260         .main_clk       = "dpll_per_m2_div4_ck",
1261         .prcm           = {
1262                 .omap4  = {
1263                         .modulemode     = MODULEMODE_SWCTRL,
1264                 },
1265         },
1266 };
1267
1268 struct omap_hwmod am33xx_uart4_hwmod = {
1269         .name           = "uart4",
1270         .class          = &uart_class,
1271         .clkdm_name     = "l4ls_clkdm",
1272         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1273         .main_clk       = "dpll_per_m2_div4_ck",
1274         .prcm           = {
1275                 .omap4  = {
1276                         .modulemode     = MODULEMODE_SWCTRL,
1277                 },
1278         },
1279 };
1280
1281 struct omap_hwmod am33xx_uart5_hwmod = {
1282         .name           = "uart5",
1283         .class          = &uart_class,
1284         .clkdm_name     = "l4ls_clkdm",
1285         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1286         .main_clk       = "dpll_per_m2_div4_ck",
1287         .prcm           = {
1288                 .omap4  = {
1289                         .modulemode     = MODULEMODE_SWCTRL,
1290                 },
1291         },
1292 };
1293
1294 struct omap_hwmod am33xx_uart6_hwmod = {
1295         .name           = "uart6",
1296         .class          = &uart_class,
1297         .clkdm_name     = "l4ls_clkdm",
1298         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1299         .main_clk       = "dpll_per_m2_div4_ck",
1300         .prcm           = {
1301                 .omap4  = {
1302                         .modulemode     = MODULEMODE_SWCTRL,
1303                 },
1304         },
1305 };
1306
1307 /* 'wd_timer' class */
1308 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1309         .rev_offs       = 0x0,
1310         .sysc_offs      = 0x10,
1311         .syss_offs      = 0x14,
1312         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1313                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1314         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1315                         SIDLE_SMART_WKUP),
1316         .sysc_fields    = &omap_hwmod_sysc_type1,
1317 };
1318
1319 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1320         .name           = "wd_timer",
1321         .sysc           = &wdt_sysc,
1322         .pre_shutdown   = &omap2_wd_timer_disable,
1323 };
1324
1325 /*
1326  * XXX: device.c file uses hardcoded name for watchdog timer
1327  * driver "wd_timer2, so we are also using same name as of now...
1328  */
1329 struct omap_hwmod am33xx_wd_timer1_hwmod = {
1330         .name           = "wd_timer2",
1331         .class          = &am33xx_wd_timer_hwmod_class,
1332         .clkdm_name     = "l4_wkup_clkdm",
1333         .flags          = HWMOD_SWSUP_SIDLE,
1334         .main_clk       = "wdt1_fck",
1335         .prcm           = {
1336                 .omap4  = {
1337                         .modulemode     = MODULEMODE_SWCTRL,
1338                 },
1339         },
1340 };
1341
1342 static void omap_hwmod_am33xx_clkctrl(void)
1343 {
1344         CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
1345         CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
1346         CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
1347         CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
1348         CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
1349         CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1350         CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1351         CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1352         CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1353         CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1354         CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1355         CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1356         CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1357         CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1358         CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1359         CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1360         CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1361         CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1362         CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1363         CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1364         CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1365         CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1366         CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1367         CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1368         CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1369         CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1370         CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1371         CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1372         CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1373         CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1374         CLKCTRL(am33xx_smartreflex0_hwmod,
1375                 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1376         CLKCTRL(am33xx_smartreflex1_hwmod,
1377                 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1378         CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1379         CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1380         CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1381         CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1382         CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1383         CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1384         CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1385         CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1386         CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1387         CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1388         CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1389         CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1390         CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1391         CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1392         CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1393         CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1394         CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1395         CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1396         CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1397         CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1398         CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1399         CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1400 }
1401
1402 static void omap_hwmod_am33xx_rst(void)
1403 {
1404         RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1405         RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1406         RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1407 }
1408
1409 void omap_hwmod_am33xx_reg(void)
1410 {
1411         omap_hwmod_am33xx_clkctrl();
1412         omap_hwmod_am33xx_rst();
1413 }
1414
1415 static void omap_hwmod_am43xx_clkctrl(void)
1416 {
1417         CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1418         CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1419         CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1420         CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1421         CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1422         CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1423         CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1424         CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1425         CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1426         CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1427         CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1428         CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1429         CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1430         CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1431         CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1432         CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1433         CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1434         CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1435         CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1436         CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1437         CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1438         CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1439         CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1440         CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1441         CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1442         CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1443         CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1444         CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1445         CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1446         CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1447         CLKCTRL(am33xx_smartreflex0_hwmod,
1448                 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1449         CLKCTRL(am33xx_smartreflex1_hwmod,
1450                 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1451         CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1452         CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1453         CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1454         CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1455         CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1456         CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1457         CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1458         CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1459         CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1460         CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1461         CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1462         CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1463         CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1464         CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1465         CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1466         CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1467         CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1468         CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1469         CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1470         CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1471         CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1472         CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1473 }
1474
1475 static void omap_hwmod_am43xx_rst(void)
1476 {
1477         RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1478         RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1479         RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1480 }
1481
1482 void omap_hwmod_am43xx_reg(void)
1483 {
1484         omap_hwmod_am43xx_clkctrl();
1485         omap_hwmod_am43xx_rst();
1486 }