2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/power/smartreflex.h>
24 #include <plat/omap_hwmod.h>
27 #include <plat/gpio.h>
29 #include <plat/mcspi.h>
30 #include <plat/mcbsp.h>
32 #include <plat/dmtimer.h>
33 #include <plat/common.h>
35 #include "omap_hwmod_common_data.h"
39 #include "prm-regbits-44xx.h"
42 /* Base offset for all OMAP4 interrupts external to MPUSS */
43 #define OMAP44XX_IRQ_GIC_START 32
45 /* Base offset for all OMAP4 dma requests */
46 #define OMAP44XX_DMA_REQ_START 1
53 * 'c2c_target_fw' class
54 * instance(s): c2c_target_fw
56 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class
= {
57 .name
= "c2c_target_fw",
61 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod
= {
62 .name
= "c2c_target_fw",
63 .class = &omap44xx_c2c_target_fw_hwmod_class
,
64 .clkdm_name
= "d2d_clkdm",
67 .clkctrl_offs
= OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET
,
68 .context_offs
= OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET
,
77 static struct omap_hwmod_class omap44xx_dmm_hwmod_class
= {
82 static struct omap_hwmod_irq_info omap44xx_dmm_irqs
[] = {
83 { .irq
= 113 + OMAP44XX_IRQ_GIC_START
},
87 static struct omap_hwmod omap44xx_dmm_hwmod
= {
89 .class = &omap44xx_dmm_hwmod_class
,
90 .clkdm_name
= "l3_emif_clkdm",
91 .mpu_irqs
= omap44xx_dmm_irqs
,
94 .clkctrl_offs
= OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET
,
95 .context_offs
= OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET
,
102 * instance(s): emif_fw
104 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class
= {
109 static struct omap_hwmod omap44xx_emif_fw_hwmod
= {
111 .class = &omap44xx_emif_fw_hwmod_class
,
112 .clkdm_name
= "l3_emif_clkdm",
115 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET
,
116 .context_offs
= OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET
,
123 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
125 static struct omap_hwmod_class omap44xx_l3_hwmod_class
= {
130 static struct omap_hwmod omap44xx_l3_instr_hwmod
= {
132 .class = &omap44xx_l3_hwmod_class
,
133 .clkdm_name
= "l3_instr_clkdm",
136 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
,
137 .context_offs
= OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
,
138 .modulemode
= MODULEMODE_HWCTRL
,
144 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs
[] = {
145 { .name
= "dbg_err", .irq
= 9 + OMAP44XX_IRQ_GIC_START
},
146 { .name
= "app_err", .irq
= 10 + OMAP44XX_IRQ_GIC_START
},
150 static struct omap_hwmod omap44xx_l3_main_1_hwmod
= {
152 .class = &omap44xx_l3_hwmod_class
,
153 .clkdm_name
= "l3_1_clkdm",
154 .mpu_irqs
= omap44xx_l3_main_1_irqs
,
157 .clkctrl_offs
= OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET
,
158 .context_offs
= OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET
,
164 static struct omap_hwmod omap44xx_l3_main_2_hwmod
= {
166 .class = &omap44xx_l3_hwmod_class
,
167 .clkdm_name
= "l3_2_clkdm",
170 .clkctrl_offs
= OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET
,
171 .context_offs
= OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET
,
177 static struct omap_hwmod omap44xx_l3_main_3_hwmod
= {
179 .class = &omap44xx_l3_hwmod_class
,
180 .clkdm_name
= "l3_instr_clkdm",
183 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET
,
184 .context_offs
= OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET
,
185 .modulemode
= MODULEMODE_HWCTRL
,
192 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
194 static struct omap_hwmod_class omap44xx_l4_hwmod_class
= {
199 static struct omap_hwmod omap44xx_l4_abe_hwmod
= {
201 .class = &omap44xx_l4_hwmod_class
,
202 .clkdm_name
= "abe_clkdm",
205 .clkctrl_offs
= OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET
,
211 static struct omap_hwmod omap44xx_l4_cfg_hwmod
= {
213 .class = &omap44xx_l4_hwmod_class
,
214 .clkdm_name
= "l4_cfg_clkdm",
217 .clkctrl_offs
= OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
,
218 .context_offs
= OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
,
224 static struct omap_hwmod omap44xx_l4_per_hwmod
= {
226 .class = &omap44xx_l4_hwmod_class
,
227 .clkdm_name
= "l4_per_clkdm",
230 .clkctrl_offs
= OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET
,
231 .context_offs
= OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET
,
237 static struct omap_hwmod omap44xx_l4_wkup_hwmod
= {
239 .class = &omap44xx_l4_hwmod_class
,
240 .clkdm_name
= "l4_wkup_clkdm",
243 .clkctrl_offs
= OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
,
244 .context_offs
= OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET
,
251 * instance(s): mpu_private
253 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class
= {
258 static struct omap_hwmod omap44xx_mpu_private_hwmod
= {
259 .name
= "mpu_private",
260 .class = &omap44xx_mpu_bus_hwmod_class
,
261 .clkdm_name
= "mpuss_clkdm",
266 * instance(s): ocp_wp_noc
268 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class
= {
269 .name
= "ocp_wp_noc",
273 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod
= {
274 .name
= "ocp_wp_noc",
275 .class = &omap44xx_ocp_wp_noc_hwmod_class
,
276 .clkdm_name
= "l3_instr_clkdm",
279 .clkctrl_offs
= OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET
,
280 .context_offs
= OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET
,
281 .modulemode
= MODULEMODE_HWCTRL
,
287 * Modules omap_hwmod structures
289 * The following IPs are excluded for the moment because:
290 * - They do not need an explicit SW control using omap_hwmod API.
291 * - They still need to be validated with the driver
292 * properly adapted to omap_hwmod / omap_device
299 * audio engine sub system
302 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc
= {
305 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
306 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
307 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
|
308 MSTANDBY_SMART_WKUP
),
309 .sysc_fields
= &omap_hwmod_sysc_type2
,
312 static struct omap_hwmod_class omap44xx_aess_hwmod_class
= {
314 .sysc
= &omap44xx_aess_sysc
,
318 static struct omap_hwmod_irq_info omap44xx_aess_irqs
[] = {
319 { .irq
= 99 + OMAP44XX_IRQ_GIC_START
},
323 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs
[] = {
324 { .name
= "fifo0", .dma_req
= 100 + OMAP44XX_DMA_REQ_START
},
325 { .name
= "fifo1", .dma_req
= 101 + OMAP44XX_DMA_REQ_START
},
326 { .name
= "fifo2", .dma_req
= 102 + OMAP44XX_DMA_REQ_START
},
327 { .name
= "fifo3", .dma_req
= 103 + OMAP44XX_DMA_REQ_START
},
328 { .name
= "fifo4", .dma_req
= 104 + OMAP44XX_DMA_REQ_START
},
329 { .name
= "fifo5", .dma_req
= 105 + OMAP44XX_DMA_REQ_START
},
330 { .name
= "fifo6", .dma_req
= 106 + OMAP44XX_DMA_REQ_START
},
331 { .name
= "fifo7", .dma_req
= 107 + OMAP44XX_DMA_REQ_START
},
335 static struct omap_hwmod omap44xx_aess_hwmod
= {
337 .class = &omap44xx_aess_hwmod_class
,
338 .clkdm_name
= "abe_clkdm",
339 .mpu_irqs
= omap44xx_aess_irqs
,
340 .sdma_reqs
= omap44xx_aess_sdma_reqs
,
341 .main_clk
= "aess_fck",
344 .clkctrl_offs
= OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET
,
345 .context_offs
= OMAP4_RM_ABE_AESS_CONTEXT_OFFSET
,
346 .modulemode
= MODULEMODE_SWCTRL
,
353 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
357 static struct omap_hwmod_class omap44xx_c2c_hwmod_class
= {
362 static struct omap_hwmod_irq_info omap44xx_c2c_irqs
[] = {
363 { .irq
= 88 + OMAP44XX_IRQ_GIC_START
},
367 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs
[] = {
368 { .dma_req
= 68 + OMAP44XX_DMA_REQ_START
},
372 static struct omap_hwmod omap44xx_c2c_hwmod
= {
374 .class = &omap44xx_c2c_hwmod_class
,
375 .clkdm_name
= "d2d_clkdm",
376 .mpu_irqs
= omap44xx_c2c_irqs
,
377 .sdma_reqs
= omap44xx_c2c_sdma_reqs
,
380 .clkctrl_offs
= OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET
,
381 .context_offs
= OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET
,
388 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
391 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc
= {
394 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
395 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
),
396 .sysc_fields
= &omap_hwmod_sysc_type1
,
399 static struct omap_hwmod_class omap44xx_counter_hwmod_class
= {
401 .sysc
= &omap44xx_counter_sysc
,
405 static struct omap_hwmod omap44xx_counter_32k_hwmod
= {
406 .name
= "counter_32k",
407 .class = &omap44xx_counter_hwmod_class
,
408 .clkdm_name
= "l4_wkup_clkdm",
409 .flags
= HWMOD_SWSUP_SIDLE
,
410 .main_clk
= "sys_32k_ck",
413 .clkctrl_offs
= OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET
,
414 .context_offs
= OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET
,
420 * 'ctrl_module' class
421 * attila core control module + core pad control module + wkup pad control
422 * module + attila wkup control module
425 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc
= {
428 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
429 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
431 .sysc_fields
= &omap_hwmod_sysc_type2
,
434 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class
= {
435 .name
= "ctrl_module",
436 .sysc
= &omap44xx_ctrl_module_sysc
,
439 /* ctrl_module_core */
440 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs
[] = {
441 { .irq
= 8 + OMAP44XX_IRQ_GIC_START
},
445 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod
= {
446 .name
= "ctrl_module_core",
447 .class = &omap44xx_ctrl_module_hwmod_class
,
448 .clkdm_name
= "l4_cfg_clkdm",
449 .mpu_irqs
= omap44xx_ctrl_module_core_irqs
,
452 /* ctrl_module_pad_core */
453 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod
= {
454 .name
= "ctrl_module_pad_core",
455 .class = &omap44xx_ctrl_module_hwmod_class
,
456 .clkdm_name
= "l4_cfg_clkdm",
459 /* ctrl_module_wkup */
460 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod
= {
461 .name
= "ctrl_module_wkup",
462 .class = &omap44xx_ctrl_module_hwmod_class
,
463 .clkdm_name
= "l4_wkup_clkdm",
466 /* ctrl_module_pad_wkup */
467 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod
= {
468 .name
= "ctrl_module_pad_wkup",
469 .class = &omap44xx_ctrl_module_hwmod_class
,
470 .clkdm_name
= "l4_wkup_clkdm",
475 * debug and emulation sub system
478 static struct omap_hwmod_class omap44xx_debugss_hwmod_class
= {
483 static struct omap_hwmod omap44xx_debugss_hwmod
= {
485 .class = &omap44xx_debugss_hwmod_class
,
486 .clkdm_name
= "emu_sys_clkdm",
487 .main_clk
= "trace_clk_div_ck",
490 .clkctrl_offs
= OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET
,
491 .context_offs
= OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET
,
498 * dma controller for data exchange between memory to memory (i.e. internal or
499 * external memory) and gp peripherals to memory or memory to gp peripherals
502 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc
= {
506 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
507 SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
508 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
509 SYSS_HAS_RESET_STATUS
),
510 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
511 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
512 .sysc_fields
= &omap_hwmod_sysc_type1
,
515 static struct omap_hwmod_class omap44xx_dma_hwmod_class
= {
517 .sysc
= &omap44xx_dma_sysc
,
521 static struct omap_dma_dev_attr dma_dev_attr
= {
522 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
523 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
528 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs
[] = {
529 { .name
= "0", .irq
= 12 + OMAP44XX_IRQ_GIC_START
},
530 { .name
= "1", .irq
= 13 + OMAP44XX_IRQ_GIC_START
},
531 { .name
= "2", .irq
= 14 + OMAP44XX_IRQ_GIC_START
},
532 { .name
= "3", .irq
= 15 + OMAP44XX_IRQ_GIC_START
},
536 static struct omap_hwmod omap44xx_dma_system_hwmod
= {
537 .name
= "dma_system",
538 .class = &omap44xx_dma_hwmod_class
,
539 .clkdm_name
= "l3_dma_clkdm",
540 .mpu_irqs
= omap44xx_dma_system_irqs
,
541 .main_clk
= "l3_div_ck",
544 .clkctrl_offs
= OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET
,
545 .context_offs
= OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET
,
548 .dev_attr
= &dma_dev_attr
,
553 * digital microphone controller
556 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc
= {
559 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
560 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
561 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
563 .sysc_fields
= &omap_hwmod_sysc_type2
,
566 static struct omap_hwmod_class omap44xx_dmic_hwmod_class
= {
568 .sysc
= &omap44xx_dmic_sysc
,
572 static struct omap_hwmod_irq_info omap44xx_dmic_irqs
[] = {
573 { .irq
= 114 + OMAP44XX_IRQ_GIC_START
},
577 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs
[] = {
578 { .dma_req
= 66 + OMAP44XX_DMA_REQ_START
},
582 static struct omap_hwmod omap44xx_dmic_hwmod
= {
584 .class = &omap44xx_dmic_hwmod_class
,
585 .clkdm_name
= "abe_clkdm",
586 .mpu_irqs
= omap44xx_dmic_irqs
,
587 .sdma_reqs
= omap44xx_dmic_sdma_reqs
,
588 .main_clk
= "dmic_fck",
591 .clkctrl_offs
= OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET
,
592 .context_offs
= OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET
,
593 .modulemode
= MODULEMODE_SWCTRL
,
603 static struct omap_hwmod_class omap44xx_dsp_hwmod_class
= {
608 static struct omap_hwmod_irq_info omap44xx_dsp_irqs
[] = {
609 { .irq
= 28 + OMAP44XX_IRQ_GIC_START
},
613 static struct omap_hwmod_rst_info omap44xx_dsp_resets
[] = {
614 { .name
= "dsp", .rst_shift
= 0 },
615 { .name
= "mmu_cache", .rst_shift
= 1 },
618 static struct omap_hwmod omap44xx_dsp_hwmod
= {
620 .class = &omap44xx_dsp_hwmod_class
,
621 .clkdm_name
= "tesla_clkdm",
622 .mpu_irqs
= omap44xx_dsp_irqs
,
623 .rst_lines
= omap44xx_dsp_resets
,
624 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_dsp_resets
),
625 .main_clk
= "dsp_fck",
628 .clkctrl_offs
= OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET
,
629 .rstctrl_offs
= OMAP4_RM_TESLA_RSTCTRL_OFFSET
,
630 .context_offs
= OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET
,
631 .modulemode
= MODULEMODE_HWCTRL
,
641 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc
= {
644 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
647 static struct omap_hwmod_class omap44xx_dss_hwmod_class
= {
649 .sysc
= &omap44xx_dss_sysc
,
650 .reset
= omap_dss_reset
,
654 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
655 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
656 { .role
= "tv_clk", .clk
= "dss_tv_clk" },
657 { .role
= "hdmi_clk", .clk
= "dss_48mhz_clk" },
660 static struct omap_hwmod omap44xx_dss_hwmod
= {
662 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
663 .class = &omap44xx_dss_hwmod_class
,
664 .clkdm_name
= "l3_dss_clkdm",
665 .main_clk
= "dss_dss_clk",
668 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
669 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
672 .opt_clks
= dss_opt_clks
,
673 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
681 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc
= {
685 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
686 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_MIDLEMODE
|
687 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
688 SYSS_HAS_RESET_STATUS
),
689 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
690 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
691 .sysc_fields
= &omap_hwmod_sysc_type1
,
694 static struct omap_hwmod_class omap44xx_dispc_hwmod_class
= {
696 .sysc
= &omap44xx_dispc_sysc
,
700 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs
[] = {
701 { .irq
= 25 + OMAP44XX_IRQ_GIC_START
},
705 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs
[] = {
706 { .dma_req
= 5 + OMAP44XX_DMA_REQ_START
},
710 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr
= {
712 .has_framedonetv_irq
= 1
715 static struct omap_hwmod omap44xx_dss_dispc_hwmod
= {
717 .class = &omap44xx_dispc_hwmod_class
,
718 .clkdm_name
= "l3_dss_clkdm",
719 .mpu_irqs
= omap44xx_dss_dispc_irqs
,
720 .sdma_reqs
= omap44xx_dss_dispc_sdma_reqs
,
721 .main_clk
= "dss_dss_clk",
724 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
725 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
728 .dev_attr
= &omap44xx_dss_dispc_dev_attr
733 * display serial interface controller
736 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc
= {
740 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
741 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
742 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
743 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
744 .sysc_fields
= &omap_hwmod_sysc_type1
,
747 static struct omap_hwmod_class omap44xx_dsi_hwmod_class
= {
749 .sysc
= &omap44xx_dsi_sysc
,
753 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs
[] = {
754 { .irq
= 53 + OMAP44XX_IRQ_GIC_START
},
758 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs
[] = {
759 { .dma_req
= 74 + OMAP44XX_DMA_REQ_START
},
763 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks
[] = {
764 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
767 static struct omap_hwmod omap44xx_dss_dsi1_hwmod
= {
769 .class = &omap44xx_dsi_hwmod_class
,
770 .clkdm_name
= "l3_dss_clkdm",
771 .mpu_irqs
= omap44xx_dss_dsi1_irqs
,
772 .sdma_reqs
= omap44xx_dss_dsi1_sdma_reqs
,
773 .main_clk
= "dss_dss_clk",
776 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
777 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
780 .opt_clks
= dss_dsi1_opt_clks
,
781 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi1_opt_clks
),
785 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs
[] = {
786 { .irq
= 84 + OMAP44XX_IRQ_GIC_START
},
790 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs
[] = {
791 { .dma_req
= 83 + OMAP44XX_DMA_REQ_START
},
795 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks
[] = {
796 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
799 static struct omap_hwmod omap44xx_dss_dsi2_hwmod
= {
801 .class = &omap44xx_dsi_hwmod_class
,
802 .clkdm_name
= "l3_dss_clkdm",
803 .mpu_irqs
= omap44xx_dss_dsi2_irqs
,
804 .sdma_reqs
= omap44xx_dss_dsi2_sdma_reqs
,
805 .main_clk
= "dss_dss_clk",
808 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
809 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
812 .opt_clks
= dss_dsi2_opt_clks
,
813 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi2_opt_clks
),
821 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc
= {
824 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
826 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
828 .sysc_fields
= &omap_hwmod_sysc_type2
,
831 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class
= {
833 .sysc
= &omap44xx_hdmi_sysc
,
837 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs
[] = {
838 { .irq
= 101 + OMAP44XX_IRQ_GIC_START
},
842 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs
[] = {
843 { .dma_req
= 75 + OMAP44XX_DMA_REQ_START
},
847 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks
[] = {
848 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
851 static struct omap_hwmod omap44xx_dss_hdmi_hwmod
= {
853 .class = &omap44xx_hdmi_hwmod_class
,
854 .clkdm_name
= "l3_dss_clkdm",
856 * HDMI audio requires to use no-idle mode. Hence,
857 * set idle mode by software.
859 .flags
= HWMOD_SWSUP_SIDLE
,
860 .mpu_irqs
= omap44xx_dss_hdmi_irqs
,
861 .sdma_reqs
= omap44xx_dss_hdmi_sdma_reqs
,
862 .main_clk
= "dss_48mhz_clk",
865 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
866 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
869 .opt_clks
= dss_hdmi_opt_clks
,
870 .opt_clks_cnt
= ARRAY_SIZE(dss_hdmi_opt_clks
),
875 * remote frame buffer interface
878 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc
= {
882 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
883 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
884 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
885 .sysc_fields
= &omap_hwmod_sysc_type1
,
888 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class
= {
890 .sysc
= &omap44xx_rfbi_sysc
,
894 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs
[] = {
895 { .dma_req
= 13 + OMAP44XX_DMA_REQ_START
},
899 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks
[] = {
900 { .role
= "ick", .clk
= "dss_fck" },
903 static struct omap_hwmod omap44xx_dss_rfbi_hwmod
= {
905 .class = &omap44xx_rfbi_hwmod_class
,
906 .clkdm_name
= "l3_dss_clkdm",
907 .sdma_reqs
= omap44xx_dss_rfbi_sdma_reqs
,
908 .main_clk
= "dss_dss_clk",
911 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
912 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
915 .opt_clks
= dss_rfbi_opt_clks
,
916 .opt_clks_cnt
= ARRAY_SIZE(dss_rfbi_opt_clks
),
924 static struct omap_hwmod_class omap44xx_venc_hwmod_class
= {
929 static struct omap_hwmod omap44xx_dss_venc_hwmod
= {
931 .class = &omap44xx_venc_hwmod_class
,
932 .clkdm_name
= "l3_dss_clkdm",
933 .main_clk
= "dss_tv_clk",
936 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
937 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
944 * bch error location module
947 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc
= {
951 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
952 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
953 SYSS_HAS_RESET_STATUS
),
954 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
955 .sysc_fields
= &omap_hwmod_sysc_type1
,
958 static struct omap_hwmod_class omap44xx_elm_hwmod_class
= {
960 .sysc
= &omap44xx_elm_sysc
,
964 static struct omap_hwmod_irq_info omap44xx_elm_irqs
[] = {
965 { .irq
= 4 + OMAP44XX_IRQ_GIC_START
},
969 static struct omap_hwmod omap44xx_elm_hwmod
= {
971 .class = &omap44xx_elm_hwmod_class
,
972 .clkdm_name
= "l4_per_clkdm",
973 .mpu_irqs
= omap44xx_elm_irqs
,
976 .clkctrl_offs
= OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET
,
977 .context_offs
= OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET
,
984 * external memory interface no1
987 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc
= {
991 static struct omap_hwmod_class omap44xx_emif_hwmod_class
= {
993 .sysc
= &omap44xx_emif_sysc
,
997 static struct omap_hwmod_irq_info omap44xx_emif1_irqs
[] = {
998 { .irq
= 110 + OMAP44XX_IRQ_GIC_START
},
1002 static struct omap_hwmod omap44xx_emif1_hwmod
= {
1004 .class = &omap44xx_emif_hwmod_class
,
1005 .clkdm_name
= "l3_emif_clkdm",
1006 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1007 .mpu_irqs
= omap44xx_emif1_irqs
,
1008 .main_clk
= "ddrphy_ck",
1011 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET
,
1012 .context_offs
= OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET
,
1013 .modulemode
= MODULEMODE_HWCTRL
,
1019 static struct omap_hwmod_irq_info omap44xx_emif2_irqs
[] = {
1020 { .irq
= 111 + OMAP44XX_IRQ_GIC_START
},
1024 static struct omap_hwmod omap44xx_emif2_hwmod
= {
1026 .class = &omap44xx_emif_hwmod_class
,
1027 .clkdm_name
= "l3_emif_clkdm",
1028 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1029 .mpu_irqs
= omap44xx_emif2_irqs
,
1030 .main_clk
= "ddrphy_ck",
1033 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET
,
1034 .context_offs
= OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET
,
1035 .modulemode
= MODULEMODE_HWCTRL
,
1042 * face detection hw accelerator module
1045 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc
= {
1047 .sysc_offs
= 0x0010,
1049 * FDIF needs 100 OCP clk cycles delay after a softreset before
1050 * accessing sysconfig again.
1051 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1052 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1054 * TODO: Indicate errata when available.
1057 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1058 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1059 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1060 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1061 .sysc_fields
= &omap_hwmod_sysc_type2
,
1064 static struct omap_hwmod_class omap44xx_fdif_hwmod_class
= {
1066 .sysc
= &omap44xx_fdif_sysc
,
1070 static struct omap_hwmod_irq_info omap44xx_fdif_irqs
[] = {
1071 { .irq
= 69 + OMAP44XX_IRQ_GIC_START
},
1075 static struct omap_hwmod omap44xx_fdif_hwmod
= {
1077 .class = &omap44xx_fdif_hwmod_class
,
1078 .clkdm_name
= "iss_clkdm",
1079 .mpu_irqs
= omap44xx_fdif_irqs
,
1080 .main_clk
= "fdif_fck",
1083 .clkctrl_offs
= OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET
,
1084 .context_offs
= OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET
,
1085 .modulemode
= MODULEMODE_SWCTRL
,
1092 * general purpose io module
1095 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc
= {
1097 .sysc_offs
= 0x0010,
1098 .syss_offs
= 0x0114,
1099 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
1100 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1101 SYSS_HAS_RESET_STATUS
),
1102 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1104 .sysc_fields
= &omap_hwmod_sysc_type1
,
1107 static struct omap_hwmod_class omap44xx_gpio_hwmod_class
= {
1109 .sysc
= &omap44xx_gpio_sysc
,
1114 static struct omap_gpio_dev_attr gpio_dev_attr
= {
1120 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs
[] = {
1121 { .irq
= 29 + OMAP44XX_IRQ_GIC_START
},
1125 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
1126 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
1129 static struct omap_hwmod omap44xx_gpio1_hwmod
= {
1131 .class = &omap44xx_gpio_hwmod_class
,
1132 .clkdm_name
= "l4_wkup_clkdm",
1133 .mpu_irqs
= omap44xx_gpio1_irqs
,
1134 .main_clk
= "gpio1_ick",
1137 .clkctrl_offs
= OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET
,
1138 .context_offs
= OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET
,
1139 .modulemode
= MODULEMODE_HWCTRL
,
1142 .opt_clks
= gpio1_opt_clks
,
1143 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
1144 .dev_attr
= &gpio_dev_attr
,
1148 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs
[] = {
1149 { .irq
= 30 + OMAP44XX_IRQ_GIC_START
},
1153 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
1154 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
1157 static struct omap_hwmod omap44xx_gpio2_hwmod
= {
1159 .class = &omap44xx_gpio_hwmod_class
,
1160 .clkdm_name
= "l4_per_clkdm",
1161 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1162 .mpu_irqs
= omap44xx_gpio2_irqs
,
1163 .main_clk
= "gpio2_ick",
1166 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET
,
1167 .context_offs
= OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET
,
1168 .modulemode
= MODULEMODE_HWCTRL
,
1171 .opt_clks
= gpio2_opt_clks
,
1172 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
1173 .dev_attr
= &gpio_dev_attr
,
1177 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs
[] = {
1178 { .irq
= 31 + OMAP44XX_IRQ_GIC_START
},
1182 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
1183 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
1186 static struct omap_hwmod omap44xx_gpio3_hwmod
= {
1188 .class = &omap44xx_gpio_hwmod_class
,
1189 .clkdm_name
= "l4_per_clkdm",
1190 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1191 .mpu_irqs
= omap44xx_gpio3_irqs
,
1192 .main_clk
= "gpio3_ick",
1195 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET
,
1196 .context_offs
= OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET
,
1197 .modulemode
= MODULEMODE_HWCTRL
,
1200 .opt_clks
= gpio3_opt_clks
,
1201 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
1202 .dev_attr
= &gpio_dev_attr
,
1206 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs
[] = {
1207 { .irq
= 32 + OMAP44XX_IRQ_GIC_START
},
1211 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
1212 { .role
= "dbclk", .clk
= "gpio4_dbclk" },
1215 static struct omap_hwmod omap44xx_gpio4_hwmod
= {
1217 .class = &omap44xx_gpio_hwmod_class
,
1218 .clkdm_name
= "l4_per_clkdm",
1219 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1220 .mpu_irqs
= omap44xx_gpio4_irqs
,
1221 .main_clk
= "gpio4_ick",
1224 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET
,
1225 .context_offs
= OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET
,
1226 .modulemode
= MODULEMODE_HWCTRL
,
1229 .opt_clks
= gpio4_opt_clks
,
1230 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
1231 .dev_attr
= &gpio_dev_attr
,
1235 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs
[] = {
1236 { .irq
= 33 + OMAP44XX_IRQ_GIC_START
},
1240 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
1241 { .role
= "dbclk", .clk
= "gpio5_dbclk" },
1244 static struct omap_hwmod omap44xx_gpio5_hwmod
= {
1246 .class = &omap44xx_gpio_hwmod_class
,
1247 .clkdm_name
= "l4_per_clkdm",
1248 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1249 .mpu_irqs
= omap44xx_gpio5_irqs
,
1250 .main_clk
= "gpio5_ick",
1253 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET
,
1254 .context_offs
= OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET
,
1255 .modulemode
= MODULEMODE_HWCTRL
,
1258 .opt_clks
= gpio5_opt_clks
,
1259 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
1260 .dev_attr
= &gpio_dev_attr
,
1264 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs
[] = {
1265 { .irq
= 34 + OMAP44XX_IRQ_GIC_START
},
1269 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
1270 { .role
= "dbclk", .clk
= "gpio6_dbclk" },
1273 static struct omap_hwmod omap44xx_gpio6_hwmod
= {
1275 .class = &omap44xx_gpio_hwmod_class
,
1276 .clkdm_name
= "l4_per_clkdm",
1277 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1278 .mpu_irqs
= omap44xx_gpio6_irqs
,
1279 .main_clk
= "gpio6_ick",
1282 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET
,
1283 .context_offs
= OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET
,
1284 .modulemode
= MODULEMODE_HWCTRL
,
1287 .opt_clks
= gpio6_opt_clks
,
1288 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
1289 .dev_attr
= &gpio_dev_attr
,
1294 * general purpose memory controller
1297 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc
= {
1299 .sysc_offs
= 0x0010,
1300 .syss_offs
= 0x0014,
1301 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
1302 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1303 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1304 .sysc_fields
= &omap_hwmod_sysc_type1
,
1307 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class
= {
1309 .sysc
= &omap44xx_gpmc_sysc
,
1313 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs
[] = {
1314 { .irq
= 20 + OMAP44XX_IRQ_GIC_START
},
1318 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs
[] = {
1319 { .dma_req
= 3 + OMAP44XX_DMA_REQ_START
},
1323 static struct omap_hwmod omap44xx_gpmc_hwmod
= {
1325 .class = &omap44xx_gpmc_hwmod_class
,
1326 .clkdm_name
= "l3_2_clkdm",
1327 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1328 .mpu_irqs
= omap44xx_gpmc_irqs
,
1329 .sdma_reqs
= omap44xx_gpmc_sdma_reqs
,
1332 .clkctrl_offs
= OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET
,
1333 .context_offs
= OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET
,
1334 .modulemode
= MODULEMODE_HWCTRL
,
1341 * 2d/3d graphics accelerator
1344 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc
= {
1345 .rev_offs
= 0x1fc00,
1346 .sysc_offs
= 0x1fc10,
1347 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
1348 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1349 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1350 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1351 .sysc_fields
= &omap_hwmod_sysc_type2
,
1354 static struct omap_hwmod_class omap44xx_gpu_hwmod_class
= {
1356 .sysc
= &omap44xx_gpu_sysc
,
1360 static struct omap_hwmod_irq_info omap44xx_gpu_irqs
[] = {
1361 { .irq
= 21 + OMAP44XX_IRQ_GIC_START
},
1365 static struct omap_hwmod omap44xx_gpu_hwmod
= {
1367 .class = &omap44xx_gpu_hwmod_class
,
1368 .clkdm_name
= "l3_gfx_clkdm",
1369 .mpu_irqs
= omap44xx_gpu_irqs
,
1370 .main_clk
= "gpu_fck",
1373 .clkctrl_offs
= OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET
,
1374 .context_offs
= OMAP4_RM_GFX_GFX_CONTEXT_OFFSET
,
1375 .modulemode
= MODULEMODE_SWCTRL
,
1382 * hdq / 1-wire serial interface controller
1385 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc
= {
1387 .sysc_offs
= 0x0014,
1388 .syss_offs
= 0x0018,
1389 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SOFTRESET
|
1390 SYSS_HAS_RESET_STATUS
),
1391 .sysc_fields
= &omap_hwmod_sysc_type1
,
1394 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class
= {
1396 .sysc
= &omap44xx_hdq1w_sysc
,
1400 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs
[] = {
1401 { .irq
= 58 + OMAP44XX_IRQ_GIC_START
},
1405 static struct omap_hwmod omap44xx_hdq1w_hwmod
= {
1407 .class = &omap44xx_hdq1w_hwmod_class
,
1408 .clkdm_name
= "l4_per_clkdm",
1409 .flags
= HWMOD_INIT_NO_RESET
, /* XXX temporary */
1410 .mpu_irqs
= omap44xx_hdq1w_irqs
,
1411 .main_clk
= "hdq1w_fck",
1414 .clkctrl_offs
= OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET
,
1415 .context_offs
= OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET
,
1416 .modulemode
= MODULEMODE_SWCTRL
,
1423 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1427 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc
= {
1429 .sysc_offs
= 0x0010,
1430 .syss_offs
= 0x0014,
1431 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_EMUFREE
|
1432 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
1433 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1434 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1435 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1436 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1437 .sysc_fields
= &omap_hwmod_sysc_type1
,
1440 static struct omap_hwmod_class omap44xx_hsi_hwmod_class
= {
1442 .sysc
= &omap44xx_hsi_sysc
,
1446 static struct omap_hwmod_irq_info omap44xx_hsi_irqs
[] = {
1447 { .name
= "mpu_p1", .irq
= 67 + OMAP44XX_IRQ_GIC_START
},
1448 { .name
= "mpu_p2", .irq
= 68 + OMAP44XX_IRQ_GIC_START
},
1449 { .name
= "mpu_dma", .irq
= 71 + OMAP44XX_IRQ_GIC_START
},
1453 static struct omap_hwmod omap44xx_hsi_hwmod
= {
1455 .class = &omap44xx_hsi_hwmod_class
,
1456 .clkdm_name
= "l3_init_clkdm",
1457 .mpu_irqs
= omap44xx_hsi_irqs
,
1458 .main_clk
= "hsi_fck",
1461 .clkctrl_offs
= OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET
,
1462 .context_offs
= OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET
,
1463 .modulemode
= MODULEMODE_HWCTRL
,
1470 * multimaster high-speed i2c controller
1473 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc
= {
1474 .sysc_offs
= 0x0010,
1475 .syss_offs
= 0x0090,
1476 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1477 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
1478 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1479 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1481 .clockact
= CLOCKACT_TEST_ICLK
,
1482 .sysc_fields
= &omap_hwmod_sysc_type1
,
1485 static struct omap_hwmod_class omap44xx_i2c_hwmod_class
= {
1487 .sysc
= &omap44xx_i2c_sysc
,
1488 .rev
= OMAP_I2C_IP_VERSION_2
,
1489 .reset
= &omap_i2c_reset
,
1492 static struct omap_i2c_dev_attr i2c_dev_attr
= {
1493 .flags
= OMAP_I2C_FLAG_BUS_SHIFT_NONE
|
1494 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE
,
1498 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs
[] = {
1499 { .irq
= 56 + OMAP44XX_IRQ_GIC_START
},
1503 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs
[] = {
1504 { .name
= "tx", .dma_req
= 26 + OMAP44XX_DMA_REQ_START
},
1505 { .name
= "rx", .dma_req
= 27 + OMAP44XX_DMA_REQ_START
},
1509 static struct omap_hwmod omap44xx_i2c1_hwmod
= {
1511 .class = &omap44xx_i2c_hwmod_class
,
1512 .clkdm_name
= "l4_per_clkdm",
1513 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1514 .mpu_irqs
= omap44xx_i2c1_irqs
,
1515 .sdma_reqs
= omap44xx_i2c1_sdma_reqs
,
1516 .main_clk
= "i2c1_fck",
1519 .clkctrl_offs
= OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET
,
1520 .context_offs
= OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET
,
1521 .modulemode
= MODULEMODE_SWCTRL
,
1524 .dev_attr
= &i2c_dev_attr
,
1528 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs
[] = {
1529 { .irq
= 57 + OMAP44XX_IRQ_GIC_START
},
1533 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs
[] = {
1534 { .name
= "tx", .dma_req
= 28 + OMAP44XX_DMA_REQ_START
},
1535 { .name
= "rx", .dma_req
= 29 + OMAP44XX_DMA_REQ_START
},
1539 static struct omap_hwmod omap44xx_i2c2_hwmod
= {
1541 .class = &omap44xx_i2c_hwmod_class
,
1542 .clkdm_name
= "l4_per_clkdm",
1543 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1544 .mpu_irqs
= omap44xx_i2c2_irqs
,
1545 .sdma_reqs
= omap44xx_i2c2_sdma_reqs
,
1546 .main_clk
= "i2c2_fck",
1549 .clkctrl_offs
= OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET
,
1550 .context_offs
= OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET
,
1551 .modulemode
= MODULEMODE_SWCTRL
,
1554 .dev_attr
= &i2c_dev_attr
,
1558 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs
[] = {
1559 { .irq
= 61 + OMAP44XX_IRQ_GIC_START
},
1563 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs
[] = {
1564 { .name
= "tx", .dma_req
= 24 + OMAP44XX_DMA_REQ_START
},
1565 { .name
= "rx", .dma_req
= 25 + OMAP44XX_DMA_REQ_START
},
1569 static struct omap_hwmod omap44xx_i2c3_hwmod
= {
1571 .class = &omap44xx_i2c_hwmod_class
,
1572 .clkdm_name
= "l4_per_clkdm",
1573 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1574 .mpu_irqs
= omap44xx_i2c3_irqs
,
1575 .sdma_reqs
= omap44xx_i2c3_sdma_reqs
,
1576 .main_clk
= "i2c3_fck",
1579 .clkctrl_offs
= OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET
,
1580 .context_offs
= OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET
,
1581 .modulemode
= MODULEMODE_SWCTRL
,
1584 .dev_attr
= &i2c_dev_attr
,
1588 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs
[] = {
1589 { .irq
= 62 + OMAP44XX_IRQ_GIC_START
},
1593 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs
[] = {
1594 { .name
= "tx", .dma_req
= 123 + OMAP44XX_DMA_REQ_START
},
1595 { .name
= "rx", .dma_req
= 124 + OMAP44XX_DMA_REQ_START
},
1599 static struct omap_hwmod omap44xx_i2c4_hwmod
= {
1601 .class = &omap44xx_i2c_hwmod_class
,
1602 .clkdm_name
= "l4_per_clkdm",
1603 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1604 .mpu_irqs
= omap44xx_i2c4_irqs
,
1605 .sdma_reqs
= omap44xx_i2c4_sdma_reqs
,
1606 .main_clk
= "i2c4_fck",
1609 .clkctrl_offs
= OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET
,
1610 .context_offs
= OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET
,
1611 .modulemode
= MODULEMODE_SWCTRL
,
1614 .dev_attr
= &i2c_dev_attr
,
1619 * imaging processor unit
1622 static struct omap_hwmod_class omap44xx_ipu_hwmod_class
= {
1627 static struct omap_hwmod_irq_info omap44xx_ipu_irqs
[] = {
1628 { .irq
= 100 + OMAP44XX_IRQ_GIC_START
},
1632 static struct omap_hwmod_rst_info omap44xx_ipu_resets
[] = {
1633 { .name
= "cpu0", .rst_shift
= 0 },
1634 { .name
= "cpu1", .rst_shift
= 1 },
1635 { .name
= "mmu_cache", .rst_shift
= 2 },
1638 static struct omap_hwmod omap44xx_ipu_hwmod
= {
1640 .class = &omap44xx_ipu_hwmod_class
,
1641 .clkdm_name
= "ducati_clkdm",
1642 .mpu_irqs
= omap44xx_ipu_irqs
,
1643 .rst_lines
= omap44xx_ipu_resets
,
1644 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_ipu_resets
),
1645 .main_clk
= "ipu_fck",
1648 .clkctrl_offs
= OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET
,
1649 .rstctrl_offs
= OMAP4_RM_DUCATI_RSTCTRL_OFFSET
,
1650 .context_offs
= OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET
,
1651 .modulemode
= MODULEMODE_HWCTRL
,
1658 * external images sensor pixel data processor
1661 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc
= {
1663 .sysc_offs
= 0x0010,
1665 * ISS needs 100 OCP clk cycles delay after a softreset before
1666 * accessing sysconfig again.
1667 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1668 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1670 * TODO: Indicate errata when available.
1673 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1674 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1675 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1676 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1677 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1678 .sysc_fields
= &omap_hwmod_sysc_type2
,
1681 static struct omap_hwmod_class omap44xx_iss_hwmod_class
= {
1683 .sysc
= &omap44xx_iss_sysc
,
1687 static struct omap_hwmod_irq_info omap44xx_iss_irqs
[] = {
1688 { .irq
= 24 + OMAP44XX_IRQ_GIC_START
},
1692 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs
[] = {
1693 { .name
= "1", .dma_req
= 8 + OMAP44XX_DMA_REQ_START
},
1694 { .name
= "2", .dma_req
= 9 + OMAP44XX_DMA_REQ_START
},
1695 { .name
= "3", .dma_req
= 11 + OMAP44XX_DMA_REQ_START
},
1696 { .name
= "4", .dma_req
= 12 + OMAP44XX_DMA_REQ_START
},
1700 static struct omap_hwmod_opt_clk iss_opt_clks
[] = {
1701 { .role
= "ctrlclk", .clk
= "iss_ctrlclk" },
1704 static struct omap_hwmod omap44xx_iss_hwmod
= {
1706 .class = &omap44xx_iss_hwmod_class
,
1707 .clkdm_name
= "iss_clkdm",
1708 .mpu_irqs
= omap44xx_iss_irqs
,
1709 .sdma_reqs
= omap44xx_iss_sdma_reqs
,
1710 .main_clk
= "iss_fck",
1713 .clkctrl_offs
= OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET
,
1714 .context_offs
= OMAP4_RM_CAM_ISS_CONTEXT_OFFSET
,
1715 .modulemode
= MODULEMODE_SWCTRL
,
1718 .opt_clks
= iss_opt_clks
,
1719 .opt_clks_cnt
= ARRAY_SIZE(iss_opt_clks
),
1724 * multi-standard video encoder/decoder hardware accelerator
1727 static struct omap_hwmod_class omap44xx_iva_hwmod_class
= {
1732 static struct omap_hwmod_irq_info omap44xx_iva_irqs
[] = {
1733 { .name
= "sync_1", .irq
= 103 + OMAP44XX_IRQ_GIC_START
},
1734 { .name
= "sync_0", .irq
= 104 + OMAP44XX_IRQ_GIC_START
},
1735 { .name
= "mailbox_0", .irq
= 107 + OMAP44XX_IRQ_GIC_START
},
1739 static struct omap_hwmod_rst_info omap44xx_iva_resets
[] = {
1740 { .name
= "seq0", .rst_shift
= 0 },
1741 { .name
= "seq1", .rst_shift
= 1 },
1742 { .name
= "logic", .rst_shift
= 2 },
1745 static struct omap_hwmod omap44xx_iva_hwmod
= {
1747 .class = &omap44xx_iva_hwmod_class
,
1748 .clkdm_name
= "ivahd_clkdm",
1749 .mpu_irqs
= omap44xx_iva_irqs
,
1750 .rst_lines
= omap44xx_iva_resets
,
1751 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_iva_resets
),
1752 .main_clk
= "iva_fck",
1755 .clkctrl_offs
= OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET
,
1756 .rstctrl_offs
= OMAP4_RM_IVAHD_RSTCTRL_OFFSET
,
1757 .context_offs
= OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET
,
1758 .modulemode
= MODULEMODE_HWCTRL
,
1765 * keyboard controller
1768 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc
= {
1770 .sysc_offs
= 0x0010,
1771 .syss_offs
= 0x0014,
1772 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1773 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
1774 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1775 SYSS_HAS_RESET_STATUS
),
1776 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1777 .sysc_fields
= &omap_hwmod_sysc_type1
,
1780 static struct omap_hwmod_class omap44xx_kbd_hwmod_class
= {
1782 .sysc
= &omap44xx_kbd_sysc
,
1786 static struct omap_hwmod_irq_info omap44xx_kbd_irqs
[] = {
1787 { .irq
= 120 + OMAP44XX_IRQ_GIC_START
},
1791 static struct omap_hwmod omap44xx_kbd_hwmod
= {
1793 .class = &omap44xx_kbd_hwmod_class
,
1794 .clkdm_name
= "l4_wkup_clkdm",
1795 .mpu_irqs
= omap44xx_kbd_irqs
,
1796 .main_clk
= "kbd_fck",
1799 .clkctrl_offs
= OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET
,
1800 .context_offs
= OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET
,
1801 .modulemode
= MODULEMODE_SWCTRL
,
1808 * mailbox module allowing communication between the on-chip processors using a
1809 * queued mailbox-interrupt mechanism.
1812 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc
= {
1814 .sysc_offs
= 0x0010,
1815 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1816 SYSC_HAS_SOFTRESET
),
1817 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1818 .sysc_fields
= &omap_hwmod_sysc_type2
,
1821 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class
= {
1823 .sysc
= &omap44xx_mailbox_sysc
,
1827 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs
[] = {
1828 { .irq
= 26 + OMAP44XX_IRQ_GIC_START
},
1832 static struct omap_hwmod omap44xx_mailbox_hwmod
= {
1834 .class = &omap44xx_mailbox_hwmod_class
,
1835 .clkdm_name
= "l4_cfg_clkdm",
1836 .mpu_irqs
= omap44xx_mailbox_irqs
,
1839 .clkctrl_offs
= OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET
,
1840 .context_offs
= OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET
,
1847 * multi-channel audio serial port controller
1850 /* The IP is not compliant to type1 / type2 scheme */
1851 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp
= {
1855 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc
= {
1856 .sysc_offs
= 0x0004,
1857 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1858 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1860 .sysc_fields
= &omap_hwmod_sysc_type_mcasp
,
1863 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class
= {
1865 .sysc
= &omap44xx_mcasp_sysc
,
1869 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs
[] = {
1870 { .name
= "arevt", .irq
= 108 + OMAP44XX_IRQ_GIC_START
},
1871 { .name
= "axevt", .irq
= 109 + OMAP44XX_IRQ_GIC_START
},
1875 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs
[] = {
1876 { .name
= "axevt", .dma_req
= 7 + OMAP44XX_DMA_REQ_START
},
1877 { .name
= "arevt", .dma_req
= 10 + OMAP44XX_DMA_REQ_START
},
1881 static struct omap_hwmod omap44xx_mcasp_hwmod
= {
1883 .class = &omap44xx_mcasp_hwmod_class
,
1884 .clkdm_name
= "abe_clkdm",
1885 .mpu_irqs
= omap44xx_mcasp_irqs
,
1886 .sdma_reqs
= omap44xx_mcasp_sdma_reqs
,
1887 .main_clk
= "mcasp_fck",
1890 .clkctrl_offs
= OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET
,
1891 .context_offs
= OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET
,
1892 .modulemode
= MODULEMODE_SWCTRL
,
1899 * multi channel buffered serial port controller
1902 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc
= {
1903 .sysc_offs
= 0x008c,
1904 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_ENAWAKEUP
|
1905 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1906 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1907 .sysc_fields
= &omap_hwmod_sysc_type1
,
1910 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class
= {
1912 .sysc
= &omap44xx_mcbsp_sysc
,
1913 .rev
= MCBSP_CONFIG_TYPE4
,
1917 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs
[] = {
1918 { .name
= "common", .irq
= 17 + OMAP44XX_IRQ_GIC_START
},
1922 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs
[] = {
1923 { .name
= "tx", .dma_req
= 32 + OMAP44XX_DMA_REQ_START
},
1924 { .name
= "rx", .dma_req
= 33 + OMAP44XX_DMA_REQ_START
},
1928 static struct omap_hwmod_opt_clk mcbsp1_opt_clks
[] = {
1929 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1930 { .role
= "prcm_clk", .clk
= "mcbsp1_sync_mux_ck" },
1933 static struct omap_hwmod omap44xx_mcbsp1_hwmod
= {
1935 .class = &omap44xx_mcbsp_hwmod_class
,
1936 .clkdm_name
= "abe_clkdm",
1937 .mpu_irqs
= omap44xx_mcbsp1_irqs
,
1938 .sdma_reqs
= omap44xx_mcbsp1_sdma_reqs
,
1939 .main_clk
= "mcbsp1_fck",
1942 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET
,
1943 .context_offs
= OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET
,
1944 .modulemode
= MODULEMODE_SWCTRL
,
1947 .opt_clks
= mcbsp1_opt_clks
,
1948 .opt_clks_cnt
= ARRAY_SIZE(mcbsp1_opt_clks
),
1952 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs
[] = {
1953 { .name
= "common", .irq
= 22 + OMAP44XX_IRQ_GIC_START
},
1957 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs
[] = {
1958 { .name
= "tx", .dma_req
= 16 + OMAP44XX_DMA_REQ_START
},
1959 { .name
= "rx", .dma_req
= 17 + OMAP44XX_DMA_REQ_START
},
1963 static struct omap_hwmod_opt_clk mcbsp2_opt_clks
[] = {
1964 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1965 { .role
= "prcm_clk", .clk
= "mcbsp2_sync_mux_ck" },
1968 static struct omap_hwmod omap44xx_mcbsp2_hwmod
= {
1970 .class = &omap44xx_mcbsp_hwmod_class
,
1971 .clkdm_name
= "abe_clkdm",
1972 .mpu_irqs
= omap44xx_mcbsp2_irqs
,
1973 .sdma_reqs
= omap44xx_mcbsp2_sdma_reqs
,
1974 .main_clk
= "mcbsp2_fck",
1977 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET
,
1978 .context_offs
= OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET
,
1979 .modulemode
= MODULEMODE_SWCTRL
,
1982 .opt_clks
= mcbsp2_opt_clks
,
1983 .opt_clks_cnt
= ARRAY_SIZE(mcbsp2_opt_clks
),
1987 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs
[] = {
1988 { .name
= "common", .irq
= 23 + OMAP44XX_IRQ_GIC_START
},
1992 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs
[] = {
1993 { .name
= "tx", .dma_req
= 18 + OMAP44XX_DMA_REQ_START
},
1994 { .name
= "rx", .dma_req
= 19 + OMAP44XX_DMA_REQ_START
},
1998 static struct omap_hwmod_opt_clk mcbsp3_opt_clks
[] = {
1999 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
2000 { .role
= "prcm_clk", .clk
= "mcbsp3_sync_mux_ck" },
2003 static struct omap_hwmod omap44xx_mcbsp3_hwmod
= {
2005 .class = &omap44xx_mcbsp_hwmod_class
,
2006 .clkdm_name
= "abe_clkdm",
2007 .mpu_irqs
= omap44xx_mcbsp3_irqs
,
2008 .sdma_reqs
= omap44xx_mcbsp3_sdma_reqs
,
2009 .main_clk
= "mcbsp3_fck",
2012 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET
,
2013 .context_offs
= OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET
,
2014 .modulemode
= MODULEMODE_SWCTRL
,
2017 .opt_clks
= mcbsp3_opt_clks
,
2018 .opt_clks_cnt
= ARRAY_SIZE(mcbsp3_opt_clks
),
2022 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs
[] = {
2023 { .name
= "common", .irq
= 16 + OMAP44XX_IRQ_GIC_START
},
2027 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs
[] = {
2028 { .name
= "tx", .dma_req
= 30 + OMAP44XX_DMA_REQ_START
},
2029 { .name
= "rx", .dma_req
= 31 + OMAP44XX_DMA_REQ_START
},
2033 static struct omap_hwmod_opt_clk mcbsp4_opt_clks
[] = {
2034 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
2035 { .role
= "prcm_clk", .clk
= "mcbsp4_sync_mux_ck" },
2038 static struct omap_hwmod omap44xx_mcbsp4_hwmod
= {
2040 .class = &omap44xx_mcbsp_hwmod_class
,
2041 .clkdm_name
= "l4_per_clkdm",
2042 .mpu_irqs
= omap44xx_mcbsp4_irqs
,
2043 .sdma_reqs
= omap44xx_mcbsp4_sdma_reqs
,
2044 .main_clk
= "mcbsp4_fck",
2047 .clkctrl_offs
= OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET
,
2048 .context_offs
= OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET
,
2049 .modulemode
= MODULEMODE_SWCTRL
,
2052 .opt_clks
= mcbsp4_opt_clks
,
2053 .opt_clks_cnt
= ARRAY_SIZE(mcbsp4_opt_clks
),
2058 * multi channel pdm controller (proprietary interface with phoenix power
2062 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc
= {
2064 .sysc_offs
= 0x0010,
2065 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2066 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2067 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2069 .sysc_fields
= &omap_hwmod_sysc_type2
,
2072 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class
= {
2074 .sysc
= &omap44xx_mcpdm_sysc
,
2078 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs
[] = {
2079 { .irq
= 112 + OMAP44XX_IRQ_GIC_START
},
2083 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs
[] = {
2084 { .name
= "up_link", .dma_req
= 64 + OMAP44XX_DMA_REQ_START
},
2085 { .name
= "dn_link", .dma_req
= 65 + OMAP44XX_DMA_REQ_START
},
2089 static struct omap_hwmod omap44xx_mcpdm_hwmod
= {
2091 .class = &omap44xx_mcpdm_hwmod_class
,
2092 .clkdm_name
= "abe_clkdm",
2093 .mpu_irqs
= omap44xx_mcpdm_irqs
,
2094 .sdma_reqs
= omap44xx_mcpdm_sdma_reqs
,
2095 .main_clk
= "mcpdm_fck",
2098 .clkctrl_offs
= OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET
,
2099 .context_offs
= OMAP4_RM_ABE_PDM_CONTEXT_OFFSET
,
2100 .modulemode
= MODULEMODE_SWCTRL
,
2107 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2111 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc
= {
2113 .sysc_offs
= 0x0010,
2114 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2115 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2116 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2118 .sysc_fields
= &omap_hwmod_sysc_type2
,
2121 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class
= {
2123 .sysc
= &omap44xx_mcspi_sysc
,
2124 .rev
= OMAP4_MCSPI_REV
,
2128 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs
[] = {
2129 { .irq
= 65 + OMAP44XX_IRQ_GIC_START
},
2133 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs
[] = {
2134 { .name
= "tx0", .dma_req
= 34 + OMAP44XX_DMA_REQ_START
},
2135 { .name
= "rx0", .dma_req
= 35 + OMAP44XX_DMA_REQ_START
},
2136 { .name
= "tx1", .dma_req
= 36 + OMAP44XX_DMA_REQ_START
},
2137 { .name
= "rx1", .dma_req
= 37 + OMAP44XX_DMA_REQ_START
},
2138 { .name
= "tx2", .dma_req
= 38 + OMAP44XX_DMA_REQ_START
},
2139 { .name
= "rx2", .dma_req
= 39 + OMAP44XX_DMA_REQ_START
},
2140 { .name
= "tx3", .dma_req
= 40 + OMAP44XX_DMA_REQ_START
},
2141 { .name
= "rx3", .dma_req
= 41 + OMAP44XX_DMA_REQ_START
},
2145 /* mcspi1 dev_attr */
2146 static struct omap2_mcspi_dev_attr mcspi1_dev_attr
= {
2147 .num_chipselect
= 4,
2150 static struct omap_hwmod omap44xx_mcspi1_hwmod
= {
2152 .class = &omap44xx_mcspi_hwmod_class
,
2153 .clkdm_name
= "l4_per_clkdm",
2154 .mpu_irqs
= omap44xx_mcspi1_irqs
,
2155 .sdma_reqs
= omap44xx_mcspi1_sdma_reqs
,
2156 .main_clk
= "mcspi1_fck",
2159 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
,
2160 .context_offs
= OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET
,
2161 .modulemode
= MODULEMODE_SWCTRL
,
2164 .dev_attr
= &mcspi1_dev_attr
,
2168 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs
[] = {
2169 { .irq
= 66 + OMAP44XX_IRQ_GIC_START
},
2173 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs
[] = {
2174 { .name
= "tx0", .dma_req
= 42 + OMAP44XX_DMA_REQ_START
},
2175 { .name
= "rx0", .dma_req
= 43 + OMAP44XX_DMA_REQ_START
},
2176 { .name
= "tx1", .dma_req
= 44 + OMAP44XX_DMA_REQ_START
},
2177 { .name
= "rx1", .dma_req
= 45 + OMAP44XX_DMA_REQ_START
},
2181 /* mcspi2 dev_attr */
2182 static struct omap2_mcspi_dev_attr mcspi2_dev_attr
= {
2183 .num_chipselect
= 2,
2186 static struct omap_hwmod omap44xx_mcspi2_hwmod
= {
2188 .class = &omap44xx_mcspi_hwmod_class
,
2189 .clkdm_name
= "l4_per_clkdm",
2190 .mpu_irqs
= omap44xx_mcspi2_irqs
,
2191 .sdma_reqs
= omap44xx_mcspi2_sdma_reqs
,
2192 .main_clk
= "mcspi2_fck",
2195 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
,
2196 .context_offs
= OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET
,
2197 .modulemode
= MODULEMODE_SWCTRL
,
2200 .dev_attr
= &mcspi2_dev_attr
,
2204 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs
[] = {
2205 { .irq
= 91 + OMAP44XX_IRQ_GIC_START
},
2209 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs
[] = {
2210 { .name
= "tx0", .dma_req
= 14 + OMAP44XX_DMA_REQ_START
},
2211 { .name
= "rx0", .dma_req
= 15 + OMAP44XX_DMA_REQ_START
},
2212 { .name
= "tx1", .dma_req
= 22 + OMAP44XX_DMA_REQ_START
},
2213 { .name
= "rx1", .dma_req
= 23 + OMAP44XX_DMA_REQ_START
},
2217 /* mcspi3 dev_attr */
2218 static struct omap2_mcspi_dev_attr mcspi3_dev_attr
= {
2219 .num_chipselect
= 2,
2222 static struct omap_hwmod omap44xx_mcspi3_hwmod
= {
2224 .class = &omap44xx_mcspi_hwmod_class
,
2225 .clkdm_name
= "l4_per_clkdm",
2226 .mpu_irqs
= omap44xx_mcspi3_irqs
,
2227 .sdma_reqs
= omap44xx_mcspi3_sdma_reqs
,
2228 .main_clk
= "mcspi3_fck",
2231 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
,
2232 .context_offs
= OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET
,
2233 .modulemode
= MODULEMODE_SWCTRL
,
2236 .dev_attr
= &mcspi3_dev_attr
,
2240 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs
[] = {
2241 { .irq
= 48 + OMAP44XX_IRQ_GIC_START
},
2245 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs
[] = {
2246 { .name
= "tx0", .dma_req
= 69 + OMAP44XX_DMA_REQ_START
},
2247 { .name
= "rx0", .dma_req
= 70 + OMAP44XX_DMA_REQ_START
},
2251 /* mcspi4 dev_attr */
2252 static struct omap2_mcspi_dev_attr mcspi4_dev_attr
= {
2253 .num_chipselect
= 1,
2256 static struct omap_hwmod omap44xx_mcspi4_hwmod
= {
2258 .class = &omap44xx_mcspi_hwmod_class
,
2259 .clkdm_name
= "l4_per_clkdm",
2260 .mpu_irqs
= omap44xx_mcspi4_irqs
,
2261 .sdma_reqs
= omap44xx_mcspi4_sdma_reqs
,
2262 .main_clk
= "mcspi4_fck",
2265 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
,
2266 .context_offs
= OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET
,
2267 .modulemode
= MODULEMODE_SWCTRL
,
2270 .dev_attr
= &mcspi4_dev_attr
,
2275 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2278 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc
= {
2280 .sysc_offs
= 0x0010,
2281 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
2282 SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
2283 SYSC_HAS_SOFTRESET
),
2284 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2285 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
2286 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
2287 .sysc_fields
= &omap_hwmod_sysc_type2
,
2290 static struct omap_hwmod_class omap44xx_mmc_hwmod_class
= {
2292 .sysc
= &omap44xx_mmc_sysc
,
2296 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs
[] = {
2297 { .irq
= 83 + OMAP44XX_IRQ_GIC_START
},
2301 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs
[] = {
2302 { .name
= "tx", .dma_req
= 60 + OMAP44XX_DMA_REQ_START
},
2303 { .name
= "rx", .dma_req
= 61 + OMAP44XX_DMA_REQ_START
},
2308 static struct omap_mmc_dev_attr mmc1_dev_attr
= {
2309 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
2312 static struct omap_hwmod omap44xx_mmc1_hwmod
= {
2314 .class = &omap44xx_mmc_hwmod_class
,
2315 .clkdm_name
= "l3_init_clkdm",
2316 .mpu_irqs
= omap44xx_mmc1_irqs
,
2317 .sdma_reqs
= omap44xx_mmc1_sdma_reqs
,
2318 .main_clk
= "mmc1_fck",
2321 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET
,
2322 .context_offs
= OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET
,
2323 .modulemode
= MODULEMODE_SWCTRL
,
2326 .dev_attr
= &mmc1_dev_attr
,
2330 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs
[] = {
2331 { .irq
= 86 + OMAP44XX_IRQ_GIC_START
},
2335 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs
[] = {
2336 { .name
= "tx", .dma_req
= 46 + OMAP44XX_DMA_REQ_START
},
2337 { .name
= "rx", .dma_req
= 47 + OMAP44XX_DMA_REQ_START
},
2341 static struct omap_hwmod omap44xx_mmc2_hwmod
= {
2343 .class = &omap44xx_mmc_hwmod_class
,
2344 .clkdm_name
= "l3_init_clkdm",
2345 .mpu_irqs
= omap44xx_mmc2_irqs
,
2346 .sdma_reqs
= omap44xx_mmc2_sdma_reqs
,
2347 .main_clk
= "mmc2_fck",
2350 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET
,
2351 .context_offs
= OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET
,
2352 .modulemode
= MODULEMODE_SWCTRL
,
2358 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs
[] = {
2359 { .irq
= 94 + OMAP44XX_IRQ_GIC_START
},
2363 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs
[] = {
2364 { .name
= "tx", .dma_req
= 76 + OMAP44XX_DMA_REQ_START
},
2365 { .name
= "rx", .dma_req
= 77 + OMAP44XX_DMA_REQ_START
},
2369 static struct omap_hwmod omap44xx_mmc3_hwmod
= {
2371 .class = &omap44xx_mmc_hwmod_class
,
2372 .clkdm_name
= "l4_per_clkdm",
2373 .mpu_irqs
= omap44xx_mmc3_irqs
,
2374 .sdma_reqs
= omap44xx_mmc3_sdma_reqs
,
2375 .main_clk
= "mmc3_fck",
2378 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET
,
2379 .context_offs
= OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET
,
2380 .modulemode
= MODULEMODE_SWCTRL
,
2386 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs
[] = {
2387 { .irq
= 96 + OMAP44XX_IRQ_GIC_START
},
2391 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs
[] = {
2392 { .name
= "tx", .dma_req
= 56 + OMAP44XX_DMA_REQ_START
},
2393 { .name
= "rx", .dma_req
= 57 + OMAP44XX_DMA_REQ_START
},
2397 static struct omap_hwmod omap44xx_mmc4_hwmod
= {
2399 .class = &omap44xx_mmc_hwmod_class
,
2400 .clkdm_name
= "l4_per_clkdm",
2401 .mpu_irqs
= omap44xx_mmc4_irqs
,
2402 .sdma_reqs
= omap44xx_mmc4_sdma_reqs
,
2403 .main_clk
= "mmc4_fck",
2406 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET
,
2407 .context_offs
= OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET
,
2408 .modulemode
= MODULEMODE_SWCTRL
,
2414 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs
[] = {
2415 { .irq
= 59 + OMAP44XX_IRQ_GIC_START
},
2419 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs
[] = {
2420 { .name
= "tx", .dma_req
= 58 + OMAP44XX_DMA_REQ_START
},
2421 { .name
= "rx", .dma_req
= 59 + OMAP44XX_DMA_REQ_START
},
2425 static struct omap_hwmod omap44xx_mmc5_hwmod
= {
2427 .class = &omap44xx_mmc_hwmod_class
,
2428 .clkdm_name
= "l4_per_clkdm",
2429 .mpu_irqs
= omap44xx_mmc5_irqs
,
2430 .sdma_reqs
= omap44xx_mmc5_sdma_reqs
,
2431 .main_clk
= "mmc5_fck",
2434 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET
,
2435 .context_offs
= OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET
,
2436 .modulemode
= MODULEMODE_SWCTRL
,
2446 static struct omap_hwmod_class omap44xx_mpu_hwmod_class
= {
2451 static struct omap_hwmod_irq_info omap44xx_mpu_irqs
[] = {
2452 { .name
= "pl310", .irq
= 0 + OMAP44XX_IRQ_GIC_START
},
2453 { .name
= "cti0", .irq
= 1 + OMAP44XX_IRQ_GIC_START
},
2454 { .name
= "cti1", .irq
= 2 + OMAP44XX_IRQ_GIC_START
},
2458 static struct omap_hwmod omap44xx_mpu_hwmod
= {
2460 .class = &omap44xx_mpu_hwmod_class
,
2461 .clkdm_name
= "mpuss_clkdm",
2462 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
2463 .mpu_irqs
= omap44xx_mpu_irqs
,
2464 .main_clk
= "dpll_mpu_m2_ck",
2467 .clkctrl_offs
= OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET
,
2468 .context_offs
= OMAP4_RM_MPU_MPU_CONTEXT_OFFSET
,
2475 * top-level core on-chip ram
2478 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class
= {
2483 static struct omap_hwmod omap44xx_ocmc_ram_hwmod
= {
2485 .class = &omap44xx_ocmc_ram_hwmod_class
,
2486 .clkdm_name
= "l3_2_clkdm",
2489 .clkctrl_offs
= OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET
,
2490 .context_offs
= OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET
,
2497 * bridge to transform ocp interface protocol to scp (serial control port)
2501 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class
= {
2505 /* ocp2scp_usb_phy */
2506 static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks
[] = {
2507 { .role
= "phy_48m", .clk
= "ocp2scp_usb_phy_phy_48m" },
2510 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod
= {
2511 .name
= "ocp2scp_usb_phy",
2512 .class = &omap44xx_ocp2scp_hwmod_class
,
2513 .clkdm_name
= "l3_init_clkdm",
2516 .clkctrl_offs
= OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET
,
2517 .context_offs
= OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET
,
2518 .modulemode
= MODULEMODE_HWCTRL
,
2521 .opt_clks
= ocp2scp_usb_phy_opt_clks
,
2522 .opt_clks_cnt
= ARRAY_SIZE(ocp2scp_usb_phy_opt_clks
),
2527 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2528 * + clock manager 1 (in always on power domain) + local prm in mpu
2531 static struct omap_hwmod_class omap44xx_prcm_hwmod_class
= {
2536 static struct omap_hwmod omap44xx_prcm_mpu_hwmod
= {
2538 .class = &omap44xx_prcm_hwmod_class
,
2539 .clkdm_name
= "l4_wkup_clkdm",
2543 static struct omap_hwmod omap44xx_cm_core_aon_hwmod
= {
2544 .name
= "cm_core_aon",
2545 .class = &omap44xx_prcm_hwmod_class
,
2546 .clkdm_name
= "cm_clkdm",
2550 static struct omap_hwmod omap44xx_cm_core_hwmod
= {
2552 .class = &omap44xx_prcm_hwmod_class
,
2553 .clkdm_name
= "cm_clkdm",
2557 static struct omap_hwmod_irq_info omap44xx_prm_irqs
[] = {
2558 { .irq
= 11 + OMAP44XX_IRQ_GIC_START
},
2562 static struct omap_hwmod_rst_info omap44xx_prm_resets
[] = {
2563 { .name
= "rst_global_warm_sw", .rst_shift
= 0 },
2564 { .name
= "rst_global_cold_sw", .rst_shift
= 1 },
2567 static struct omap_hwmod omap44xx_prm_hwmod
= {
2569 .class = &omap44xx_prcm_hwmod_class
,
2570 .clkdm_name
= "prm_clkdm",
2571 .mpu_irqs
= omap44xx_prm_irqs
,
2572 .rst_lines
= omap44xx_prm_resets
,
2573 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_prm_resets
),
2578 * system clock and reset manager
2581 static struct omap_hwmod_class omap44xx_scrm_hwmod_class
= {
2586 static struct omap_hwmod omap44xx_scrm_hwmod
= {
2588 .class = &omap44xx_scrm_hwmod_class
,
2589 .clkdm_name
= "l4_wkup_clkdm",
2594 * shared level 2 memory interface
2597 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class
= {
2602 static struct omap_hwmod omap44xx_sl2if_hwmod
= {
2604 .class = &omap44xx_sl2if_hwmod_class
,
2605 .clkdm_name
= "ivahd_clkdm",
2608 .clkctrl_offs
= OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET
,
2609 .context_offs
= OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET
,
2610 .modulemode
= MODULEMODE_HWCTRL
,
2617 * bidirectional, multi-drop, multi-channel two-line serial interface between
2618 * the device and external components
2621 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc
= {
2623 .sysc_offs
= 0x0010,
2624 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
2625 SYSC_HAS_SOFTRESET
),
2626 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2628 .sysc_fields
= &omap_hwmod_sysc_type2
,
2631 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class
= {
2633 .sysc
= &omap44xx_slimbus_sysc
,
2637 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs
[] = {
2638 { .irq
= 97 + OMAP44XX_IRQ_GIC_START
},
2642 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs
[] = {
2643 { .name
= "tx0", .dma_req
= 84 + OMAP44XX_DMA_REQ_START
},
2644 { .name
= "tx1", .dma_req
= 85 + OMAP44XX_DMA_REQ_START
},
2645 { .name
= "tx2", .dma_req
= 86 + OMAP44XX_DMA_REQ_START
},
2646 { .name
= "tx3", .dma_req
= 87 + OMAP44XX_DMA_REQ_START
},
2647 { .name
= "rx0", .dma_req
= 88 + OMAP44XX_DMA_REQ_START
},
2648 { .name
= "rx1", .dma_req
= 89 + OMAP44XX_DMA_REQ_START
},
2649 { .name
= "rx2", .dma_req
= 90 + OMAP44XX_DMA_REQ_START
},
2650 { .name
= "rx3", .dma_req
= 91 + OMAP44XX_DMA_REQ_START
},
2654 static struct omap_hwmod_opt_clk slimbus1_opt_clks
[] = {
2655 { .role
= "fclk_1", .clk
= "slimbus1_fclk_1" },
2656 { .role
= "fclk_0", .clk
= "slimbus1_fclk_0" },
2657 { .role
= "fclk_2", .clk
= "slimbus1_fclk_2" },
2658 { .role
= "slimbus_clk", .clk
= "slimbus1_slimbus_clk" },
2661 static struct omap_hwmod omap44xx_slimbus1_hwmod
= {
2663 .class = &omap44xx_slimbus_hwmod_class
,
2664 .clkdm_name
= "abe_clkdm",
2665 .mpu_irqs
= omap44xx_slimbus1_irqs
,
2666 .sdma_reqs
= omap44xx_slimbus1_sdma_reqs
,
2669 .clkctrl_offs
= OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET
,
2670 .context_offs
= OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET
,
2671 .modulemode
= MODULEMODE_SWCTRL
,
2674 .opt_clks
= slimbus1_opt_clks
,
2675 .opt_clks_cnt
= ARRAY_SIZE(slimbus1_opt_clks
),
2679 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs
[] = {
2680 { .irq
= 98 + OMAP44XX_IRQ_GIC_START
},
2684 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs
[] = {
2685 { .name
= "tx0", .dma_req
= 92 + OMAP44XX_DMA_REQ_START
},
2686 { .name
= "tx1", .dma_req
= 93 + OMAP44XX_DMA_REQ_START
},
2687 { .name
= "tx2", .dma_req
= 94 + OMAP44XX_DMA_REQ_START
},
2688 { .name
= "tx3", .dma_req
= 95 + OMAP44XX_DMA_REQ_START
},
2689 { .name
= "rx0", .dma_req
= 96 + OMAP44XX_DMA_REQ_START
},
2690 { .name
= "rx1", .dma_req
= 97 + OMAP44XX_DMA_REQ_START
},
2691 { .name
= "rx2", .dma_req
= 98 + OMAP44XX_DMA_REQ_START
},
2692 { .name
= "rx3", .dma_req
= 99 + OMAP44XX_DMA_REQ_START
},
2696 static struct omap_hwmod_opt_clk slimbus2_opt_clks
[] = {
2697 { .role
= "fclk_1", .clk
= "slimbus2_fclk_1" },
2698 { .role
= "fclk_0", .clk
= "slimbus2_fclk_0" },
2699 { .role
= "slimbus_clk", .clk
= "slimbus2_slimbus_clk" },
2702 static struct omap_hwmod omap44xx_slimbus2_hwmod
= {
2704 .class = &omap44xx_slimbus_hwmod_class
,
2705 .clkdm_name
= "l4_per_clkdm",
2706 .mpu_irqs
= omap44xx_slimbus2_irqs
,
2707 .sdma_reqs
= omap44xx_slimbus2_sdma_reqs
,
2710 .clkctrl_offs
= OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET
,
2711 .context_offs
= OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET
,
2712 .modulemode
= MODULEMODE_SWCTRL
,
2715 .opt_clks
= slimbus2_opt_clks
,
2716 .opt_clks_cnt
= ARRAY_SIZE(slimbus2_opt_clks
),
2720 * 'smartreflex' class
2721 * smartreflex module (monitor silicon performance and outputs a measure of
2722 * performance error)
2725 /* The IP is not compliant to type1 / type2 scheme */
2726 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex
= {
2731 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc
= {
2732 .sysc_offs
= 0x0038,
2733 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
),
2734 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2736 .sysc_fields
= &omap_hwmod_sysc_type_smartreflex
,
2739 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class
= {
2740 .name
= "smartreflex",
2741 .sysc
= &omap44xx_smartreflex_sysc
,
2745 /* smartreflex_core */
2746 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr
= {
2747 .sensor_voltdm_name
= "core",
2750 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs
[] = {
2751 { .irq
= 19 + OMAP44XX_IRQ_GIC_START
},
2755 static struct omap_hwmod omap44xx_smartreflex_core_hwmod
= {
2756 .name
= "smartreflex_core",
2757 .class = &omap44xx_smartreflex_hwmod_class
,
2758 .clkdm_name
= "l4_ao_clkdm",
2759 .mpu_irqs
= omap44xx_smartreflex_core_irqs
,
2761 .main_clk
= "smartreflex_core_fck",
2764 .clkctrl_offs
= OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET
,
2765 .context_offs
= OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET
,
2766 .modulemode
= MODULEMODE_SWCTRL
,
2769 .dev_attr
= &smartreflex_core_dev_attr
,
2772 /* smartreflex_iva */
2773 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr
= {
2774 .sensor_voltdm_name
= "iva",
2777 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs
[] = {
2778 { .irq
= 102 + OMAP44XX_IRQ_GIC_START
},
2782 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod
= {
2783 .name
= "smartreflex_iva",
2784 .class = &omap44xx_smartreflex_hwmod_class
,
2785 .clkdm_name
= "l4_ao_clkdm",
2786 .mpu_irqs
= omap44xx_smartreflex_iva_irqs
,
2787 .main_clk
= "smartreflex_iva_fck",
2790 .clkctrl_offs
= OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET
,
2791 .context_offs
= OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET
,
2792 .modulemode
= MODULEMODE_SWCTRL
,
2795 .dev_attr
= &smartreflex_iva_dev_attr
,
2798 /* smartreflex_mpu */
2799 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr
= {
2800 .sensor_voltdm_name
= "mpu",
2803 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs
[] = {
2804 { .irq
= 18 + OMAP44XX_IRQ_GIC_START
},
2808 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod
= {
2809 .name
= "smartreflex_mpu",
2810 .class = &omap44xx_smartreflex_hwmod_class
,
2811 .clkdm_name
= "l4_ao_clkdm",
2812 .mpu_irqs
= omap44xx_smartreflex_mpu_irqs
,
2813 .main_clk
= "smartreflex_mpu_fck",
2816 .clkctrl_offs
= OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET
,
2817 .context_offs
= OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET
,
2818 .modulemode
= MODULEMODE_SWCTRL
,
2821 .dev_attr
= &smartreflex_mpu_dev_attr
,
2826 * spinlock provides hardware assistance for synchronizing the processes
2827 * running on multiple processors
2830 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc
= {
2832 .sysc_offs
= 0x0010,
2833 .syss_offs
= 0x0014,
2834 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
2835 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
2836 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
2837 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2839 .sysc_fields
= &omap_hwmod_sysc_type1
,
2842 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class
= {
2844 .sysc
= &omap44xx_spinlock_sysc
,
2848 static struct omap_hwmod omap44xx_spinlock_hwmod
= {
2850 .class = &omap44xx_spinlock_hwmod_class
,
2851 .clkdm_name
= "l4_cfg_clkdm",
2854 .clkctrl_offs
= OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET
,
2855 .context_offs
= OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET
,
2862 * general purpose timer module with accurate 1ms tick
2863 * This class contains several variants: ['timer_1ms', 'timer']
2866 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc
= {
2868 .sysc_offs
= 0x0010,
2869 .syss_offs
= 0x0014,
2870 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
2871 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
2872 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
2873 SYSS_HAS_RESET_STATUS
),
2874 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2875 .sysc_fields
= &omap_hwmod_sysc_type1
,
2878 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class
= {
2880 .sysc
= &omap44xx_timer_1ms_sysc
,
2883 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc
= {
2885 .sysc_offs
= 0x0010,
2886 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2887 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2888 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2890 .sysc_fields
= &omap_hwmod_sysc_type2
,
2893 static struct omap_hwmod_class omap44xx_timer_hwmod_class
= {
2895 .sysc
= &omap44xx_timer_sysc
,
2898 /* always-on timers dev attribute */
2899 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr
= {
2900 .timer_capability
= OMAP_TIMER_ALWON
,
2903 /* pwm timers dev attribute */
2904 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr
= {
2905 .timer_capability
= OMAP_TIMER_HAS_PWM
,
2909 static struct omap_hwmod_irq_info omap44xx_timer1_irqs
[] = {
2910 { .irq
= 37 + OMAP44XX_IRQ_GIC_START
},
2914 static struct omap_hwmod omap44xx_timer1_hwmod
= {
2916 .class = &omap44xx_timer_1ms_hwmod_class
,
2917 .clkdm_name
= "l4_wkup_clkdm",
2918 .mpu_irqs
= omap44xx_timer1_irqs
,
2919 .main_clk
= "timer1_fck",
2922 .clkctrl_offs
= OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET
,
2923 .context_offs
= OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET
,
2924 .modulemode
= MODULEMODE_SWCTRL
,
2927 .dev_attr
= &capability_alwon_dev_attr
,
2931 static struct omap_hwmod_irq_info omap44xx_timer2_irqs
[] = {
2932 { .irq
= 38 + OMAP44XX_IRQ_GIC_START
},
2936 static struct omap_hwmod omap44xx_timer2_hwmod
= {
2938 .class = &omap44xx_timer_1ms_hwmod_class
,
2939 .clkdm_name
= "l4_per_clkdm",
2940 .mpu_irqs
= omap44xx_timer2_irqs
,
2941 .main_clk
= "timer2_fck",
2944 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET
,
2945 .context_offs
= OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET
,
2946 .modulemode
= MODULEMODE_SWCTRL
,
2949 .dev_attr
= &capability_alwon_dev_attr
,
2953 static struct omap_hwmod_irq_info omap44xx_timer3_irqs
[] = {
2954 { .irq
= 39 + OMAP44XX_IRQ_GIC_START
},
2958 static struct omap_hwmod omap44xx_timer3_hwmod
= {
2960 .class = &omap44xx_timer_hwmod_class
,
2961 .clkdm_name
= "l4_per_clkdm",
2962 .mpu_irqs
= omap44xx_timer3_irqs
,
2963 .main_clk
= "timer3_fck",
2966 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET
,
2967 .context_offs
= OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET
,
2968 .modulemode
= MODULEMODE_SWCTRL
,
2971 .dev_attr
= &capability_alwon_dev_attr
,
2975 static struct omap_hwmod_irq_info omap44xx_timer4_irqs
[] = {
2976 { .irq
= 40 + OMAP44XX_IRQ_GIC_START
},
2980 static struct omap_hwmod omap44xx_timer4_hwmod
= {
2982 .class = &omap44xx_timer_hwmod_class
,
2983 .clkdm_name
= "l4_per_clkdm",
2984 .mpu_irqs
= omap44xx_timer4_irqs
,
2985 .main_clk
= "timer4_fck",
2988 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET
,
2989 .context_offs
= OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET
,
2990 .modulemode
= MODULEMODE_SWCTRL
,
2993 .dev_attr
= &capability_alwon_dev_attr
,
2997 static struct omap_hwmod_irq_info omap44xx_timer5_irqs
[] = {
2998 { .irq
= 41 + OMAP44XX_IRQ_GIC_START
},
3002 static struct omap_hwmod omap44xx_timer5_hwmod
= {
3004 .class = &omap44xx_timer_hwmod_class
,
3005 .clkdm_name
= "abe_clkdm",
3006 .mpu_irqs
= omap44xx_timer5_irqs
,
3007 .main_clk
= "timer5_fck",
3010 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET
,
3011 .context_offs
= OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET
,
3012 .modulemode
= MODULEMODE_SWCTRL
,
3015 .dev_attr
= &capability_alwon_dev_attr
,
3019 static struct omap_hwmod_irq_info omap44xx_timer6_irqs
[] = {
3020 { .irq
= 42 + OMAP44XX_IRQ_GIC_START
},
3024 static struct omap_hwmod omap44xx_timer6_hwmod
= {
3026 .class = &omap44xx_timer_hwmod_class
,
3027 .clkdm_name
= "abe_clkdm",
3028 .mpu_irqs
= omap44xx_timer6_irqs
,
3030 .main_clk
= "timer6_fck",
3033 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET
,
3034 .context_offs
= OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET
,
3035 .modulemode
= MODULEMODE_SWCTRL
,
3038 .dev_attr
= &capability_alwon_dev_attr
,
3042 static struct omap_hwmod_irq_info omap44xx_timer7_irqs
[] = {
3043 { .irq
= 43 + OMAP44XX_IRQ_GIC_START
},
3047 static struct omap_hwmod omap44xx_timer7_hwmod
= {
3049 .class = &omap44xx_timer_hwmod_class
,
3050 .clkdm_name
= "abe_clkdm",
3051 .mpu_irqs
= omap44xx_timer7_irqs
,
3052 .main_clk
= "timer7_fck",
3055 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET
,
3056 .context_offs
= OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET
,
3057 .modulemode
= MODULEMODE_SWCTRL
,
3060 .dev_attr
= &capability_alwon_dev_attr
,
3064 static struct omap_hwmod_irq_info omap44xx_timer8_irqs
[] = {
3065 { .irq
= 44 + OMAP44XX_IRQ_GIC_START
},
3069 static struct omap_hwmod omap44xx_timer8_hwmod
= {
3071 .class = &omap44xx_timer_hwmod_class
,
3072 .clkdm_name
= "abe_clkdm",
3073 .mpu_irqs
= omap44xx_timer8_irqs
,
3074 .main_clk
= "timer8_fck",
3077 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET
,
3078 .context_offs
= OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET
,
3079 .modulemode
= MODULEMODE_SWCTRL
,
3082 .dev_attr
= &capability_pwm_dev_attr
,
3086 static struct omap_hwmod_irq_info omap44xx_timer9_irqs
[] = {
3087 { .irq
= 45 + OMAP44XX_IRQ_GIC_START
},
3091 static struct omap_hwmod omap44xx_timer9_hwmod
= {
3093 .class = &omap44xx_timer_hwmod_class
,
3094 .clkdm_name
= "l4_per_clkdm",
3095 .mpu_irqs
= omap44xx_timer9_irqs
,
3096 .main_clk
= "timer9_fck",
3099 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET
,
3100 .context_offs
= OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET
,
3101 .modulemode
= MODULEMODE_SWCTRL
,
3104 .dev_attr
= &capability_pwm_dev_attr
,
3108 static struct omap_hwmod_irq_info omap44xx_timer10_irqs
[] = {
3109 { .irq
= 46 + OMAP44XX_IRQ_GIC_START
},
3113 static struct omap_hwmod omap44xx_timer10_hwmod
= {
3115 .class = &omap44xx_timer_1ms_hwmod_class
,
3116 .clkdm_name
= "l4_per_clkdm",
3117 .mpu_irqs
= omap44xx_timer10_irqs
,
3118 .main_clk
= "timer10_fck",
3121 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET
,
3122 .context_offs
= OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET
,
3123 .modulemode
= MODULEMODE_SWCTRL
,
3126 .dev_attr
= &capability_pwm_dev_attr
,
3130 static struct omap_hwmod_irq_info omap44xx_timer11_irqs
[] = {
3131 { .irq
= 47 + OMAP44XX_IRQ_GIC_START
},
3135 static struct omap_hwmod omap44xx_timer11_hwmod
= {
3137 .class = &omap44xx_timer_hwmod_class
,
3138 .clkdm_name
= "l4_per_clkdm",
3139 .mpu_irqs
= omap44xx_timer11_irqs
,
3140 .main_clk
= "timer11_fck",
3143 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET
,
3144 .context_offs
= OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET
,
3145 .modulemode
= MODULEMODE_SWCTRL
,
3148 .dev_attr
= &capability_pwm_dev_attr
,
3153 * universal asynchronous receiver/transmitter (uart)
3156 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc
= {
3158 .sysc_offs
= 0x0054,
3159 .syss_offs
= 0x0058,
3160 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
3161 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
3162 SYSS_HAS_RESET_STATUS
),
3163 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3165 .sysc_fields
= &omap_hwmod_sysc_type1
,
3168 static struct omap_hwmod_class omap44xx_uart_hwmod_class
= {
3170 .sysc
= &omap44xx_uart_sysc
,
3174 static struct omap_hwmod_irq_info omap44xx_uart1_irqs
[] = {
3175 { .irq
= 72 + OMAP44XX_IRQ_GIC_START
},
3179 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs
[] = {
3180 { .name
= "tx", .dma_req
= 48 + OMAP44XX_DMA_REQ_START
},
3181 { .name
= "rx", .dma_req
= 49 + OMAP44XX_DMA_REQ_START
},
3185 static struct omap_hwmod omap44xx_uart1_hwmod
= {
3187 .class = &omap44xx_uart_hwmod_class
,
3188 .clkdm_name
= "l4_per_clkdm",
3189 .mpu_irqs
= omap44xx_uart1_irqs
,
3190 .sdma_reqs
= omap44xx_uart1_sdma_reqs
,
3191 .main_clk
= "uart1_fck",
3194 .clkctrl_offs
= OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET
,
3195 .context_offs
= OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET
,
3196 .modulemode
= MODULEMODE_SWCTRL
,
3202 static struct omap_hwmod_irq_info omap44xx_uart2_irqs
[] = {
3203 { .irq
= 73 + OMAP44XX_IRQ_GIC_START
},
3207 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs
[] = {
3208 { .name
= "tx", .dma_req
= 50 + OMAP44XX_DMA_REQ_START
},
3209 { .name
= "rx", .dma_req
= 51 + OMAP44XX_DMA_REQ_START
},
3213 static struct omap_hwmod omap44xx_uart2_hwmod
= {
3215 .class = &omap44xx_uart_hwmod_class
,
3216 .clkdm_name
= "l4_per_clkdm",
3217 .mpu_irqs
= omap44xx_uart2_irqs
,
3218 .sdma_reqs
= omap44xx_uart2_sdma_reqs
,
3219 .main_clk
= "uart2_fck",
3222 .clkctrl_offs
= OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET
,
3223 .context_offs
= OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET
,
3224 .modulemode
= MODULEMODE_SWCTRL
,
3230 static struct omap_hwmod_irq_info omap44xx_uart3_irqs
[] = {
3231 { .irq
= 74 + OMAP44XX_IRQ_GIC_START
},
3235 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs
[] = {
3236 { .name
= "tx", .dma_req
= 52 + OMAP44XX_DMA_REQ_START
},
3237 { .name
= "rx", .dma_req
= 53 + OMAP44XX_DMA_REQ_START
},
3241 static struct omap_hwmod omap44xx_uart3_hwmod
= {
3243 .class = &omap44xx_uart_hwmod_class
,
3244 .clkdm_name
= "l4_per_clkdm",
3245 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
3246 .mpu_irqs
= omap44xx_uart3_irqs
,
3247 .sdma_reqs
= omap44xx_uart3_sdma_reqs
,
3248 .main_clk
= "uart3_fck",
3251 .clkctrl_offs
= OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET
,
3252 .context_offs
= OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET
,
3253 .modulemode
= MODULEMODE_SWCTRL
,
3259 static struct omap_hwmod_irq_info omap44xx_uart4_irqs
[] = {
3260 { .irq
= 70 + OMAP44XX_IRQ_GIC_START
},
3264 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs
[] = {
3265 { .name
= "tx", .dma_req
= 54 + OMAP44XX_DMA_REQ_START
},
3266 { .name
= "rx", .dma_req
= 55 + OMAP44XX_DMA_REQ_START
},
3270 static struct omap_hwmod omap44xx_uart4_hwmod
= {
3272 .class = &omap44xx_uart_hwmod_class
,
3273 .clkdm_name
= "l4_per_clkdm",
3274 .mpu_irqs
= omap44xx_uart4_irqs
,
3275 .sdma_reqs
= omap44xx_uart4_sdma_reqs
,
3276 .main_clk
= "uart4_fck",
3279 .clkctrl_offs
= OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET
,
3280 .context_offs
= OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET
,
3281 .modulemode
= MODULEMODE_SWCTRL
,
3287 * 'usb_host_fs' class
3288 * full-speed usb host controller
3291 /* The IP is not compliant to type1 / type2 scheme */
3292 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs
= {
3298 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc
= {
3300 .sysc_offs
= 0x0210,
3301 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3302 SYSC_HAS_SOFTRESET
),
3303 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3305 .sysc_fields
= &omap_hwmod_sysc_type_usb_host_fs
,
3308 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class
= {
3309 .name
= "usb_host_fs",
3310 .sysc
= &omap44xx_usb_host_fs_sysc
,
3314 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs
[] = {
3315 { .name
= "std", .irq
= 89 + OMAP44XX_IRQ_GIC_START
},
3316 { .name
= "smi", .irq
= 90 + OMAP44XX_IRQ_GIC_START
},
3320 static struct omap_hwmod omap44xx_usb_host_fs_hwmod
= {
3321 .name
= "usb_host_fs",
3322 .class = &omap44xx_usb_host_fs_hwmod_class
,
3323 .clkdm_name
= "l3_init_clkdm",
3324 .mpu_irqs
= omap44xx_usb_host_fs_irqs
,
3325 .main_clk
= "usb_host_fs_fck",
3328 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET
,
3329 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET
,
3330 .modulemode
= MODULEMODE_SWCTRL
,
3336 * 'usb_host_hs' class
3337 * high-speed multi-port usb host controller
3340 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc
= {
3342 .sysc_offs
= 0x0010,
3343 .syss_offs
= 0x0014,
3344 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3345 SYSC_HAS_SOFTRESET
),
3346 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3347 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
3348 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
3349 .sysc_fields
= &omap_hwmod_sysc_type2
,
3352 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class
= {
3353 .name
= "usb_host_hs",
3354 .sysc
= &omap44xx_usb_host_hs_sysc
,
3358 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs
[] = {
3359 { .name
= "ohci-irq", .irq
= 76 + OMAP44XX_IRQ_GIC_START
},
3360 { .name
= "ehci-irq", .irq
= 77 + OMAP44XX_IRQ_GIC_START
},
3364 static struct omap_hwmod omap44xx_usb_host_hs_hwmod
= {
3365 .name
= "usb_host_hs",
3366 .class = &omap44xx_usb_host_hs_hwmod_class
,
3367 .clkdm_name
= "l3_init_clkdm",
3368 .main_clk
= "usb_host_hs_fck",
3371 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET
,
3372 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET
,
3373 .modulemode
= MODULEMODE_SWCTRL
,
3376 .mpu_irqs
= omap44xx_usb_host_hs_irqs
,
3379 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3383 * In the following configuration :
3384 * - USBHOST module is set to smart-idle mode
3385 * - PRCM asserts idle_req to the USBHOST module ( This typically
3386 * happens when the system is going to a low power mode : all ports
3387 * have been suspended, the master part of the USBHOST module has
3388 * entered the standby state, and SW has cut the functional clocks)
3389 * - an USBHOST interrupt occurs before the module is able to answer
3390 * idle_ack, typically a remote wakeup IRQ.
3391 * Then the USB HOST module will enter a deadlock situation where it
3392 * is no more accessible nor functional.
3395 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3399 * Errata: USB host EHCI may stall when entering smart-standby mode
3403 * When the USBHOST module is set to smart-standby mode, and when it is
3404 * ready to enter the standby state (i.e. all ports are suspended and
3405 * all attached devices are in suspend mode), then it can wrongly assert
3406 * the Mstandby signal too early while there are still some residual OCP
3407 * transactions ongoing. If this condition occurs, the internal state
3408 * machine may go to an undefined state and the USB link may be stuck
3409 * upon the next resume.
3412 * Don't use smart standby; use only force standby,
3413 * hence HWMOD_SWSUP_MSTANDBY
3417 * During system boot; If the hwmod framework resets the module
3418 * the module will have smart idle settings; which can lead to deadlock
3419 * (above Errata Id:i660); so, dont reset the module during boot;
3420 * Use HWMOD_INIT_NO_RESET.
3423 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
|
3424 HWMOD_INIT_NO_RESET
,
3428 * 'usb_otg_hs' class
3429 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3432 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc
= {
3434 .sysc_offs
= 0x0404,
3435 .syss_offs
= 0x0408,
3436 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
3437 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3438 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3439 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3440 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
3442 .sysc_fields
= &omap_hwmod_sysc_type1
,
3445 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class
= {
3446 .name
= "usb_otg_hs",
3447 .sysc
= &omap44xx_usb_otg_hs_sysc
,
3451 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs
[] = {
3452 { .name
= "mc", .irq
= 92 + OMAP44XX_IRQ_GIC_START
},
3453 { .name
= "dma", .irq
= 93 + OMAP44XX_IRQ_GIC_START
},
3457 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks
[] = {
3458 { .role
= "xclk", .clk
= "usb_otg_hs_xclk" },
3461 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod
= {
3462 .name
= "usb_otg_hs",
3463 .class = &omap44xx_usb_otg_hs_hwmod_class
,
3464 .clkdm_name
= "l3_init_clkdm",
3465 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
3466 .mpu_irqs
= omap44xx_usb_otg_hs_irqs
,
3467 .main_clk
= "usb_otg_hs_ick",
3470 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET
,
3471 .context_offs
= OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET
,
3472 .modulemode
= MODULEMODE_HWCTRL
,
3475 .opt_clks
= usb_otg_hs_opt_clks
,
3476 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_hs_opt_clks
),
3480 * 'usb_tll_hs' class
3481 * usb_tll_hs module is the adapter on the usb_host_hs ports
3484 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc
= {
3486 .sysc_offs
= 0x0010,
3487 .syss_offs
= 0x0014,
3488 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
3489 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
3491 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3492 .sysc_fields
= &omap_hwmod_sysc_type1
,
3495 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class
= {
3496 .name
= "usb_tll_hs",
3497 .sysc
= &omap44xx_usb_tll_hs_sysc
,
3500 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs
[] = {
3501 { .name
= "tll-irq", .irq
= 78 + OMAP44XX_IRQ_GIC_START
},
3505 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod
= {
3506 .name
= "usb_tll_hs",
3507 .class = &omap44xx_usb_tll_hs_hwmod_class
,
3508 .clkdm_name
= "l3_init_clkdm",
3509 .mpu_irqs
= omap44xx_usb_tll_hs_irqs
,
3510 .main_clk
= "usb_tll_hs_ick",
3513 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET
,
3514 .context_offs
= OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET
,
3515 .modulemode
= MODULEMODE_HWCTRL
,
3522 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3523 * overflow condition
3526 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc
= {
3528 .sysc_offs
= 0x0010,
3529 .syss_offs
= 0x0014,
3530 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
3531 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3532 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3534 .sysc_fields
= &omap_hwmod_sysc_type1
,
3537 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class
= {
3539 .sysc
= &omap44xx_wd_timer_sysc
,
3540 .pre_shutdown
= &omap2_wd_timer_disable
,
3541 .reset
= &omap2_wd_timer_reset
,
3545 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs
[] = {
3546 { .irq
= 80 + OMAP44XX_IRQ_GIC_START
},
3550 static struct omap_hwmod omap44xx_wd_timer2_hwmod
= {
3551 .name
= "wd_timer2",
3552 .class = &omap44xx_wd_timer_hwmod_class
,
3553 .clkdm_name
= "l4_wkup_clkdm",
3554 .mpu_irqs
= omap44xx_wd_timer2_irqs
,
3555 .main_clk
= "wd_timer2_fck",
3558 .clkctrl_offs
= OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET
,
3559 .context_offs
= OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET
,
3560 .modulemode
= MODULEMODE_SWCTRL
,
3566 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs
[] = {
3567 { .irq
= 36 + OMAP44XX_IRQ_GIC_START
},
3571 static struct omap_hwmod omap44xx_wd_timer3_hwmod
= {
3572 .name
= "wd_timer3",
3573 .class = &omap44xx_wd_timer_hwmod_class
,
3574 .clkdm_name
= "abe_clkdm",
3575 .mpu_irqs
= omap44xx_wd_timer3_irqs
,
3576 .main_clk
= "wd_timer3_fck",
3579 .clkctrl_offs
= OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET
,
3580 .context_offs
= OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET
,
3581 .modulemode
= MODULEMODE_SWCTRL
,
3591 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs
[] = {
3593 .pa_start
= 0x4a204000,
3594 .pa_end
= 0x4a2040ff,
3595 .flags
= ADDR_TYPE_RT
3600 /* c2c -> c2c_target_fw */
3601 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw
= {
3602 .master
= &omap44xx_c2c_hwmod
,
3603 .slave
= &omap44xx_c2c_target_fw_hwmod
,
3604 .clk
= "div_core_ck",
3605 .addr
= omap44xx_c2c_target_fw_addrs
,
3606 .user
= OCP_USER_MPU
,
3609 /* l4_cfg -> c2c_target_fw */
3610 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw
= {
3611 .master
= &omap44xx_l4_cfg_hwmod
,
3612 .slave
= &omap44xx_c2c_target_fw_hwmod
,
3614 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3617 /* l3_main_1 -> dmm */
3618 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm
= {
3619 .master
= &omap44xx_l3_main_1_hwmod
,
3620 .slave
= &omap44xx_dmm_hwmod
,
3622 .user
= OCP_USER_SDMA
,
3625 static struct omap_hwmod_addr_space omap44xx_dmm_addrs
[] = {
3627 .pa_start
= 0x4e000000,
3628 .pa_end
= 0x4e0007ff,
3629 .flags
= ADDR_TYPE_RT
3635 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm
= {
3636 .master
= &omap44xx_mpu_hwmod
,
3637 .slave
= &omap44xx_dmm_hwmod
,
3639 .addr
= omap44xx_dmm_addrs
,
3640 .user
= OCP_USER_MPU
,
3643 /* c2c -> emif_fw */
3644 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw
= {
3645 .master
= &omap44xx_c2c_hwmod
,
3646 .slave
= &omap44xx_emif_fw_hwmod
,
3647 .clk
= "div_core_ck",
3648 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3651 /* dmm -> emif_fw */
3652 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw
= {
3653 .master
= &omap44xx_dmm_hwmod
,
3654 .slave
= &omap44xx_emif_fw_hwmod
,
3656 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3659 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs
[] = {
3661 .pa_start
= 0x4a20c000,
3662 .pa_end
= 0x4a20c0ff,
3663 .flags
= ADDR_TYPE_RT
3668 /* l4_cfg -> emif_fw */
3669 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw
= {
3670 .master
= &omap44xx_l4_cfg_hwmod
,
3671 .slave
= &omap44xx_emif_fw_hwmod
,
3673 .addr
= omap44xx_emif_fw_addrs
,
3674 .user
= OCP_USER_MPU
,
3677 /* iva -> l3_instr */
3678 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr
= {
3679 .master
= &omap44xx_iva_hwmod
,
3680 .slave
= &omap44xx_l3_instr_hwmod
,
3682 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3685 /* l3_main_3 -> l3_instr */
3686 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr
= {
3687 .master
= &omap44xx_l3_main_3_hwmod
,
3688 .slave
= &omap44xx_l3_instr_hwmod
,
3690 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3693 /* ocp_wp_noc -> l3_instr */
3694 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr
= {
3695 .master
= &omap44xx_ocp_wp_noc_hwmod
,
3696 .slave
= &omap44xx_l3_instr_hwmod
,
3698 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3701 /* dsp -> l3_main_1 */
3702 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1
= {
3703 .master
= &omap44xx_dsp_hwmod
,
3704 .slave
= &omap44xx_l3_main_1_hwmod
,
3706 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3709 /* dss -> l3_main_1 */
3710 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1
= {
3711 .master
= &omap44xx_dss_hwmod
,
3712 .slave
= &omap44xx_l3_main_1_hwmod
,
3714 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3717 /* l3_main_2 -> l3_main_1 */
3718 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1
= {
3719 .master
= &omap44xx_l3_main_2_hwmod
,
3720 .slave
= &omap44xx_l3_main_1_hwmod
,
3722 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3725 /* l4_cfg -> l3_main_1 */
3726 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1
= {
3727 .master
= &omap44xx_l4_cfg_hwmod
,
3728 .slave
= &omap44xx_l3_main_1_hwmod
,
3730 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3733 /* mmc1 -> l3_main_1 */
3734 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1
= {
3735 .master
= &omap44xx_mmc1_hwmod
,
3736 .slave
= &omap44xx_l3_main_1_hwmod
,
3738 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3741 /* mmc2 -> l3_main_1 */
3742 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1
= {
3743 .master
= &omap44xx_mmc2_hwmod
,
3744 .slave
= &omap44xx_l3_main_1_hwmod
,
3746 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3749 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs
[] = {
3751 .pa_start
= 0x44000000,
3752 .pa_end
= 0x44000fff,
3753 .flags
= ADDR_TYPE_RT
3758 /* mpu -> l3_main_1 */
3759 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1
= {
3760 .master
= &omap44xx_mpu_hwmod
,
3761 .slave
= &omap44xx_l3_main_1_hwmod
,
3763 .addr
= omap44xx_l3_main_1_addrs
,
3764 .user
= OCP_USER_MPU
,
3767 /* c2c_target_fw -> l3_main_2 */
3768 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2
= {
3769 .master
= &omap44xx_c2c_target_fw_hwmod
,
3770 .slave
= &omap44xx_l3_main_2_hwmod
,
3772 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3775 /* debugss -> l3_main_2 */
3776 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2
= {
3777 .master
= &omap44xx_debugss_hwmod
,
3778 .slave
= &omap44xx_l3_main_2_hwmod
,
3779 .clk
= "dbgclk_mux_ck",
3780 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3783 /* dma_system -> l3_main_2 */
3784 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2
= {
3785 .master
= &omap44xx_dma_system_hwmod
,
3786 .slave
= &omap44xx_l3_main_2_hwmod
,
3788 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3791 /* fdif -> l3_main_2 */
3792 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2
= {
3793 .master
= &omap44xx_fdif_hwmod
,
3794 .slave
= &omap44xx_l3_main_2_hwmod
,
3796 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3799 /* gpu -> l3_main_2 */
3800 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2
= {
3801 .master
= &omap44xx_gpu_hwmod
,
3802 .slave
= &omap44xx_l3_main_2_hwmod
,
3804 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3807 /* hsi -> l3_main_2 */
3808 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2
= {
3809 .master
= &omap44xx_hsi_hwmod
,
3810 .slave
= &omap44xx_l3_main_2_hwmod
,
3812 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3815 /* ipu -> l3_main_2 */
3816 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2
= {
3817 .master
= &omap44xx_ipu_hwmod
,
3818 .slave
= &omap44xx_l3_main_2_hwmod
,
3820 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3823 /* iss -> l3_main_2 */
3824 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2
= {
3825 .master
= &omap44xx_iss_hwmod
,
3826 .slave
= &omap44xx_l3_main_2_hwmod
,
3828 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3831 /* iva -> l3_main_2 */
3832 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2
= {
3833 .master
= &omap44xx_iva_hwmod
,
3834 .slave
= &omap44xx_l3_main_2_hwmod
,
3836 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3839 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs
[] = {
3841 .pa_start
= 0x44800000,
3842 .pa_end
= 0x44801fff,
3843 .flags
= ADDR_TYPE_RT
3848 /* l3_main_1 -> l3_main_2 */
3849 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2
= {
3850 .master
= &omap44xx_l3_main_1_hwmod
,
3851 .slave
= &omap44xx_l3_main_2_hwmod
,
3853 .addr
= omap44xx_l3_main_2_addrs
,
3854 .user
= OCP_USER_MPU
,
3857 /* l4_cfg -> l3_main_2 */
3858 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2
= {
3859 .master
= &omap44xx_l4_cfg_hwmod
,
3860 .slave
= &omap44xx_l3_main_2_hwmod
,
3862 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3865 /* usb_host_fs -> l3_main_2 */
3866 static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2
= {
3867 .master
= &omap44xx_usb_host_fs_hwmod
,
3868 .slave
= &omap44xx_l3_main_2_hwmod
,
3870 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3873 /* usb_host_hs -> l3_main_2 */
3874 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2
= {
3875 .master
= &omap44xx_usb_host_hs_hwmod
,
3876 .slave
= &omap44xx_l3_main_2_hwmod
,
3878 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3881 /* usb_otg_hs -> l3_main_2 */
3882 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2
= {
3883 .master
= &omap44xx_usb_otg_hs_hwmod
,
3884 .slave
= &omap44xx_l3_main_2_hwmod
,
3886 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3889 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs
[] = {
3891 .pa_start
= 0x45000000,
3892 .pa_end
= 0x45000fff,
3893 .flags
= ADDR_TYPE_RT
3898 /* l3_main_1 -> l3_main_3 */
3899 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3
= {
3900 .master
= &omap44xx_l3_main_1_hwmod
,
3901 .slave
= &omap44xx_l3_main_3_hwmod
,
3903 .addr
= omap44xx_l3_main_3_addrs
,
3904 .user
= OCP_USER_MPU
,
3907 /* l3_main_2 -> l3_main_3 */
3908 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3
= {
3909 .master
= &omap44xx_l3_main_2_hwmod
,
3910 .slave
= &omap44xx_l3_main_3_hwmod
,
3912 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3915 /* l4_cfg -> l3_main_3 */
3916 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3
= {
3917 .master
= &omap44xx_l4_cfg_hwmod
,
3918 .slave
= &omap44xx_l3_main_3_hwmod
,
3920 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3923 /* aess -> l4_abe */
3924 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe
= {
3925 .master
= &omap44xx_aess_hwmod
,
3926 .slave
= &omap44xx_l4_abe_hwmod
,
3927 .clk
= "ocp_abe_iclk",
3928 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3932 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe
= {
3933 .master
= &omap44xx_dsp_hwmod
,
3934 .slave
= &omap44xx_l4_abe_hwmod
,
3935 .clk
= "ocp_abe_iclk",
3936 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3939 /* l3_main_1 -> l4_abe */
3940 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe
= {
3941 .master
= &omap44xx_l3_main_1_hwmod
,
3942 .slave
= &omap44xx_l4_abe_hwmod
,
3944 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3948 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe
= {
3949 .master
= &omap44xx_mpu_hwmod
,
3950 .slave
= &omap44xx_l4_abe_hwmod
,
3951 .clk
= "ocp_abe_iclk",
3952 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3955 /* l3_main_1 -> l4_cfg */
3956 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg
= {
3957 .master
= &omap44xx_l3_main_1_hwmod
,
3958 .slave
= &omap44xx_l4_cfg_hwmod
,
3960 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3963 /* l3_main_2 -> l4_per */
3964 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per
= {
3965 .master
= &omap44xx_l3_main_2_hwmod
,
3966 .slave
= &omap44xx_l4_per_hwmod
,
3968 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3971 /* l4_cfg -> l4_wkup */
3972 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup
= {
3973 .master
= &omap44xx_l4_cfg_hwmod
,
3974 .slave
= &omap44xx_l4_wkup_hwmod
,
3976 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3979 /* mpu -> mpu_private */
3980 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private
= {
3981 .master
= &omap44xx_mpu_hwmod
,
3982 .slave
= &omap44xx_mpu_private_hwmod
,
3984 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3987 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs
[] = {
3989 .pa_start
= 0x4a102000,
3990 .pa_end
= 0x4a10207f,
3991 .flags
= ADDR_TYPE_RT
3996 /* l4_cfg -> ocp_wp_noc */
3997 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc
= {
3998 .master
= &omap44xx_l4_cfg_hwmod
,
3999 .slave
= &omap44xx_ocp_wp_noc_hwmod
,
4001 .addr
= omap44xx_ocp_wp_noc_addrs
,
4002 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4005 static struct omap_hwmod_addr_space omap44xx_aess_addrs
[] = {
4007 .pa_start
= 0x401f1000,
4008 .pa_end
= 0x401f13ff,
4009 .flags
= ADDR_TYPE_RT
4014 /* l4_abe -> aess */
4015 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess
= {
4016 .master
= &omap44xx_l4_abe_hwmod
,
4017 .slave
= &omap44xx_aess_hwmod
,
4018 .clk
= "ocp_abe_iclk",
4019 .addr
= omap44xx_aess_addrs
,
4020 .user
= OCP_USER_MPU
,
4023 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs
[] = {
4025 .pa_start
= 0x490f1000,
4026 .pa_end
= 0x490f13ff,
4027 .flags
= ADDR_TYPE_RT
4032 /* l4_abe -> aess (dma) */
4033 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma
= {
4034 .master
= &omap44xx_l4_abe_hwmod
,
4035 .slave
= &omap44xx_aess_hwmod
,
4036 .clk
= "ocp_abe_iclk",
4037 .addr
= omap44xx_aess_dma_addrs
,
4038 .user
= OCP_USER_SDMA
,
4041 /* l3_main_2 -> c2c */
4042 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c
= {
4043 .master
= &omap44xx_l3_main_2_hwmod
,
4044 .slave
= &omap44xx_c2c_hwmod
,
4046 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4049 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs
[] = {
4051 .pa_start
= 0x4a304000,
4052 .pa_end
= 0x4a30401f,
4053 .flags
= ADDR_TYPE_RT
4058 /* l4_wkup -> counter_32k */
4059 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k
= {
4060 .master
= &omap44xx_l4_wkup_hwmod
,
4061 .slave
= &omap44xx_counter_32k_hwmod
,
4062 .clk
= "l4_wkup_clk_mux_ck",
4063 .addr
= omap44xx_counter_32k_addrs
,
4064 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4067 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs
[] = {
4069 .pa_start
= 0x4a002000,
4070 .pa_end
= 0x4a0027ff,
4071 .flags
= ADDR_TYPE_RT
4076 /* l4_cfg -> ctrl_module_core */
4077 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core
= {
4078 .master
= &omap44xx_l4_cfg_hwmod
,
4079 .slave
= &omap44xx_ctrl_module_core_hwmod
,
4081 .addr
= omap44xx_ctrl_module_core_addrs
,
4082 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4085 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs
[] = {
4087 .pa_start
= 0x4a100000,
4088 .pa_end
= 0x4a1007ff,
4089 .flags
= ADDR_TYPE_RT
4094 /* l4_cfg -> ctrl_module_pad_core */
4095 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core
= {
4096 .master
= &omap44xx_l4_cfg_hwmod
,
4097 .slave
= &omap44xx_ctrl_module_pad_core_hwmod
,
4099 .addr
= omap44xx_ctrl_module_pad_core_addrs
,
4100 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4103 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs
[] = {
4105 .pa_start
= 0x4a30c000,
4106 .pa_end
= 0x4a30c7ff,
4107 .flags
= ADDR_TYPE_RT
4112 /* l4_wkup -> ctrl_module_wkup */
4113 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup
= {
4114 .master
= &omap44xx_l4_wkup_hwmod
,
4115 .slave
= &omap44xx_ctrl_module_wkup_hwmod
,
4116 .clk
= "l4_wkup_clk_mux_ck",
4117 .addr
= omap44xx_ctrl_module_wkup_addrs
,
4118 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4121 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs
[] = {
4123 .pa_start
= 0x4a31e000,
4124 .pa_end
= 0x4a31e7ff,
4125 .flags
= ADDR_TYPE_RT
4130 /* l4_wkup -> ctrl_module_pad_wkup */
4131 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup
= {
4132 .master
= &omap44xx_l4_wkup_hwmod
,
4133 .slave
= &omap44xx_ctrl_module_pad_wkup_hwmod
,
4134 .clk
= "l4_wkup_clk_mux_ck",
4135 .addr
= omap44xx_ctrl_module_pad_wkup_addrs
,
4136 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4139 static struct omap_hwmod_addr_space omap44xx_debugss_addrs
[] = {
4141 .pa_start
= 0x54160000,
4142 .pa_end
= 0x54167fff,
4143 .flags
= ADDR_TYPE_RT
4148 /* l3_instr -> debugss */
4149 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss
= {
4150 .master
= &omap44xx_l3_instr_hwmod
,
4151 .slave
= &omap44xx_debugss_hwmod
,
4153 .addr
= omap44xx_debugss_addrs
,
4154 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4157 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs
[] = {
4159 .pa_start
= 0x4a056000,
4160 .pa_end
= 0x4a056fff,
4161 .flags
= ADDR_TYPE_RT
4166 /* l4_cfg -> dma_system */
4167 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system
= {
4168 .master
= &omap44xx_l4_cfg_hwmod
,
4169 .slave
= &omap44xx_dma_system_hwmod
,
4171 .addr
= omap44xx_dma_system_addrs
,
4172 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4175 static struct omap_hwmod_addr_space omap44xx_dmic_addrs
[] = {
4178 .pa_start
= 0x4012e000,
4179 .pa_end
= 0x4012e07f,
4180 .flags
= ADDR_TYPE_RT
4185 /* l4_abe -> dmic */
4186 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic
= {
4187 .master
= &omap44xx_l4_abe_hwmod
,
4188 .slave
= &omap44xx_dmic_hwmod
,
4189 .clk
= "ocp_abe_iclk",
4190 .addr
= omap44xx_dmic_addrs
,
4191 .user
= OCP_USER_MPU
,
4194 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs
[] = {
4197 .pa_start
= 0x4902e000,
4198 .pa_end
= 0x4902e07f,
4199 .flags
= ADDR_TYPE_RT
4204 /* l4_abe -> dmic (dma) */
4205 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma
= {
4206 .master
= &omap44xx_l4_abe_hwmod
,
4207 .slave
= &omap44xx_dmic_hwmod
,
4208 .clk
= "ocp_abe_iclk",
4209 .addr
= omap44xx_dmic_dma_addrs
,
4210 .user
= OCP_USER_SDMA
,
4214 static struct omap_hwmod_ocp_if omap44xx_dsp__iva
= {
4215 .master
= &omap44xx_dsp_hwmod
,
4216 .slave
= &omap44xx_iva_hwmod
,
4217 .clk
= "dpll_iva_m5x2_ck",
4218 .user
= OCP_USER_DSP
,
4222 static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if
= {
4223 .master
= &omap44xx_dsp_hwmod
,
4224 .slave
= &omap44xx_sl2if_hwmod
,
4225 .clk
= "dpll_iva_m5x2_ck",
4226 .user
= OCP_USER_DSP
,
4230 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp
= {
4231 .master
= &omap44xx_l4_cfg_hwmod
,
4232 .slave
= &omap44xx_dsp_hwmod
,
4234 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4237 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs
[] = {
4239 .pa_start
= 0x58000000,
4240 .pa_end
= 0x5800007f,
4241 .flags
= ADDR_TYPE_RT
4246 /* l3_main_2 -> dss */
4247 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss
= {
4248 .master
= &omap44xx_l3_main_2_hwmod
,
4249 .slave
= &omap44xx_dss_hwmod
,
4251 .addr
= omap44xx_dss_dma_addrs
,
4252 .user
= OCP_USER_SDMA
,
4255 static struct omap_hwmod_addr_space omap44xx_dss_addrs
[] = {
4257 .pa_start
= 0x48040000,
4258 .pa_end
= 0x4804007f,
4259 .flags
= ADDR_TYPE_RT
4265 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss
= {
4266 .master
= &omap44xx_l4_per_hwmod
,
4267 .slave
= &omap44xx_dss_hwmod
,
4269 .addr
= omap44xx_dss_addrs
,
4270 .user
= OCP_USER_MPU
,
4273 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs
[] = {
4275 .pa_start
= 0x58001000,
4276 .pa_end
= 0x58001fff,
4277 .flags
= ADDR_TYPE_RT
4282 /* l3_main_2 -> dss_dispc */
4283 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc
= {
4284 .master
= &omap44xx_l3_main_2_hwmod
,
4285 .slave
= &omap44xx_dss_dispc_hwmod
,
4287 .addr
= omap44xx_dss_dispc_dma_addrs
,
4288 .user
= OCP_USER_SDMA
,
4291 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs
[] = {
4293 .pa_start
= 0x48041000,
4294 .pa_end
= 0x48041fff,
4295 .flags
= ADDR_TYPE_RT
4300 /* l4_per -> dss_dispc */
4301 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc
= {
4302 .master
= &omap44xx_l4_per_hwmod
,
4303 .slave
= &omap44xx_dss_dispc_hwmod
,
4305 .addr
= omap44xx_dss_dispc_addrs
,
4306 .user
= OCP_USER_MPU
,
4309 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs
[] = {
4311 .pa_start
= 0x58004000,
4312 .pa_end
= 0x580041ff,
4313 .flags
= ADDR_TYPE_RT
4318 /* l3_main_2 -> dss_dsi1 */
4319 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1
= {
4320 .master
= &omap44xx_l3_main_2_hwmod
,
4321 .slave
= &omap44xx_dss_dsi1_hwmod
,
4323 .addr
= omap44xx_dss_dsi1_dma_addrs
,
4324 .user
= OCP_USER_SDMA
,
4327 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs
[] = {
4329 .pa_start
= 0x48044000,
4330 .pa_end
= 0x480441ff,
4331 .flags
= ADDR_TYPE_RT
4336 /* l4_per -> dss_dsi1 */
4337 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1
= {
4338 .master
= &omap44xx_l4_per_hwmod
,
4339 .slave
= &omap44xx_dss_dsi1_hwmod
,
4341 .addr
= omap44xx_dss_dsi1_addrs
,
4342 .user
= OCP_USER_MPU
,
4345 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs
[] = {
4347 .pa_start
= 0x58005000,
4348 .pa_end
= 0x580051ff,
4349 .flags
= ADDR_TYPE_RT
4354 /* l3_main_2 -> dss_dsi2 */
4355 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2
= {
4356 .master
= &omap44xx_l3_main_2_hwmod
,
4357 .slave
= &omap44xx_dss_dsi2_hwmod
,
4359 .addr
= omap44xx_dss_dsi2_dma_addrs
,
4360 .user
= OCP_USER_SDMA
,
4363 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs
[] = {
4365 .pa_start
= 0x48045000,
4366 .pa_end
= 0x480451ff,
4367 .flags
= ADDR_TYPE_RT
4372 /* l4_per -> dss_dsi2 */
4373 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2
= {
4374 .master
= &omap44xx_l4_per_hwmod
,
4375 .slave
= &omap44xx_dss_dsi2_hwmod
,
4377 .addr
= omap44xx_dss_dsi2_addrs
,
4378 .user
= OCP_USER_MPU
,
4381 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs
[] = {
4383 .pa_start
= 0x58006000,
4384 .pa_end
= 0x58006fff,
4385 .flags
= ADDR_TYPE_RT
4390 /* l3_main_2 -> dss_hdmi */
4391 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi
= {
4392 .master
= &omap44xx_l3_main_2_hwmod
,
4393 .slave
= &omap44xx_dss_hdmi_hwmod
,
4395 .addr
= omap44xx_dss_hdmi_dma_addrs
,
4396 .user
= OCP_USER_SDMA
,
4399 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs
[] = {
4401 .pa_start
= 0x48046000,
4402 .pa_end
= 0x48046fff,
4403 .flags
= ADDR_TYPE_RT
4408 /* l4_per -> dss_hdmi */
4409 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi
= {
4410 .master
= &omap44xx_l4_per_hwmod
,
4411 .slave
= &omap44xx_dss_hdmi_hwmod
,
4413 .addr
= omap44xx_dss_hdmi_addrs
,
4414 .user
= OCP_USER_MPU
,
4417 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs
[] = {
4419 .pa_start
= 0x58002000,
4420 .pa_end
= 0x580020ff,
4421 .flags
= ADDR_TYPE_RT
4426 /* l3_main_2 -> dss_rfbi */
4427 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi
= {
4428 .master
= &omap44xx_l3_main_2_hwmod
,
4429 .slave
= &omap44xx_dss_rfbi_hwmod
,
4431 .addr
= omap44xx_dss_rfbi_dma_addrs
,
4432 .user
= OCP_USER_SDMA
,
4435 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs
[] = {
4437 .pa_start
= 0x48042000,
4438 .pa_end
= 0x480420ff,
4439 .flags
= ADDR_TYPE_RT
4444 /* l4_per -> dss_rfbi */
4445 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi
= {
4446 .master
= &omap44xx_l4_per_hwmod
,
4447 .slave
= &omap44xx_dss_rfbi_hwmod
,
4449 .addr
= omap44xx_dss_rfbi_addrs
,
4450 .user
= OCP_USER_MPU
,
4453 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs
[] = {
4455 .pa_start
= 0x58003000,
4456 .pa_end
= 0x580030ff,
4457 .flags
= ADDR_TYPE_RT
4462 /* l3_main_2 -> dss_venc */
4463 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc
= {
4464 .master
= &omap44xx_l3_main_2_hwmod
,
4465 .slave
= &omap44xx_dss_venc_hwmod
,
4467 .addr
= omap44xx_dss_venc_dma_addrs
,
4468 .user
= OCP_USER_SDMA
,
4471 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs
[] = {
4473 .pa_start
= 0x48043000,
4474 .pa_end
= 0x480430ff,
4475 .flags
= ADDR_TYPE_RT
4480 /* l4_per -> dss_venc */
4481 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc
= {
4482 .master
= &omap44xx_l4_per_hwmod
,
4483 .slave
= &omap44xx_dss_venc_hwmod
,
4485 .addr
= omap44xx_dss_venc_addrs
,
4486 .user
= OCP_USER_MPU
,
4489 static struct omap_hwmod_addr_space omap44xx_elm_addrs
[] = {
4491 .pa_start
= 0x48078000,
4492 .pa_end
= 0x48078fff,
4493 .flags
= ADDR_TYPE_RT
4499 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm
= {
4500 .master
= &omap44xx_l4_per_hwmod
,
4501 .slave
= &omap44xx_elm_hwmod
,
4503 .addr
= omap44xx_elm_addrs
,
4504 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4507 static struct omap_hwmod_addr_space omap44xx_emif1_addrs
[] = {
4509 .pa_start
= 0x4c000000,
4510 .pa_end
= 0x4c0000ff,
4511 .flags
= ADDR_TYPE_RT
4516 /* emif_fw -> emif1 */
4517 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1
= {
4518 .master
= &omap44xx_emif_fw_hwmod
,
4519 .slave
= &omap44xx_emif1_hwmod
,
4521 .addr
= omap44xx_emif1_addrs
,
4522 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4525 static struct omap_hwmod_addr_space omap44xx_emif2_addrs
[] = {
4527 .pa_start
= 0x4d000000,
4528 .pa_end
= 0x4d0000ff,
4529 .flags
= ADDR_TYPE_RT
4534 /* emif_fw -> emif2 */
4535 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2
= {
4536 .master
= &omap44xx_emif_fw_hwmod
,
4537 .slave
= &omap44xx_emif2_hwmod
,
4539 .addr
= omap44xx_emif2_addrs
,
4540 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4543 static struct omap_hwmod_addr_space omap44xx_fdif_addrs
[] = {
4545 .pa_start
= 0x4a10a000,
4546 .pa_end
= 0x4a10a1ff,
4547 .flags
= ADDR_TYPE_RT
4552 /* l4_cfg -> fdif */
4553 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif
= {
4554 .master
= &omap44xx_l4_cfg_hwmod
,
4555 .slave
= &omap44xx_fdif_hwmod
,
4557 .addr
= omap44xx_fdif_addrs
,
4558 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4561 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs
[] = {
4563 .pa_start
= 0x4a310000,
4564 .pa_end
= 0x4a3101ff,
4565 .flags
= ADDR_TYPE_RT
4570 /* l4_wkup -> gpio1 */
4571 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1
= {
4572 .master
= &omap44xx_l4_wkup_hwmod
,
4573 .slave
= &omap44xx_gpio1_hwmod
,
4574 .clk
= "l4_wkup_clk_mux_ck",
4575 .addr
= omap44xx_gpio1_addrs
,
4576 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4579 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs
[] = {
4581 .pa_start
= 0x48055000,
4582 .pa_end
= 0x480551ff,
4583 .flags
= ADDR_TYPE_RT
4588 /* l4_per -> gpio2 */
4589 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2
= {
4590 .master
= &omap44xx_l4_per_hwmod
,
4591 .slave
= &omap44xx_gpio2_hwmod
,
4593 .addr
= omap44xx_gpio2_addrs
,
4594 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4597 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs
[] = {
4599 .pa_start
= 0x48057000,
4600 .pa_end
= 0x480571ff,
4601 .flags
= ADDR_TYPE_RT
4606 /* l4_per -> gpio3 */
4607 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3
= {
4608 .master
= &omap44xx_l4_per_hwmod
,
4609 .slave
= &omap44xx_gpio3_hwmod
,
4611 .addr
= omap44xx_gpio3_addrs
,
4612 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4615 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs
[] = {
4617 .pa_start
= 0x48059000,
4618 .pa_end
= 0x480591ff,
4619 .flags
= ADDR_TYPE_RT
4624 /* l4_per -> gpio4 */
4625 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4
= {
4626 .master
= &omap44xx_l4_per_hwmod
,
4627 .slave
= &omap44xx_gpio4_hwmod
,
4629 .addr
= omap44xx_gpio4_addrs
,
4630 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4633 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs
[] = {
4635 .pa_start
= 0x4805b000,
4636 .pa_end
= 0x4805b1ff,
4637 .flags
= ADDR_TYPE_RT
4642 /* l4_per -> gpio5 */
4643 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5
= {
4644 .master
= &omap44xx_l4_per_hwmod
,
4645 .slave
= &omap44xx_gpio5_hwmod
,
4647 .addr
= omap44xx_gpio5_addrs
,
4648 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4651 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs
[] = {
4653 .pa_start
= 0x4805d000,
4654 .pa_end
= 0x4805d1ff,
4655 .flags
= ADDR_TYPE_RT
4660 /* l4_per -> gpio6 */
4661 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6
= {
4662 .master
= &omap44xx_l4_per_hwmod
,
4663 .slave
= &omap44xx_gpio6_hwmod
,
4665 .addr
= omap44xx_gpio6_addrs
,
4666 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4669 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs
[] = {
4671 .pa_start
= 0x50000000,
4672 .pa_end
= 0x500003ff,
4673 .flags
= ADDR_TYPE_RT
4678 /* l3_main_2 -> gpmc */
4679 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc
= {
4680 .master
= &omap44xx_l3_main_2_hwmod
,
4681 .slave
= &omap44xx_gpmc_hwmod
,
4683 .addr
= omap44xx_gpmc_addrs
,
4684 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4687 static struct omap_hwmod_addr_space omap44xx_gpu_addrs
[] = {
4689 .pa_start
= 0x56000000,
4690 .pa_end
= 0x5600ffff,
4691 .flags
= ADDR_TYPE_RT
4696 /* l3_main_2 -> gpu */
4697 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu
= {
4698 .master
= &omap44xx_l3_main_2_hwmod
,
4699 .slave
= &omap44xx_gpu_hwmod
,
4701 .addr
= omap44xx_gpu_addrs
,
4702 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4705 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs
[] = {
4707 .pa_start
= 0x480b2000,
4708 .pa_end
= 0x480b201f,
4709 .flags
= ADDR_TYPE_RT
4714 /* l4_per -> hdq1w */
4715 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w
= {
4716 .master
= &omap44xx_l4_per_hwmod
,
4717 .slave
= &omap44xx_hdq1w_hwmod
,
4719 .addr
= omap44xx_hdq1w_addrs
,
4720 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4723 static struct omap_hwmod_addr_space omap44xx_hsi_addrs
[] = {
4725 .pa_start
= 0x4a058000,
4726 .pa_end
= 0x4a05bfff,
4727 .flags
= ADDR_TYPE_RT
4733 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi
= {
4734 .master
= &omap44xx_l4_cfg_hwmod
,
4735 .slave
= &omap44xx_hsi_hwmod
,
4737 .addr
= omap44xx_hsi_addrs
,
4738 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4741 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs
[] = {
4743 .pa_start
= 0x48070000,
4744 .pa_end
= 0x480700ff,
4745 .flags
= ADDR_TYPE_RT
4750 /* l4_per -> i2c1 */
4751 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1
= {
4752 .master
= &omap44xx_l4_per_hwmod
,
4753 .slave
= &omap44xx_i2c1_hwmod
,
4755 .addr
= omap44xx_i2c1_addrs
,
4756 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4759 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs
[] = {
4761 .pa_start
= 0x48072000,
4762 .pa_end
= 0x480720ff,
4763 .flags
= ADDR_TYPE_RT
4768 /* l4_per -> i2c2 */
4769 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2
= {
4770 .master
= &omap44xx_l4_per_hwmod
,
4771 .slave
= &omap44xx_i2c2_hwmod
,
4773 .addr
= omap44xx_i2c2_addrs
,
4774 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4777 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs
[] = {
4779 .pa_start
= 0x48060000,
4780 .pa_end
= 0x480600ff,
4781 .flags
= ADDR_TYPE_RT
4786 /* l4_per -> i2c3 */
4787 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3
= {
4788 .master
= &omap44xx_l4_per_hwmod
,
4789 .slave
= &omap44xx_i2c3_hwmod
,
4791 .addr
= omap44xx_i2c3_addrs
,
4792 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4795 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs
[] = {
4797 .pa_start
= 0x48350000,
4798 .pa_end
= 0x483500ff,
4799 .flags
= ADDR_TYPE_RT
4804 /* l4_per -> i2c4 */
4805 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4
= {
4806 .master
= &omap44xx_l4_per_hwmod
,
4807 .slave
= &omap44xx_i2c4_hwmod
,
4809 .addr
= omap44xx_i2c4_addrs
,
4810 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4813 /* l3_main_2 -> ipu */
4814 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu
= {
4815 .master
= &omap44xx_l3_main_2_hwmod
,
4816 .slave
= &omap44xx_ipu_hwmod
,
4818 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4821 static struct omap_hwmod_addr_space omap44xx_iss_addrs
[] = {
4823 .pa_start
= 0x52000000,
4824 .pa_end
= 0x520000ff,
4825 .flags
= ADDR_TYPE_RT
4830 /* l3_main_2 -> iss */
4831 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss
= {
4832 .master
= &omap44xx_l3_main_2_hwmod
,
4833 .slave
= &omap44xx_iss_hwmod
,
4835 .addr
= omap44xx_iss_addrs
,
4836 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4840 static struct omap_hwmod_ocp_if omap44xx_iva__sl2if
= {
4841 .master
= &omap44xx_iva_hwmod
,
4842 .slave
= &omap44xx_sl2if_hwmod
,
4843 .clk
= "dpll_iva_m5x2_ck",
4844 .user
= OCP_USER_IVA
,
4847 static struct omap_hwmod_addr_space omap44xx_iva_addrs
[] = {
4849 .pa_start
= 0x5a000000,
4850 .pa_end
= 0x5a07ffff,
4851 .flags
= ADDR_TYPE_RT
4856 /* l3_main_2 -> iva */
4857 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva
= {
4858 .master
= &omap44xx_l3_main_2_hwmod
,
4859 .slave
= &omap44xx_iva_hwmod
,
4861 .addr
= omap44xx_iva_addrs
,
4862 .user
= OCP_USER_MPU
,
4865 static struct omap_hwmod_addr_space omap44xx_kbd_addrs
[] = {
4867 .pa_start
= 0x4a31c000,
4868 .pa_end
= 0x4a31c07f,
4869 .flags
= ADDR_TYPE_RT
4874 /* l4_wkup -> kbd */
4875 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd
= {
4876 .master
= &omap44xx_l4_wkup_hwmod
,
4877 .slave
= &omap44xx_kbd_hwmod
,
4878 .clk
= "l4_wkup_clk_mux_ck",
4879 .addr
= omap44xx_kbd_addrs
,
4880 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4883 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs
[] = {
4885 .pa_start
= 0x4a0f4000,
4886 .pa_end
= 0x4a0f41ff,
4887 .flags
= ADDR_TYPE_RT
4892 /* l4_cfg -> mailbox */
4893 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox
= {
4894 .master
= &omap44xx_l4_cfg_hwmod
,
4895 .slave
= &omap44xx_mailbox_hwmod
,
4897 .addr
= omap44xx_mailbox_addrs
,
4898 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4901 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs
[] = {
4903 .pa_start
= 0x40128000,
4904 .pa_end
= 0x401283ff,
4905 .flags
= ADDR_TYPE_RT
4910 /* l4_abe -> mcasp */
4911 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp
= {
4912 .master
= &omap44xx_l4_abe_hwmod
,
4913 .slave
= &omap44xx_mcasp_hwmod
,
4914 .clk
= "ocp_abe_iclk",
4915 .addr
= omap44xx_mcasp_addrs
,
4916 .user
= OCP_USER_MPU
,
4919 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs
[] = {
4921 .pa_start
= 0x49028000,
4922 .pa_end
= 0x490283ff,
4923 .flags
= ADDR_TYPE_RT
4928 /* l4_abe -> mcasp (dma) */
4929 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma
= {
4930 .master
= &omap44xx_l4_abe_hwmod
,
4931 .slave
= &omap44xx_mcasp_hwmod
,
4932 .clk
= "ocp_abe_iclk",
4933 .addr
= omap44xx_mcasp_dma_addrs
,
4934 .user
= OCP_USER_SDMA
,
4937 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs
[] = {
4940 .pa_start
= 0x40122000,
4941 .pa_end
= 0x401220ff,
4942 .flags
= ADDR_TYPE_RT
4947 /* l4_abe -> mcbsp1 */
4948 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1
= {
4949 .master
= &omap44xx_l4_abe_hwmod
,
4950 .slave
= &omap44xx_mcbsp1_hwmod
,
4951 .clk
= "ocp_abe_iclk",
4952 .addr
= omap44xx_mcbsp1_addrs
,
4953 .user
= OCP_USER_MPU
,
4956 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs
[] = {
4959 .pa_start
= 0x49022000,
4960 .pa_end
= 0x490220ff,
4961 .flags
= ADDR_TYPE_RT
4966 /* l4_abe -> mcbsp1 (dma) */
4967 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma
= {
4968 .master
= &omap44xx_l4_abe_hwmod
,
4969 .slave
= &omap44xx_mcbsp1_hwmod
,
4970 .clk
= "ocp_abe_iclk",
4971 .addr
= omap44xx_mcbsp1_dma_addrs
,
4972 .user
= OCP_USER_SDMA
,
4975 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs
[] = {
4978 .pa_start
= 0x40124000,
4979 .pa_end
= 0x401240ff,
4980 .flags
= ADDR_TYPE_RT
4985 /* l4_abe -> mcbsp2 */
4986 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2
= {
4987 .master
= &omap44xx_l4_abe_hwmod
,
4988 .slave
= &omap44xx_mcbsp2_hwmod
,
4989 .clk
= "ocp_abe_iclk",
4990 .addr
= omap44xx_mcbsp2_addrs
,
4991 .user
= OCP_USER_MPU
,
4994 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs
[] = {
4997 .pa_start
= 0x49024000,
4998 .pa_end
= 0x490240ff,
4999 .flags
= ADDR_TYPE_RT
5004 /* l4_abe -> mcbsp2 (dma) */
5005 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma
= {
5006 .master
= &omap44xx_l4_abe_hwmod
,
5007 .slave
= &omap44xx_mcbsp2_hwmod
,
5008 .clk
= "ocp_abe_iclk",
5009 .addr
= omap44xx_mcbsp2_dma_addrs
,
5010 .user
= OCP_USER_SDMA
,
5013 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs
[] = {
5016 .pa_start
= 0x40126000,
5017 .pa_end
= 0x401260ff,
5018 .flags
= ADDR_TYPE_RT
5023 /* l4_abe -> mcbsp3 */
5024 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3
= {
5025 .master
= &omap44xx_l4_abe_hwmod
,
5026 .slave
= &omap44xx_mcbsp3_hwmod
,
5027 .clk
= "ocp_abe_iclk",
5028 .addr
= omap44xx_mcbsp3_addrs
,
5029 .user
= OCP_USER_MPU
,
5032 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs
[] = {
5035 .pa_start
= 0x49026000,
5036 .pa_end
= 0x490260ff,
5037 .flags
= ADDR_TYPE_RT
5042 /* l4_abe -> mcbsp3 (dma) */
5043 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma
= {
5044 .master
= &omap44xx_l4_abe_hwmod
,
5045 .slave
= &omap44xx_mcbsp3_hwmod
,
5046 .clk
= "ocp_abe_iclk",
5047 .addr
= omap44xx_mcbsp3_dma_addrs
,
5048 .user
= OCP_USER_SDMA
,
5051 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs
[] = {
5053 .pa_start
= 0x48096000,
5054 .pa_end
= 0x480960ff,
5055 .flags
= ADDR_TYPE_RT
5060 /* l4_per -> mcbsp4 */
5061 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4
= {
5062 .master
= &omap44xx_l4_per_hwmod
,
5063 .slave
= &omap44xx_mcbsp4_hwmod
,
5065 .addr
= omap44xx_mcbsp4_addrs
,
5066 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5069 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs
[] = {
5071 .pa_start
= 0x40132000,
5072 .pa_end
= 0x4013207f,
5073 .flags
= ADDR_TYPE_RT
5078 /* l4_abe -> mcpdm */
5079 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm
= {
5080 .master
= &omap44xx_l4_abe_hwmod
,
5081 .slave
= &omap44xx_mcpdm_hwmod
,
5082 .clk
= "ocp_abe_iclk",
5083 .addr
= omap44xx_mcpdm_addrs
,
5084 .user
= OCP_USER_MPU
,
5087 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs
[] = {
5089 .pa_start
= 0x49032000,
5090 .pa_end
= 0x4903207f,
5091 .flags
= ADDR_TYPE_RT
5096 /* l4_abe -> mcpdm (dma) */
5097 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma
= {
5098 .master
= &omap44xx_l4_abe_hwmod
,
5099 .slave
= &omap44xx_mcpdm_hwmod
,
5100 .clk
= "ocp_abe_iclk",
5101 .addr
= omap44xx_mcpdm_dma_addrs
,
5102 .user
= OCP_USER_SDMA
,
5105 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs
[] = {
5107 .pa_start
= 0x48098000,
5108 .pa_end
= 0x480981ff,
5109 .flags
= ADDR_TYPE_RT
5114 /* l4_per -> mcspi1 */
5115 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1
= {
5116 .master
= &omap44xx_l4_per_hwmod
,
5117 .slave
= &omap44xx_mcspi1_hwmod
,
5119 .addr
= omap44xx_mcspi1_addrs
,
5120 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5123 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs
[] = {
5125 .pa_start
= 0x4809a000,
5126 .pa_end
= 0x4809a1ff,
5127 .flags
= ADDR_TYPE_RT
5132 /* l4_per -> mcspi2 */
5133 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2
= {
5134 .master
= &omap44xx_l4_per_hwmod
,
5135 .slave
= &omap44xx_mcspi2_hwmod
,
5137 .addr
= omap44xx_mcspi2_addrs
,
5138 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5141 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs
[] = {
5143 .pa_start
= 0x480b8000,
5144 .pa_end
= 0x480b81ff,
5145 .flags
= ADDR_TYPE_RT
5150 /* l4_per -> mcspi3 */
5151 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3
= {
5152 .master
= &omap44xx_l4_per_hwmod
,
5153 .slave
= &omap44xx_mcspi3_hwmod
,
5155 .addr
= omap44xx_mcspi3_addrs
,
5156 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5159 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs
[] = {
5161 .pa_start
= 0x480ba000,
5162 .pa_end
= 0x480ba1ff,
5163 .flags
= ADDR_TYPE_RT
5168 /* l4_per -> mcspi4 */
5169 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4
= {
5170 .master
= &omap44xx_l4_per_hwmod
,
5171 .slave
= &omap44xx_mcspi4_hwmod
,
5173 .addr
= omap44xx_mcspi4_addrs
,
5174 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5177 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs
[] = {
5179 .pa_start
= 0x4809c000,
5180 .pa_end
= 0x4809c3ff,
5181 .flags
= ADDR_TYPE_RT
5186 /* l4_per -> mmc1 */
5187 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1
= {
5188 .master
= &omap44xx_l4_per_hwmod
,
5189 .slave
= &omap44xx_mmc1_hwmod
,
5191 .addr
= omap44xx_mmc1_addrs
,
5192 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5195 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs
[] = {
5197 .pa_start
= 0x480b4000,
5198 .pa_end
= 0x480b43ff,
5199 .flags
= ADDR_TYPE_RT
5204 /* l4_per -> mmc2 */
5205 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2
= {
5206 .master
= &omap44xx_l4_per_hwmod
,
5207 .slave
= &omap44xx_mmc2_hwmod
,
5209 .addr
= omap44xx_mmc2_addrs
,
5210 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5213 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs
[] = {
5215 .pa_start
= 0x480ad000,
5216 .pa_end
= 0x480ad3ff,
5217 .flags
= ADDR_TYPE_RT
5222 /* l4_per -> mmc3 */
5223 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3
= {
5224 .master
= &omap44xx_l4_per_hwmod
,
5225 .slave
= &omap44xx_mmc3_hwmod
,
5227 .addr
= omap44xx_mmc3_addrs
,
5228 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5231 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs
[] = {
5233 .pa_start
= 0x480d1000,
5234 .pa_end
= 0x480d13ff,
5235 .flags
= ADDR_TYPE_RT
5240 /* l4_per -> mmc4 */
5241 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4
= {
5242 .master
= &omap44xx_l4_per_hwmod
,
5243 .slave
= &omap44xx_mmc4_hwmod
,
5245 .addr
= omap44xx_mmc4_addrs
,
5246 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5249 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs
[] = {
5251 .pa_start
= 0x480d5000,
5252 .pa_end
= 0x480d53ff,
5253 .flags
= ADDR_TYPE_RT
5258 /* l4_per -> mmc5 */
5259 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5
= {
5260 .master
= &omap44xx_l4_per_hwmod
,
5261 .slave
= &omap44xx_mmc5_hwmod
,
5263 .addr
= omap44xx_mmc5_addrs
,
5264 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5267 /* l3_main_2 -> ocmc_ram */
5268 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram
= {
5269 .master
= &omap44xx_l3_main_2_hwmod
,
5270 .slave
= &omap44xx_ocmc_ram_hwmod
,
5272 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5275 /* l4_cfg -> ocp2scp_usb_phy */
5276 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy
= {
5277 .master
= &omap44xx_l4_cfg_hwmod
,
5278 .slave
= &omap44xx_ocp2scp_usb_phy_hwmod
,
5280 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5283 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs
[] = {
5285 .pa_start
= 0x48243000,
5286 .pa_end
= 0x48243fff,
5287 .flags
= ADDR_TYPE_RT
5292 /* mpu_private -> prcm_mpu */
5293 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu
= {
5294 .master
= &omap44xx_mpu_private_hwmod
,
5295 .slave
= &omap44xx_prcm_mpu_hwmod
,
5297 .addr
= omap44xx_prcm_mpu_addrs
,
5298 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5301 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs
[] = {
5303 .pa_start
= 0x4a004000,
5304 .pa_end
= 0x4a004fff,
5305 .flags
= ADDR_TYPE_RT
5310 /* l4_wkup -> cm_core_aon */
5311 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon
= {
5312 .master
= &omap44xx_l4_wkup_hwmod
,
5313 .slave
= &omap44xx_cm_core_aon_hwmod
,
5314 .clk
= "l4_wkup_clk_mux_ck",
5315 .addr
= omap44xx_cm_core_aon_addrs
,
5316 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5319 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs
[] = {
5321 .pa_start
= 0x4a008000,
5322 .pa_end
= 0x4a009fff,
5323 .flags
= ADDR_TYPE_RT
5328 /* l4_cfg -> cm_core */
5329 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core
= {
5330 .master
= &omap44xx_l4_cfg_hwmod
,
5331 .slave
= &omap44xx_cm_core_hwmod
,
5333 .addr
= omap44xx_cm_core_addrs
,
5334 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5337 static struct omap_hwmod_addr_space omap44xx_prm_addrs
[] = {
5339 .pa_start
= 0x4a306000,
5340 .pa_end
= 0x4a307fff,
5341 .flags
= ADDR_TYPE_RT
5346 /* l4_wkup -> prm */
5347 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm
= {
5348 .master
= &omap44xx_l4_wkup_hwmod
,
5349 .slave
= &omap44xx_prm_hwmod
,
5350 .clk
= "l4_wkup_clk_mux_ck",
5351 .addr
= omap44xx_prm_addrs
,
5352 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5355 static struct omap_hwmod_addr_space omap44xx_scrm_addrs
[] = {
5357 .pa_start
= 0x4a30a000,
5358 .pa_end
= 0x4a30a7ff,
5359 .flags
= ADDR_TYPE_RT
5364 /* l4_wkup -> scrm */
5365 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm
= {
5366 .master
= &omap44xx_l4_wkup_hwmod
,
5367 .slave
= &omap44xx_scrm_hwmod
,
5368 .clk
= "l4_wkup_clk_mux_ck",
5369 .addr
= omap44xx_scrm_addrs
,
5370 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5373 /* l3_main_2 -> sl2if */
5374 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if
= {
5375 .master
= &omap44xx_l3_main_2_hwmod
,
5376 .slave
= &omap44xx_sl2if_hwmod
,
5378 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5381 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs
[] = {
5383 .pa_start
= 0x4012c000,
5384 .pa_end
= 0x4012c3ff,
5385 .flags
= ADDR_TYPE_RT
5390 /* l4_abe -> slimbus1 */
5391 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1
= {
5392 .master
= &omap44xx_l4_abe_hwmod
,
5393 .slave
= &omap44xx_slimbus1_hwmod
,
5394 .clk
= "ocp_abe_iclk",
5395 .addr
= omap44xx_slimbus1_addrs
,
5396 .user
= OCP_USER_MPU
,
5399 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs
[] = {
5401 .pa_start
= 0x4902c000,
5402 .pa_end
= 0x4902c3ff,
5403 .flags
= ADDR_TYPE_RT
5408 /* l4_abe -> slimbus1 (dma) */
5409 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma
= {
5410 .master
= &omap44xx_l4_abe_hwmod
,
5411 .slave
= &omap44xx_slimbus1_hwmod
,
5412 .clk
= "ocp_abe_iclk",
5413 .addr
= omap44xx_slimbus1_dma_addrs
,
5414 .user
= OCP_USER_SDMA
,
5417 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs
[] = {
5419 .pa_start
= 0x48076000,
5420 .pa_end
= 0x480763ff,
5421 .flags
= ADDR_TYPE_RT
5426 /* l4_per -> slimbus2 */
5427 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2
= {
5428 .master
= &omap44xx_l4_per_hwmod
,
5429 .slave
= &omap44xx_slimbus2_hwmod
,
5431 .addr
= omap44xx_slimbus2_addrs
,
5432 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5435 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs
[] = {
5437 .pa_start
= 0x4a0dd000,
5438 .pa_end
= 0x4a0dd03f,
5439 .flags
= ADDR_TYPE_RT
5444 /* l4_cfg -> smartreflex_core */
5445 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core
= {
5446 .master
= &omap44xx_l4_cfg_hwmod
,
5447 .slave
= &omap44xx_smartreflex_core_hwmod
,
5449 .addr
= omap44xx_smartreflex_core_addrs
,
5450 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5453 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs
[] = {
5455 .pa_start
= 0x4a0db000,
5456 .pa_end
= 0x4a0db03f,
5457 .flags
= ADDR_TYPE_RT
5462 /* l4_cfg -> smartreflex_iva */
5463 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva
= {
5464 .master
= &omap44xx_l4_cfg_hwmod
,
5465 .slave
= &omap44xx_smartreflex_iva_hwmod
,
5467 .addr
= omap44xx_smartreflex_iva_addrs
,
5468 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5471 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs
[] = {
5473 .pa_start
= 0x4a0d9000,
5474 .pa_end
= 0x4a0d903f,
5475 .flags
= ADDR_TYPE_RT
5480 /* l4_cfg -> smartreflex_mpu */
5481 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu
= {
5482 .master
= &omap44xx_l4_cfg_hwmod
,
5483 .slave
= &omap44xx_smartreflex_mpu_hwmod
,
5485 .addr
= omap44xx_smartreflex_mpu_addrs
,
5486 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5489 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs
[] = {
5491 .pa_start
= 0x4a0f6000,
5492 .pa_end
= 0x4a0f6fff,
5493 .flags
= ADDR_TYPE_RT
5498 /* l4_cfg -> spinlock */
5499 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock
= {
5500 .master
= &omap44xx_l4_cfg_hwmod
,
5501 .slave
= &omap44xx_spinlock_hwmod
,
5503 .addr
= omap44xx_spinlock_addrs
,
5504 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5507 static struct omap_hwmod_addr_space omap44xx_timer1_addrs
[] = {
5509 .pa_start
= 0x4a318000,
5510 .pa_end
= 0x4a31807f,
5511 .flags
= ADDR_TYPE_RT
5516 /* l4_wkup -> timer1 */
5517 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1
= {
5518 .master
= &omap44xx_l4_wkup_hwmod
,
5519 .slave
= &omap44xx_timer1_hwmod
,
5520 .clk
= "l4_wkup_clk_mux_ck",
5521 .addr
= omap44xx_timer1_addrs
,
5522 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5525 static struct omap_hwmod_addr_space omap44xx_timer2_addrs
[] = {
5527 .pa_start
= 0x48032000,
5528 .pa_end
= 0x4803207f,
5529 .flags
= ADDR_TYPE_RT
5534 /* l4_per -> timer2 */
5535 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2
= {
5536 .master
= &omap44xx_l4_per_hwmod
,
5537 .slave
= &omap44xx_timer2_hwmod
,
5539 .addr
= omap44xx_timer2_addrs
,
5540 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5543 static struct omap_hwmod_addr_space omap44xx_timer3_addrs
[] = {
5545 .pa_start
= 0x48034000,
5546 .pa_end
= 0x4803407f,
5547 .flags
= ADDR_TYPE_RT
5552 /* l4_per -> timer3 */
5553 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3
= {
5554 .master
= &omap44xx_l4_per_hwmod
,
5555 .slave
= &omap44xx_timer3_hwmod
,
5557 .addr
= omap44xx_timer3_addrs
,
5558 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5561 static struct omap_hwmod_addr_space omap44xx_timer4_addrs
[] = {
5563 .pa_start
= 0x48036000,
5564 .pa_end
= 0x4803607f,
5565 .flags
= ADDR_TYPE_RT
5570 /* l4_per -> timer4 */
5571 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4
= {
5572 .master
= &omap44xx_l4_per_hwmod
,
5573 .slave
= &omap44xx_timer4_hwmod
,
5575 .addr
= omap44xx_timer4_addrs
,
5576 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5579 static struct omap_hwmod_addr_space omap44xx_timer5_addrs
[] = {
5581 .pa_start
= 0x40138000,
5582 .pa_end
= 0x4013807f,
5583 .flags
= ADDR_TYPE_RT
5588 /* l4_abe -> timer5 */
5589 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5
= {
5590 .master
= &omap44xx_l4_abe_hwmod
,
5591 .slave
= &omap44xx_timer5_hwmod
,
5592 .clk
= "ocp_abe_iclk",
5593 .addr
= omap44xx_timer5_addrs
,
5594 .user
= OCP_USER_MPU
,
5597 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs
[] = {
5599 .pa_start
= 0x49038000,
5600 .pa_end
= 0x4903807f,
5601 .flags
= ADDR_TYPE_RT
5606 /* l4_abe -> timer5 (dma) */
5607 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma
= {
5608 .master
= &omap44xx_l4_abe_hwmod
,
5609 .slave
= &omap44xx_timer5_hwmod
,
5610 .clk
= "ocp_abe_iclk",
5611 .addr
= omap44xx_timer5_dma_addrs
,
5612 .user
= OCP_USER_SDMA
,
5615 static struct omap_hwmod_addr_space omap44xx_timer6_addrs
[] = {
5617 .pa_start
= 0x4013a000,
5618 .pa_end
= 0x4013a07f,
5619 .flags
= ADDR_TYPE_RT
5624 /* l4_abe -> timer6 */
5625 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6
= {
5626 .master
= &omap44xx_l4_abe_hwmod
,
5627 .slave
= &omap44xx_timer6_hwmod
,
5628 .clk
= "ocp_abe_iclk",
5629 .addr
= omap44xx_timer6_addrs
,
5630 .user
= OCP_USER_MPU
,
5633 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs
[] = {
5635 .pa_start
= 0x4903a000,
5636 .pa_end
= 0x4903a07f,
5637 .flags
= ADDR_TYPE_RT
5642 /* l4_abe -> timer6 (dma) */
5643 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma
= {
5644 .master
= &omap44xx_l4_abe_hwmod
,
5645 .slave
= &omap44xx_timer6_hwmod
,
5646 .clk
= "ocp_abe_iclk",
5647 .addr
= omap44xx_timer6_dma_addrs
,
5648 .user
= OCP_USER_SDMA
,
5651 static struct omap_hwmod_addr_space omap44xx_timer7_addrs
[] = {
5653 .pa_start
= 0x4013c000,
5654 .pa_end
= 0x4013c07f,
5655 .flags
= ADDR_TYPE_RT
5660 /* l4_abe -> timer7 */
5661 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7
= {
5662 .master
= &omap44xx_l4_abe_hwmod
,
5663 .slave
= &omap44xx_timer7_hwmod
,
5664 .clk
= "ocp_abe_iclk",
5665 .addr
= omap44xx_timer7_addrs
,
5666 .user
= OCP_USER_MPU
,
5669 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs
[] = {
5671 .pa_start
= 0x4903c000,
5672 .pa_end
= 0x4903c07f,
5673 .flags
= ADDR_TYPE_RT
5678 /* l4_abe -> timer7 (dma) */
5679 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma
= {
5680 .master
= &omap44xx_l4_abe_hwmod
,
5681 .slave
= &omap44xx_timer7_hwmod
,
5682 .clk
= "ocp_abe_iclk",
5683 .addr
= omap44xx_timer7_dma_addrs
,
5684 .user
= OCP_USER_SDMA
,
5687 static struct omap_hwmod_addr_space omap44xx_timer8_addrs
[] = {
5689 .pa_start
= 0x4013e000,
5690 .pa_end
= 0x4013e07f,
5691 .flags
= ADDR_TYPE_RT
5696 /* l4_abe -> timer8 */
5697 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8
= {
5698 .master
= &omap44xx_l4_abe_hwmod
,
5699 .slave
= &omap44xx_timer8_hwmod
,
5700 .clk
= "ocp_abe_iclk",
5701 .addr
= omap44xx_timer8_addrs
,
5702 .user
= OCP_USER_MPU
,
5705 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs
[] = {
5707 .pa_start
= 0x4903e000,
5708 .pa_end
= 0x4903e07f,
5709 .flags
= ADDR_TYPE_RT
5714 /* l4_abe -> timer8 (dma) */
5715 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma
= {
5716 .master
= &omap44xx_l4_abe_hwmod
,
5717 .slave
= &omap44xx_timer8_hwmod
,
5718 .clk
= "ocp_abe_iclk",
5719 .addr
= omap44xx_timer8_dma_addrs
,
5720 .user
= OCP_USER_SDMA
,
5723 static struct omap_hwmod_addr_space omap44xx_timer9_addrs
[] = {
5725 .pa_start
= 0x4803e000,
5726 .pa_end
= 0x4803e07f,
5727 .flags
= ADDR_TYPE_RT
5732 /* l4_per -> timer9 */
5733 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9
= {
5734 .master
= &omap44xx_l4_per_hwmod
,
5735 .slave
= &omap44xx_timer9_hwmod
,
5737 .addr
= omap44xx_timer9_addrs
,
5738 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5741 static struct omap_hwmod_addr_space omap44xx_timer10_addrs
[] = {
5743 .pa_start
= 0x48086000,
5744 .pa_end
= 0x4808607f,
5745 .flags
= ADDR_TYPE_RT
5750 /* l4_per -> timer10 */
5751 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10
= {
5752 .master
= &omap44xx_l4_per_hwmod
,
5753 .slave
= &omap44xx_timer10_hwmod
,
5755 .addr
= omap44xx_timer10_addrs
,
5756 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5759 static struct omap_hwmod_addr_space omap44xx_timer11_addrs
[] = {
5761 .pa_start
= 0x48088000,
5762 .pa_end
= 0x4808807f,
5763 .flags
= ADDR_TYPE_RT
5768 /* l4_per -> timer11 */
5769 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11
= {
5770 .master
= &omap44xx_l4_per_hwmod
,
5771 .slave
= &omap44xx_timer11_hwmod
,
5773 .addr
= omap44xx_timer11_addrs
,
5774 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5777 static struct omap_hwmod_addr_space omap44xx_uart1_addrs
[] = {
5779 .pa_start
= 0x4806a000,
5780 .pa_end
= 0x4806a0ff,
5781 .flags
= ADDR_TYPE_RT
5786 /* l4_per -> uart1 */
5787 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1
= {
5788 .master
= &omap44xx_l4_per_hwmod
,
5789 .slave
= &omap44xx_uart1_hwmod
,
5791 .addr
= omap44xx_uart1_addrs
,
5792 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5795 static struct omap_hwmod_addr_space omap44xx_uart2_addrs
[] = {
5797 .pa_start
= 0x4806c000,
5798 .pa_end
= 0x4806c0ff,
5799 .flags
= ADDR_TYPE_RT
5804 /* l4_per -> uart2 */
5805 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2
= {
5806 .master
= &omap44xx_l4_per_hwmod
,
5807 .slave
= &omap44xx_uart2_hwmod
,
5809 .addr
= omap44xx_uart2_addrs
,
5810 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5813 static struct omap_hwmod_addr_space omap44xx_uart3_addrs
[] = {
5815 .pa_start
= 0x48020000,
5816 .pa_end
= 0x480200ff,
5817 .flags
= ADDR_TYPE_RT
5822 /* l4_per -> uart3 */
5823 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3
= {
5824 .master
= &omap44xx_l4_per_hwmod
,
5825 .slave
= &omap44xx_uart3_hwmod
,
5827 .addr
= omap44xx_uart3_addrs
,
5828 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5831 static struct omap_hwmod_addr_space omap44xx_uart4_addrs
[] = {
5833 .pa_start
= 0x4806e000,
5834 .pa_end
= 0x4806e0ff,
5835 .flags
= ADDR_TYPE_RT
5840 /* l4_per -> uart4 */
5841 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4
= {
5842 .master
= &omap44xx_l4_per_hwmod
,
5843 .slave
= &omap44xx_uart4_hwmod
,
5845 .addr
= omap44xx_uart4_addrs
,
5846 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5849 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs
[] = {
5851 .pa_start
= 0x4a0a9000,
5852 .pa_end
= 0x4a0a93ff,
5853 .flags
= ADDR_TYPE_RT
5858 /* l4_cfg -> usb_host_fs */
5859 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs
= {
5860 .master
= &omap44xx_l4_cfg_hwmod
,
5861 .slave
= &omap44xx_usb_host_fs_hwmod
,
5863 .addr
= omap44xx_usb_host_fs_addrs
,
5864 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5867 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs
[] = {
5870 .pa_start
= 0x4a064000,
5871 .pa_end
= 0x4a0647ff,
5872 .flags
= ADDR_TYPE_RT
5876 .pa_start
= 0x4a064800,
5877 .pa_end
= 0x4a064bff,
5881 .pa_start
= 0x4a064c00,
5882 .pa_end
= 0x4a064fff,
5887 /* l4_cfg -> usb_host_hs */
5888 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs
= {
5889 .master
= &omap44xx_l4_cfg_hwmod
,
5890 .slave
= &omap44xx_usb_host_hs_hwmod
,
5892 .addr
= omap44xx_usb_host_hs_addrs
,
5893 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5896 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs
[] = {
5898 .pa_start
= 0x4a0ab000,
5899 .pa_end
= 0x4a0ab003,
5900 .flags
= ADDR_TYPE_RT
5905 /* l4_cfg -> usb_otg_hs */
5906 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs
= {
5907 .master
= &omap44xx_l4_cfg_hwmod
,
5908 .slave
= &omap44xx_usb_otg_hs_hwmod
,
5910 .addr
= omap44xx_usb_otg_hs_addrs
,
5911 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5914 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs
[] = {
5917 .pa_start
= 0x4a062000,
5918 .pa_end
= 0x4a063fff,
5919 .flags
= ADDR_TYPE_RT
5924 /* l4_cfg -> usb_tll_hs */
5925 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs
= {
5926 .master
= &omap44xx_l4_cfg_hwmod
,
5927 .slave
= &omap44xx_usb_tll_hs_hwmod
,
5929 .addr
= omap44xx_usb_tll_hs_addrs
,
5930 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5933 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs
[] = {
5935 .pa_start
= 0x4a314000,
5936 .pa_end
= 0x4a31407f,
5937 .flags
= ADDR_TYPE_RT
5942 /* l4_wkup -> wd_timer2 */
5943 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2
= {
5944 .master
= &omap44xx_l4_wkup_hwmod
,
5945 .slave
= &omap44xx_wd_timer2_hwmod
,
5946 .clk
= "l4_wkup_clk_mux_ck",
5947 .addr
= omap44xx_wd_timer2_addrs
,
5948 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5951 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs
[] = {
5953 .pa_start
= 0x40130000,
5954 .pa_end
= 0x4013007f,
5955 .flags
= ADDR_TYPE_RT
5960 /* l4_abe -> wd_timer3 */
5961 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3
= {
5962 .master
= &omap44xx_l4_abe_hwmod
,
5963 .slave
= &omap44xx_wd_timer3_hwmod
,
5964 .clk
= "ocp_abe_iclk",
5965 .addr
= omap44xx_wd_timer3_addrs
,
5966 .user
= OCP_USER_MPU
,
5969 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs
[] = {
5971 .pa_start
= 0x49030000,
5972 .pa_end
= 0x4903007f,
5973 .flags
= ADDR_TYPE_RT
5978 /* l4_abe -> wd_timer3 (dma) */
5979 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma
= {
5980 .master
= &omap44xx_l4_abe_hwmod
,
5981 .slave
= &omap44xx_wd_timer3_hwmod
,
5982 .clk
= "ocp_abe_iclk",
5983 .addr
= omap44xx_wd_timer3_dma_addrs
,
5984 .user
= OCP_USER_SDMA
,
5987 static struct omap_hwmod_ocp_if
*omap44xx_hwmod_ocp_ifs
[] __initdata
= {
5988 &omap44xx_c2c__c2c_target_fw
,
5989 &omap44xx_l4_cfg__c2c_target_fw
,
5990 &omap44xx_l3_main_1__dmm
,
5992 &omap44xx_c2c__emif_fw
,
5993 &omap44xx_dmm__emif_fw
,
5994 &omap44xx_l4_cfg__emif_fw
,
5995 &omap44xx_iva__l3_instr
,
5996 &omap44xx_l3_main_3__l3_instr
,
5997 &omap44xx_ocp_wp_noc__l3_instr
,
5998 &omap44xx_dsp__l3_main_1
,
5999 &omap44xx_dss__l3_main_1
,
6000 &omap44xx_l3_main_2__l3_main_1
,
6001 &omap44xx_l4_cfg__l3_main_1
,
6002 &omap44xx_mmc1__l3_main_1
,
6003 &omap44xx_mmc2__l3_main_1
,
6004 &omap44xx_mpu__l3_main_1
,
6005 &omap44xx_c2c_target_fw__l3_main_2
,
6006 &omap44xx_debugss__l3_main_2
,
6007 &omap44xx_dma_system__l3_main_2
,
6008 &omap44xx_fdif__l3_main_2
,
6009 &omap44xx_gpu__l3_main_2
,
6010 &omap44xx_hsi__l3_main_2
,
6011 &omap44xx_ipu__l3_main_2
,
6012 &omap44xx_iss__l3_main_2
,
6013 &omap44xx_iva__l3_main_2
,
6014 &omap44xx_l3_main_1__l3_main_2
,
6015 &omap44xx_l4_cfg__l3_main_2
,
6016 &omap44xx_usb_host_fs__l3_main_2
,
6017 &omap44xx_usb_host_hs__l3_main_2
,
6018 &omap44xx_usb_otg_hs__l3_main_2
,
6019 &omap44xx_l3_main_1__l3_main_3
,
6020 &omap44xx_l3_main_2__l3_main_3
,
6021 &omap44xx_l4_cfg__l3_main_3
,
6022 &omap44xx_aess__l4_abe
,
6023 &omap44xx_dsp__l4_abe
,
6024 &omap44xx_l3_main_1__l4_abe
,
6025 &omap44xx_mpu__l4_abe
,
6026 &omap44xx_l3_main_1__l4_cfg
,
6027 &omap44xx_l3_main_2__l4_per
,
6028 &omap44xx_l4_cfg__l4_wkup
,
6029 &omap44xx_mpu__mpu_private
,
6030 &omap44xx_l4_cfg__ocp_wp_noc
,
6031 &omap44xx_l4_abe__aess
,
6032 &omap44xx_l4_abe__aess_dma
,
6033 &omap44xx_l3_main_2__c2c
,
6034 &omap44xx_l4_wkup__counter_32k
,
6035 &omap44xx_l4_cfg__ctrl_module_core
,
6036 &omap44xx_l4_cfg__ctrl_module_pad_core
,
6037 &omap44xx_l4_wkup__ctrl_module_wkup
,
6038 &omap44xx_l4_wkup__ctrl_module_pad_wkup
,
6039 &omap44xx_l3_instr__debugss
,
6040 &omap44xx_l4_cfg__dma_system
,
6041 &omap44xx_l4_abe__dmic
,
6042 &omap44xx_l4_abe__dmic_dma
,
6044 &omap44xx_dsp__sl2if
,
6045 &omap44xx_l4_cfg__dsp
,
6046 &omap44xx_l3_main_2__dss
,
6047 &omap44xx_l4_per__dss
,
6048 &omap44xx_l3_main_2__dss_dispc
,
6049 &omap44xx_l4_per__dss_dispc
,
6050 &omap44xx_l3_main_2__dss_dsi1
,
6051 &omap44xx_l4_per__dss_dsi1
,
6052 &omap44xx_l3_main_2__dss_dsi2
,
6053 &omap44xx_l4_per__dss_dsi2
,
6054 &omap44xx_l3_main_2__dss_hdmi
,
6055 &omap44xx_l4_per__dss_hdmi
,
6056 &omap44xx_l3_main_2__dss_rfbi
,
6057 &omap44xx_l4_per__dss_rfbi
,
6058 &omap44xx_l3_main_2__dss_venc
,
6059 &omap44xx_l4_per__dss_venc
,
6060 &omap44xx_l4_per__elm
,
6061 &omap44xx_emif_fw__emif1
,
6062 &omap44xx_emif_fw__emif2
,
6063 &omap44xx_l4_cfg__fdif
,
6064 &omap44xx_l4_wkup__gpio1
,
6065 &omap44xx_l4_per__gpio2
,
6066 &omap44xx_l4_per__gpio3
,
6067 &omap44xx_l4_per__gpio4
,
6068 &omap44xx_l4_per__gpio5
,
6069 &omap44xx_l4_per__gpio6
,
6070 &omap44xx_l3_main_2__gpmc
,
6071 &omap44xx_l3_main_2__gpu
,
6072 &omap44xx_l4_per__hdq1w
,
6073 &omap44xx_l4_cfg__hsi
,
6074 &omap44xx_l4_per__i2c1
,
6075 &omap44xx_l4_per__i2c2
,
6076 &omap44xx_l4_per__i2c3
,
6077 &omap44xx_l4_per__i2c4
,
6078 &omap44xx_l3_main_2__ipu
,
6079 &omap44xx_l3_main_2__iss
,
6080 &omap44xx_iva__sl2if
,
6081 &omap44xx_l3_main_2__iva
,
6082 &omap44xx_l4_wkup__kbd
,
6083 &omap44xx_l4_cfg__mailbox
,
6084 &omap44xx_l4_abe__mcasp
,
6085 &omap44xx_l4_abe__mcasp_dma
,
6086 &omap44xx_l4_abe__mcbsp1
,
6087 &omap44xx_l4_abe__mcbsp1_dma
,
6088 &omap44xx_l4_abe__mcbsp2
,
6089 &omap44xx_l4_abe__mcbsp2_dma
,
6090 &omap44xx_l4_abe__mcbsp3
,
6091 &omap44xx_l4_abe__mcbsp3_dma
,
6092 &omap44xx_l4_per__mcbsp4
,
6093 &omap44xx_l4_abe__mcpdm
,
6094 &omap44xx_l4_abe__mcpdm_dma
,
6095 &omap44xx_l4_per__mcspi1
,
6096 &omap44xx_l4_per__mcspi2
,
6097 &omap44xx_l4_per__mcspi3
,
6098 &omap44xx_l4_per__mcspi4
,
6099 &omap44xx_l4_per__mmc1
,
6100 &omap44xx_l4_per__mmc2
,
6101 &omap44xx_l4_per__mmc3
,
6102 &omap44xx_l4_per__mmc4
,
6103 &omap44xx_l4_per__mmc5
,
6104 &omap44xx_l3_main_2__ocmc_ram
,
6105 &omap44xx_l4_cfg__ocp2scp_usb_phy
,
6106 &omap44xx_mpu_private__prcm_mpu
,
6107 &omap44xx_l4_wkup__cm_core_aon
,
6108 &omap44xx_l4_cfg__cm_core
,
6109 &omap44xx_l4_wkup__prm
,
6110 &omap44xx_l4_wkup__scrm
,
6111 &omap44xx_l3_main_2__sl2if
,
6112 &omap44xx_l4_abe__slimbus1
,
6113 &omap44xx_l4_abe__slimbus1_dma
,
6114 &omap44xx_l4_per__slimbus2
,
6115 &omap44xx_l4_cfg__smartreflex_core
,
6116 &omap44xx_l4_cfg__smartreflex_iva
,
6117 &omap44xx_l4_cfg__smartreflex_mpu
,
6118 &omap44xx_l4_cfg__spinlock
,
6119 &omap44xx_l4_wkup__timer1
,
6120 &omap44xx_l4_per__timer2
,
6121 &omap44xx_l4_per__timer3
,
6122 &omap44xx_l4_per__timer4
,
6123 &omap44xx_l4_abe__timer5
,
6124 &omap44xx_l4_abe__timer5_dma
,
6125 &omap44xx_l4_abe__timer6
,
6126 &omap44xx_l4_abe__timer6_dma
,
6127 &omap44xx_l4_abe__timer7
,
6128 &omap44xx_l4_abe__timer7_dma
,
6129 &omap44xx_l4_abe__timer8
,
6130 &omap44xx_l4_abe__timer8_dma
,
6131 &omap44xx_l4_per__timer9
,
6132 &omap44xx_l4_per__timer10
,
6133 &omap44xx_l4_per__timer11
,
6134 &omap44xx_l4_per__uart1
,
6135 &omap44xx_l4_per__uart2
,
6136 &omap44xx_l4_per__uart3
,
6137 &omap44xx_l4_per__uart4
,
6138 &omap44xx_l4_cfg__usb_host_fs
,
6139 &omap44xx_l4_cfg__usb_host_hs
,
6140 &omap44xx_l4_cfg__usb_otg_hs
,
6141 &omap44xx_l4_cfg__usb_tll_hs
,
6142 &omap44xx_l4_wkup__wd_timer2
,
6143 &omap44xx_l4_abe__wd_timer3
,
6144 &omap44xx_l4_abe__wd_timer3_dma
,
6148 int __init
omap44xx_hwmod_init(void)
6150 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs
);