2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
23 #include <plat/omap_hwmod.h>
26 #include <plat/gpio.h>
28 #include <plat/mcspi.h>
29 #include <plat/mcbsp.h>
31 #include <plat/dmtimer.h>
32 #include <plat/common.h>
34 #include "omap_hwmod_common_data.h"
36 #include "smartreflex.h"
40 #include "prm-regbits-44xx.h"
43 /* Base offset for all OMAP4 interrupts external to MPUSS */
44 #define OMAP44XX_IRQ_GIC_START 32
46 /* Base offset for all OMAP4 dma requests */
47 #define OMAP44XX_DMA_REQ_START 1
57 static struct omap_hwmod_class omap44xx_dmm_hwmod_class
= {
62 static struct omap_hwmod_irq_info omap44xx_dmm_irqs
[] = {
63 { .irq
= 113 + OMAP44XX_IRQ_GIC_START
},
67 static struct omap_hwmod omap44xx_dmm_hwmod
= {
69 .class = &omap44xx_dmm_hwmod_class
,
70 .clkdm_name
= "l3_emif_clkdm",
71 .mpu_irqs
= omap44xx_dmm_irqs
,
74 .clkctrl_offs
= OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET
,
75 .context_offs
= OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET
,
82 * instance(s): emif_fw
84 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class
= {
89 static struct omap_hwmod omap44xx_emif_fw_hwmod
= {
91 .class = &omap44xx_emif_fw_hwmod_class
,
92 .clkdm_name
= "l3_emif_clkdm",
95 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET
,
96 .context_offs
= OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET
,
103 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
105 static struct omap_hwmod_class omap44xx_l3_hwmod_class
= {
110 static struct omap_hwmod omap44xx_l3_instr_hwmod
= {
112 .class = &omap44xx_l3_hwmod_class
,
113 .clkdm_name
= "l3_instr_clkdm",
116 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
,
117 .context_offs
= OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
,
118 .modulemode
= MODULEMODE_HWCTRL
,
124 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs
[] = {
125 { .name
= "dbg_err", .irq
= 9 + OMAP44XX_IRQ_GIC_START
},
126 { .name
= "app_err", .irq
= 10 + OMAP44XX_IRQ_GIC_START
},
130 static struct omap_hwmod omap44xx_l3_main_1_hwmod
= {
132 .class = &omap44xx_l3_hwmod_class
,
133 .clkdm_name
= "l3_1_clkdm",
134 .mpu_irqs
= omap44xx_l3_main_1_irqs
,
137 .clkctrl_offs
= OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET
,
138 .context_offs
= OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET
,
144 static struct omap_hwmod omap44xx_l3_main_2_hwmod
= {
146 .class = &omap44xx_l3_hwmod_class
,
147 .clkdm_name
= "l3_2_clkdm",
150 .clkctrl_offs
= OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET
,
151 .context_offs
= OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET
,
157 static struct omap_hwmod omap44xx_l3_main_3_hwmod
= {
159 .class = &omap44xx_l3_hwmod_class
,
160 .clkdm_name
= "l3_instr_clkdm",
163 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET
,
164 .context_offs
= OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET
,
165 .modulemode
= MODULEMODE_HWCTRL
,
172 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
174 static struct omap_hwmod_class omap44xx_l4_hwmod_class
= {
179 static struct omap_hwmod omap44xx_l4_abe_hwmod
= {
181 .class = &omap44xx_l4_hwmod_class
,
182 .clkdm_name
= "abe_clkdm",
185 .clkctrl_offs
= OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET
,
191 static struct omap_hwmod omap44xx_l4_cfg_hwmod
= {
193 .class = &omap44xx_l4_hwmod_class
,
194 .clkdm_name
= "l4_cfg_clkdm",
197 .clkctrl_offs
= OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
,
198 .context_offs
= OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
,
204 static struct omap_hwmod omap44xx_l4_per_hwmod
= {
206 .class = &omap44xx_l4_hwmod_class
,
207 .clkdm_name
= "l4_per_clkdm",
210 .clkctrl_offs
= OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET
,
211 .context_offs
= OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET
,
217 static struct omap_hwmod omap44xx_l4_wkup_hwmod
= {
219 .class = &omap44xx_l4_hwmod_class
,
220 .clkdm_name
= "l4_wkup_clkdm",
223 .clkctrl_offs
= OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
,
224 .context_offs
= OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET
,
231 * instance(s): mpu_private
233 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class
= {
238 static struct omap_hwmod omap44xx_mpu_private_hwmod
= {
239 .name
= "mpu_private",
240 .class = &omap44xx_mpu_bus_hwmod_class
,
241 .clkdm_name
= "mpuss_clkdm",
245 * Modules omap_hwmod structures
247 * The following IPs are excluded for the moment because:
248 * - They do not need an explicit SW control using omap_hwmod API.
249 * - They still need to be validated with the driver
250 * properly adapted to omap_hwmod / omap_device
257 * ctrl_module_pad_core
258 * ctrl_module_pad_wkup
288 * audio engine sub system
291 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc
= {
294 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
295 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
296 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
|
297 MSTANDBY_SMART_WKUP
),
298 .sysc_fields
= &omap_hwmod_sysc_type2
,
301 static struct omap_hwmod_class omap44xx_aess_hwmod_class
= {
303 .sysc
= &omap44xx_aess_sysc
,
307 static struct omap_hwmod_irq_info omap44xx_aess_irqs
[] = {
308 { .irq
= 99 + OMAP44XX_IRQ_GIC_START
},
312 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs
[] = {
313 { .name
= "fifo0", .dma_req
= 100 + OMAP44XX_DMA_REQ_START
},
314 { .name
= "fifo1", .dma_req
= 101 + OMAP44XX_DMA_REQ_START
},
315 { .name
= "fifo2", .dma_req
= 102 + OMAP44XX_DMA_REQ_START
},
316 { .name
= "fifo3", .dma_req
= 103 + OMAP44XX_DMA_REQ_START
},
317 { .name
= "fifo4", .dma_req
= 104 + OMAP44XX_DMA_REQ_START
},
318 { .name
= "fifo5", .dma_req
= 105 + OMAP44XX_DMA_REQ_START
},
319 { .name
= "fifo6", .dma_req
= 106 + OMAP44XX_DMA_REQ_START
},
320 { .name
= "fifo7", .dma_req
= 107 + OMAP44XX_DMA_REQ_START
},
324 static struct omap_hwmod omap44xx_aess_hwmod
= {
326 .class = &omap44xx_aess_hwmod_class
,
327 .clkdm_name
= "abe_clkdm",
328 .mpu_irqs
= omap44xx_aess_irqs
,
329 .sdma_reqs
= omap44xx_aess_sdma_reqs
,
330 .main_clk
= "aess_fck",
333 .clkctrl_offs
= OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET
,
334 .context_offs
= OMAP4_RM_ABE_AESS_CONTEXT_OFFSET
,
335 .modulemode
= MODULEMODE_SWCTRL
,
342 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
345 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc
= {
348 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
349 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
351 .sysc_fields
= &omap_hwmod_sysc_type1
,
354 static struct omap_hwmod_class omap44xx_counter_hwmod_class
= {
356 .sysc
= &omap44xx_counter_sysc
,
360 static struct omap_hwmod omap44xx_counter_32k_hwmod
= {
361 .name
= "counter_32k",
362 .class = &omap44xx_counter_hwmod_class
,
363 .clkdm_name
= "l4_wkup_clkdm",
364 .flags
= HWMOD_SWSUP_SIDLE
,
365 .main_clk
= "sys_32k_ck",
368 .clkctrl_offs
= OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET
,
369 .context_offs
= OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET
,
376 * dma controller for data exchange between memory to memory (i.e. internal or
377 * external memory) and gp peripherals to memory or memory to gp peripherals
380 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc
= {
384 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
385 SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
386 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
387 SYSS_HAS_RESET_STATUS
),
388 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
389 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
390 .sysc_fields
= &omap_hwmod_sysc_type1
,
393 static struct omap_hwmod_class omap44xx_dma_hwmod_class
= {
395 .sysc
= &omap44xx_dma_sysc
,
399 static struct omap_dma_dev_attr dma_dev_attr
= {
400 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
401 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
406 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs
[] = {
407 { .name
= "0", .irq
= 12 + OMAP44XX_IRQ_GIC_START
},
408 { .name
= "1", .irq
= 13 + OMAP44XX_IRQ_GIC_START
},
409 { .name
= "2", .irq
= 14 + OMAP44XX_IRQ_GIC_START
},
410 { .name
= "3", .irq
= 15 + OMAP44XX_IRQ_GIC_START
},
414 static struct omap_hwmod omap44xx_dma_system_hwmod
= {
415 .name
= "dma_system",
416 .class = &omap44xx_dma_hwmod_class
,
417 .clkdm_name
= "l3_dma_clkdm",
418 .mpu_irqs
= omap44xx_dma_system_irqs
,
419 .main_clk
= "l3_div_ck",
422 .clkctrl_offs
= OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET
,
423 .context_offs
= OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET
,
426 .dev_attr
= &dma_dev_attr
,
431 * digital microphone controller
434 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc
= {
437 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
438 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
439 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
441 .sysc_fields
= &omap_hwmod_sysc_type2
,
444 static struct omap_hwmod_class omap44xx_dmic_hwmod_class
= {
446 .sysc
= &omap44xx_dmic_sysc
,
450 static struct omap_hwmod_irq_info omap44xx_dmic_irqs
[] = {
451 { .irq
= 114 + OMAP44XX_IRQ_GIC_START
},
455 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs
[] = {
456 { .dma_req
= 66 + OMAP44XX_DMA_REQ_START
},
460 static struct omap_hwmod omap44xx_dmic_hwmod
= {
462 .class = &omap44xx_dmic_hwmod_class
,
463 .clkdm_name
= "abe_clkdm",
464 .mpu_irqs
= omap44xx_dmic_irqs
,
465 .sdma_reqs
= omap44xx_dmic_sdma_reqs
,
466 .main_clk
= "dmic_fck",
469 .clkctrl_offs
= OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET
,
470 .context_offs
= OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET
,
471 .modulemode
= MODULEMODE_SWCTRL
,
481 static struct omap_hwmod_class omap44xx_dsp_hwmod_class
= {
486 static struct omap_hwmod_irq_info omap44xx_dsp_irqs
[] = {
487 { .irq
= 28 + OMAP44XX_IRQ_GIC_START
},
491 static struct omap_hwmod_rst_info omap44xx_dsp_resets
[] = {
492 { .name
= "dsp", .rst_shift
= 0 },
493 { .name
= "mmu_cache", .rst_shift
= 1 },
496 static struct omap_hwmod omap44xx_dsp_hwmod
= {
498 .class = &omap44xx_dsp_hwmod_class
,
499 .clkdm_name
= "tesla_clkdm",
500 .mpu_irqs
= omap44xx_dsp_irqs
,
501 .rst_lines
= omap44xx_dsp_resets
,
502 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_dsp_resets
),
503 .main_clk
= "dsp_fck",
506 .clkctrl_offs
= OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET
,
507 .rstctrl_offs
= OMAP4_RM_TESLA_RSTCTRL_OFFSET
,
508 .context_offs
= OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET
,
509 .modulemode
= MODULEMODE_HWCTRL
,
519 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc
= {
522 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
525 static struct omap_hwmod_class omap44xx_dss_hwmod_class
= {
527 .sysc
= &omap44xx_dss_sysc
,
528 .reset
= omap_dss_reset
,
532 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
533 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
534 { .role
= "tv_clk", .clk
= "dss_tv_clk" },
535 { .role
= "hdmi_clk", .clk
= "dss_48mhz_clk" },
538 static struct omap_hwmod omap44xx_dss_hwmod
= {
540 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
541 .class = &omap44xx_dss_hwmod_class
,
542 .clkdm_name
= "l3_dss_clkdm",
543 .main_clk
= "dss_dss_clk",
546 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
547 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
550 .opt_clks
= dss_opt_clks
,
551 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
559 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc
= {
563 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
564 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_MIDLEMODE
|
565 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
566 SYSS_HAS_RESET_STATUS
),
567 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
568 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
569 .sysc_fields
= &omap_hwmod_sysc_type1
,
572 static struct omap_hwmod_class omap44xx_dispc_hwmod_class
= {
574 .sysc
= &omap44xx_dispc_sysc
,
578 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs
[] = {
579 { .irq
= 25 + OMAP44XX_IRQ_GIC_START
},
583 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs
[] = {
584 { .dma_req
= 5 + OMAP44XX_DMA_REQ_START
},
588 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr
= {
590 .has_framedonetv_irq
= 1
593 static struct omap_hwmod omap44xx_dss_dispc_hwmod
= {
595 .class = &omap44xx_dispc_hwmod_class
,
596 .clkdm_name
= "l3_dss_clkdm",
597 .mpu_irqs
= omap44xx_dss_dispc_irqs
,
598 .sdma_reqs
= omap44xx_dss_dispc_sdma_reqs
,
599 .main_clk
= "dss_dss_clk",
602 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
603 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
606 .dev_attr
= &omap44xx_dss_dispc_dev_attr
611 * display serial interface controller
614 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc
= {
618 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
619 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
620 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
621 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
622 .sysc_fields
= &omap_hwmod_sysc_type1
,
625 static struct omap_hwmod_class omap44xx_dsi_hwmod_class
= {
627 .sysc
= &omap44xx_dsi_sysc
,
631 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs
[] = {
632 { .irq
= 53 + OMAP44XX_IRQ_GIC_START
},
636 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs
[] = {
637 { .dma_req
= 74 + OMAP44XX_DMA_REQ_START
},
641 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks
[] = {
642 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
645 static struct omap_hwmod omap44xx_dss_dsi1_hwmod
= {
647 .class = &omap44xx_dsi_hwmod_class
,
648 .clkdm_name
= "l3_dss_clkdm",
649 .mpu_irqs
= omap44xx_dss_dsi1_irqs
,
650 .sdma_reqs
= omap44xx_dss_dsi1_sdma_reqs
,
651 .main_clk
= "dss_dss_clk",
654 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
655 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
658 .opt_clks
= dss_dsi1_opt_clks
,
659 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi1_opt_clks
),
663 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs
[] = {
664 { .irq
= 84 + OMAP44XX_IRQ_GIC_START
},
668 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs
[] = {
669 { .dma_req
= 83 + OMAP44XX_DMA_REQ_START
},
673 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks
[] = {
674 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
677 static struct omap_hwmod omap44xx_dss_dsi2_hwmod
= {
679 .class = &omap44xx_dsi_hwmod_class
,
680 .clkdm_name
= "l3_dss_clkdm",
681 .mpu_irqs
= omap44xx_dss_dsi2_irqs
,
682 .sdma_reqs
= omap44xx_dss_dsi2_sdma_reqs
,
683 .main_clk
= "dss_dss_clk",
686 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
687 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
690 .opt_clks
= dss_dsi2_opt_clks
,
691 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi2_opt_clks
),
699 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc
= {
702 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
704 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
706 .sysc_fields
= &omap_hwmod_sysc_type2
,
709 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class
= {
711 .sysc
= &omap44xx_hdmi_sysc
,
715 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs
[] = {
716 { .irq
= 101 + OMAP44XX_IRQ_GIC_START
},
720 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs
[] = {
721 { .dma_req
= 75 + OMAP44XX_DMA_REQ_START
},
725 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks
[] = {
726 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
729 static struct omap_hwmod omap44xx_dss_hdmi_hwmod
= {
731 .class = &omap44xx_hdmi_hwmod_class
,
732 .clkdm_name
= "l3_dss_clkdm",
733 .mpu_irqs
= omap44xx_dss_hdmi_irqs
,
734 .sdma_reqs
= omap44xx_dss_hdmi_sdma_reqs
,
735 .main_clk
= "dss_48mhz_clk",
738 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
739 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
742 .opt_clks
= dss_hdmi_opt_clks
,
743 .opt_clks_cnt
= ARRAY_SIZE(dss_hdmi_opt_clks
),
748 * remote frame buffer interface
751 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc
= {
755 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
756 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
757 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
758 .sysc_fields
= &omap_hwmod_sysc_type1
,
761 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class
= {
763 .sysc
= &omap44xx_rfbi_sysc
,
767 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs
[] = {
768 { .dma_req
= 13 + OMAP44XX_DMA_REQ_START
},
772 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks
[] = {
773 { .role
= "ick", .clk
= "dss_fck" },
776 static struct omap_hwmod omap44xx_dss_rfbi_hwmod
= {
778 .class = &omap44xx_rfbi_hwmod_class
,
779 .clkdm_name
= "l3_dss_clkdm",
780 .sdma_reqs
= omap44xx_dss_rfbi_sdma_reqs
,
781 .main_clk
= "dss_dss_clk",
784 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
785 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
788 .opt_clks
= dss_rfbi_opt_clks
,
789 .opt_clks_cnt
= ARRAY_SIZE(dss_rfbi_opt_clks
),
797 static struct omap_hwmod_class omap44xx_venc_hwmod_class
= {
802 static struct omap_hwmod omap44xx_dss_venc_hwmod
= {
804 .class = &omap44xx_venc_hwmod_class
,
805 .clkdm_name
= "l3_dss_clkdm",
806 .main_clk
= "dss_tv_clk",
809 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
810 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
817 * face detection hw accelerator module
820 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc
= {
824 * FDIF needs 100 OCP clk cycles delay after a softreset before
825 * accessing sysconfig again.
826 * The lowest frequency at the moment for L3 bus is 100 MHz, so
827 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
829 * TODO: Indicate errata when available.
832 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
833 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
834 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
835 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
836 .sysc_fields
= &omap_hwmod_sysc_type2
,
839 static struct omap_hwmod_class omap44xx_fdif_hwmod_class
= {
841 .sysc
= &omap44xx_fdif_sysc
,
845 static struct omap_hwmod_irq_info omap44xx_fdif_irqs
[] = {
846 { .irq
= 69 + OMAP44XX_IRQ_GIC_START
},
850 static struct omap_hwmod omap44xx_fdif_hwmod
= {
852 .class = &omap44xx_fdif_hwmod_class
,
853 .clkdm_name
= "iss_clkdm",
854 .mpu_irqs
= omap44xx_fdif_irqs
,
855 .main_clk
= "fdif_fck",
858 .clkctrl_offs
= OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET
,
859 .context_offs
= OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET
,
860 .modulemode
= MODULEMODE_SWCTRL
,
867 * general purpose io module
870 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc
= {
874 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
875 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
876 SYSS_HAS_RESET_STATUS
),
877 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
879 .sysc_fields
= &omap_hwmod_sysc_type1
,
882 static struct omap_hwmod_class omap44xx_gpio_hwmod_class
= {
884 .sysc
= &omap44xx_gpio_sysc
,
889 static struct omap_gpio_dev_attr gpio_dev_attr
= {
895 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs
[] = {
896 { .irq
= 29 + OMAP44XX_IRQ_GIC_START
},
900 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
901 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
904 static struct omap_hwmod omap44xx_gpio1_hwmod
= {
906 .class = &omap44xx_gpio_hwmod_class
,
907 .clkdm_name
= "l4_wkup_clkdm",
908 .mpu_irqs
= omap44xx_gpio1_irqs
,
909 .main_clk
= "gpio1_ick",
912 .clkctrl_offs
= OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET
,
913 .context_offs
= OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET
,
914 .modulemode
= MODULEMODE_HWCTRL
,
917 .opt_clks
= gpio1_opt_clks
,
918 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
919 .dev_attr
= &gpio_dev_attr
,
923 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs
[] = {
924 { .irq
= 30 + OMAP44XX_IRQ_GIC_START
},
928 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
929 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
932 static struct omap_hwmod omap44xx_gpio2_hwmod
= {
934 .class = &omap44xx_gpio_hwmod_class
,
935 .clkdm_name
= "l4_per_clkdm",
936 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
937 .mpu_irqs
= omap44xx_gpio2_irqs
,
938 .main_clk
= "gpio2_ick",
941 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET
,
942 .context_offs
= OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET
,
943 .modulemode
= MODULEMODE_HWCTRL
,
946 .opt_clks
= gpio2_opt_clks
,
947 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
948 .dev_attr
= &gpio_dev_attr
,
952 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs
[] = {
953 { .irq
= 31 + OMAP44XX_IRQ_GIC_START
},
957 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
958 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
961 static struct omap_hwmod omap44xx_gpio3_hwmod
= {
963 .class = &omap44xx_gpio_hwmod_class
,
964 .clkdm_name
= "l4_per_clkdm",
965 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
966 .mpu_irqs
= omap44xx_gpio3_irqs
,
967 .main_clk
= "gpio3_ick",
970 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET
,
971 .context_offs
= OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET
,
972 .modulemode
= MODULEMODE_HWCTRL
,
975 .opt_clks
= gpio3_opt_clks
,
976 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
977 .dev_attr
= &gpio_dev_attr
,
981 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs
[] = {
982 { .irq
= 32 + OMAP44XX_IRQ_GIC_START
},
986 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
987 { .role
= "dbclk", .clk
= "gpio4_dbclk" },
990 static struct omap_hwmod omap44xx_gpio4_hwmod
= {
992 .class = &omap44xx_gpio_hwmod_class
,
993 .clkdm_name
= "l4_per_clkdm",
994 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
995 .mpu_irqs
= omap44xx_gpio4_irqs
,
996 .main_clk
= "gpio4_ick",
999 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET
,
1000 .context_offs
= OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET
,
1001 .modulemode
= MODULEMODE_HWCTRL
,
1004 .opt_clks
= gpio4_opt_clks
,
1005 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
1006 .dev_attr
= &gpio_dev_attr
,
1010 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs
[] = {
1011 { .irq
= 33 + OMAP44XX_IRQ_GIC_START
},
1015 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
1016 { .role
= "dbclk", .clk
= "gpio5_dbclk" },
1019 static struct omap_hwmod omap44xx_gpio5_hwmod
= {
1021 .class = &omap44xx_gpio_hwmod_class
,
1022 .clkdm_name
= "l4_per_clkdm",
1023 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1024 .mpu_irqs
= omap44xx_gpio5_irqs
,
1025 .main_clk
= "gpio5_ick",
1028 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET
,
1029 .context_offs
= OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET
,
1030 .modulemode
= MODULEMODE_HWCTRL
,
1033 .opt_clks
= gpio5_opt_clks
,
1034 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
1035 .dev_attr
= &gpio_dev_attr
,
1039 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs
[] = {
1040 { .irq
= 34 + OMAP44XX_IRQ_GIC_START
},
1044 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
1045 { .role
= "dbclk", .clk
= "gpio6_dbclk" },
1048 static struct omap_hwmod omap44xx_gpio6_hwmod
= {
1050 .class = &omap44xx_gpio_hwmod_class
,
1051 .clkdm_name
= "l4_per_clkdm",
1052 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1053 .mpu_irqs
= omap44xx_gpio6_irqs
,
1054 .main_clk
= "gpio6_ick",
1057 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET
,
1058 .context_offs
= OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET
,
1059 .modulemode
= MODULEMODE_HWCTRL
,
1062 .opt_clks
= gpio6_opt_clks
,
1063 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
1064 .dev_attr
= &gpio_dev_attr
,
1069 * general purpose memory controller
1072 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc
= {
1074 .sysc_offs
= 0x0010,
1075 .syss_offs
= 0x0014,
1076 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
1077 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1078 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1079 .sysc_fields
= &omap_hwmod_sysc_type1
,
1082 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class
= {
1084 .sysc
= &omap44xx_gpmc_sysc
,
1088 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs
[] = {
1089 { .irq
= 20 + OMAP44XX_IRQ_GIC_START
},
1093 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs
[] = {
1094 { .dma_req
= 3 + OMAP44XX_DMA_REQ_START
},
1098 static struct omap_hwmod omap44xx_gpmc_hwmod
= {
1100 .class = &omap44xx_gpmc_hwmod_class
,
1101 .clkdm_name
= "l3_2_clkdm",
1102 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1103 .mpu_irqs
= omap44xx_gpmc_irqs
,
1104 .sdma_reqs
= omap44xx_gpmc_sdma_reqs
,
1107 .clkctrl_offs
= OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET
,
1108 .context_offs
= OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET
,
1109 .modulemode
= MODULEMODE_HWCTRL
,
1116 * hdq / 1-wire serial interface controller
1119 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc
= {
1121 .sysc_offs
= 0x0014,
1122 .syss_offs
= 0x0018,
1123 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SOFTRESET
|
1124 SYSS_HAS_RESET_STATUS
),
1125 .sysc_fields
= &omap_hwmod_sysc_type1
,
1128 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class
= {
1130 .sysc
= &omap44xx_hdq1w_sysc
,
1134 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs
[] = {
1135 { .irq
= 58 + OMAP44XX_IRQ_GIC_START
},
1139 static struct omap_hwmod omap44xx_hdq1w_hwmod
= {
1141 .class = &omap44xx_hdq1w_hwmod_class
,
1142 .clkdm_name
= "l4_per_clkdm",
1143 .flags
= HWMOD_INIT_NO_RESET
, /* XXX temporary */
1144 .mpu_irqs
= omap44xx_hdq1w_irqs
,
1145 .main_clk
= "hdq1w_fck",
1148 .clkctrl_offs
= OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET
,
1149 .context_offs
= OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET
,
1150 .modulemode
= MODULEMODE_SWCTRL
,
1157 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1161 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc
= {
1163 .sysc_offs
= 0x0010,
1164 .syss_offs
= 0x0014,
1165 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_EMUFREE
|
1166 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
1167 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1168 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1169 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1170 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1171 .sysc_fields
= &omap_hwmod_sysc_type1
,
1174 static struct omap_hwmod_class omap44xx_hsi_hwmod_class
= {
1176 .sysc
= &omap44xx_hsi_sysc
,
1180 static struct omap_hwmod_irq_info omap44xx_hsi_irqs
[] = {
1181 { .name
= "mpu_p1", .irq
= 67 + OMAP44XX_IRQ_GIC_START
},
1182 { .name
= "mpu_p2", .irq
= 68 + OMAP44XX_IRQ_GIC_START
},
1183 { .name
= "mpu_dma", .irq
= 71 + OMAP44XX_IRQ_GIC_START
},
1187 static struct omap_hwmod omap44xx_hsi_hwmod
= {
1189 .class = &omap44xx_hsi_hwmod_class
,
1190 .clkdm_name
= "l3_init_clkdm",
1191 .mpu_irqs
= omap44xx_hsi_irqs
,
1192 .main_clk
= "hsi_fck",
1195 .clkctrl_offs
= OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET
,
1196 .context_offs
= OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET
,
1197 .modulemode
= MODULEMODE_HWCTRL
,
1204 * multimaster high-speed i2c controller
1207 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc
= {
1208 .sysc_offs
= 0x0010,
1209 .syss_offs
= 0x0090,
1210 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1211 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
1212 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1213 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1215 .clockact
= CLOCKACT_TEST_ICLK
,
1216 .sysc_fields
= &omap_hwmod_sysc_type1
,
1219 static struct omap_hwmod_class omap44xx_i2c_hwmod_class
= {
1221 .sysc
= &omap44xx_i2c_sysc
,
1222 .rev
= OMAP_I2C_IP_VERSION_2
,
1223 .reset
= &omap_i2c_reset
,
1226 static struct omap_i2c_dev_attr i2c_dev_attr
= {
1227 .flags
= OMAP_I2C_FLAG_BUS_SHIFT_NONE
,
1231 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs
[] = {
1232 { .irq
= 56 + OMAP44XX_IRQ_GIC_START
},
1236 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs
[] = {
1237 { .name
= "tx", .dma_req
= 26 + OMAP44XX_DMA_REQ_START
},
1238 { .name
= "rx", .dma_req
= 27 + OMAP44XX_DMA_REQ_START
},
1242 static struct omap_hwmod omap44xx_i2c1_hwmod
= {
1244 .class = &omap44xx_i2c_hwmod_class
,
1245 .clkdm_name
= "l4_per_clkdm",
1246 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1247 .mpu_irqs
= omap44xx_i2c1_irqs
,
1248 .sdma_reqs
= omap44xx_i2c1_sdma_reqs
,
1249 .main_clk
= "i2c1_fck",
1252 .clkctrl_offs
= OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET
,
1253 .context_offs
= OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET
,
1254 .modulemode
= MODULEMODE_SWCTRL
,
1257 .dev_attr
= &i2c_dev_attr
,
1261 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs
[] = {
1262 { .irq
= 57 + OMAP44XX_IRQ_GIC_START
},
1266 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs
[] = {
1267 { .name
= "tx", .dma_req
= 28 + OMAP44XX_DMA_REQ_START
},
1268 { .name
= "rx", .dma_req
= 29 + OMAP44XX_DMA_REQ_START
},
1272 static struct omap_hwmod omap44xx_i2c2_hwmod
= {
1274 .class = &omap44xx_i2c_hwmod_class
,
1275 .clkdm_name
= "l4_per_clkdm",
1276 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1277 .mpu_irqs
= omap44xx_i2c2_irqs
,
1278 .sdma_reqs
= omap44xx_i2c2_sdma_reqs
,
1279 .main_clk
= "i2c2_fck",
1282 .clkctrl_offs
= OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET
,
1283 .context_offs
= OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET
,
1284 .modulemode
= MODULEMODE_SWCTRL
,
1287 .dev_attr
= &i2c_dev_attr
,
1291 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs
[] = {
1292 { .irq
= 61 + OMAP44XX_IRQ_GIC_START
},
1296 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs
[] = {
1297 { .name
= "tx", .dma_req
= 24 + OMAP44XX_DMA_REQ_START
},
1298 { .name
= "rx", .dma_req
= 25 + OMAP44XX_DMA_REQ_START
},
1302 static struct omap_hwmod omap44xx_i2c3_hwmod
= {
1304 .class = &omap44xx_i2c_hwmod_class
,
1305 .clkdm_name
= "l4_per_clkdm",
1306 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1307 .mpu_irqs
= omap44xx_i2c3_irqs
,
1308 .sdma_reqs
= omap44xx_i2c3_sdma_reqs
,
1309 .main_clk
= "i2c3_fck",
1312 .clkctrl_offs
= OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET
,
1313 .context_offs
= OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET
,
1314 .modulemode
= MODULEMODE_SWCTRL
,
1317 .dev_attr
= &i2c_dev_attr
,
1321 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs
[] = {
1322 { .irq
= 62 + OMAP44XX_IRQ_GIC_START
},
1326 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs
[] = {
1327 { .name
= "tx", .dma_req
= 123 + OMAP44XX_DMA_REQ_START
},
1328 { .name
= "rx", .dma_req
= 124 + OMAP44XX_DMA_REQ_START
},
1332 static struct omap_hwmod omap44xx_i2c4_hwmod
= {
1334 .class = &omap44xx_i2c_hwmod_class
,
1335 .clkdm_name
= "l4_per_clkdm",
1336 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1337 .mpu_irqs
= omap44xx_i2c4_irqs
,
1338 .sdma_reqs
= omap44xx_i2c4_sdma_reqs
,
1339 .main_clk
= "i2c4_fck",
1342 .clkctrl_offs
= OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET
,
1343 .context_offs
= OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET
,
1344 .modulemode
= MODULEMODE_SWCTRL
,
1347 .dev_attr
= &i2c_dev_attr
,
1352 * imaging processor unit
1355 static struct omap_hwmod_class omap44xx_ipu_hwmod_class
= {
1360 static struct omap_hwmod_irq_info omap44xx_ipu_irqs
[] = {
1361 { .irq
= 100 + OMAP44XX_IRQ_GIC_START
},
1365 static struct omap_hwmod_rst_info omap44xx_ipu_resets
[] = {
1366 { .name
= "cpu0", .rst_shift
= 0 },
1367 { .name
= "cpu1", .rst_shift
= 1 },
1368 { .name
= "mmu_cache", .rst_shift
= 2 },
1371 static struct omap_hwmod omap44xx_ipu_hwmod
= {
1373 .class = &omap44xx_ipu_hwmod_class
,
1374 .clkdm_name
= "ducati_clkdm",
1375 .mpu_irqs
= omap44xx_ipu_irqs
,
1376 .rst_lines
= omap44xx_ipu_resets
,
1377 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_ipu_resets
),
1378 .main_clk
= "ipu_fck",
1381 .clkctrl_offs
= OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET
,
1382 .rstctrl_offs
= OMAP4_RM_DUCATI_RSTCTRL_OFFSET
,
1383 .context_offs
= OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET
,
1384 .modulemode
= MODULEMODE_HWCTRL
,
1391 * external images sensor pixel data processor
1394 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc
= {
1396 .sysc_offs
= 0x0010,
1398 * ISS needs 100 OCP clk cycles delay after a softreset before
1399 * accessing sysconfig again.
1400 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1401 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1403 * TODO: Indicate errata when available.
1406 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1407 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1408 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1409 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1410 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1411 .sysc_fields
= &omap_hwmod_sysc_type2
,
1414 static struct omap_hwmod_class omap44xx_iss_hwmod_class
= {
1416 .sysc
= &omap44xx_iss_sysc
,
1420 static struct omap_hwmod_irq_info omap44xx_iss_irqs
[] = {
1421 { .irq
= 24 + OMAP44XX_IRQ_GIC_START
},
1425 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs
[] = {
1426 { .name
= "1", .dma_req
= 8 + OMAP44XX_DMA_REQ_START
},
1427 { .name
= "2", .dma_req
= 9 + OMAP44XX_DMA_REQ_START
},
1428 { .name
= "3", .dma_req
= 11 + OMAP44XX_DMA_REQ_START
},
1429 { .name
= "4", .dma_req
= 12 + OMAP44XX_DMA_REQ_START
},
1433 static struct omap_hwmod_opt_clk iss_opt_clks
[] = {
1434 { .role
= "ctrlclk", .clk
= "iss_ctrlclk" },
1437 static struct omap_hwmod omap44xx_iss_hwmod
= {
1439 .class = &omap44xx_iss_hwmod_class
,
1440 .clkdm_name
= "iss_clkdm",
1441 .mpu_irqs
= omap44xx_iss_irqs
,
1442 .sdma_reqs
= omap44xx_iss_sdma_reqs
,
1443 .main_clk
= "iss_fck",
1446 .clkctrl_offs
= OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET
,
1447 .context_offs
= OMAP4_RM_CAM_ISS_CONTEXT_OFFSET
,
1448 .modulemode
= MODULEMODE_SWCTRL
,
1451 .opt_clks
= iss_opt_clks
,
1452 .opt_clks_cnt
= ARRAY_SIZE(iss_opt_clks
),
1457 * multi-standard video encoder/decoder hardware accelerator
1460 static struct omap_hwmod_class omap44xx_iva_hwmod_class
= {
1465 static struct omap_hwmod_irq_info omap44xx_iva_irqs
[] = {
1466 { .name
= "sync_1", .irq
= 103 + OMAP44XX_IRQ_GIC_START
},
1467 { .name
= "sync_0", .irq
= 104 + OMAP44XX_IRQ_GIC_START
},
1468 { .name
= "mailbox_0", .irq
= 107 + OMAP44XX_IRQ_GIC_START
},
1472 static struct omap_hwmod_rst_info omap44xx_iva_resets
[] = {
1473 { .name
= "seq0", .rst_shift
= 0 },
1474 { .name
= "seq1", .rst_shift
= 1 },
1475 { .name
= "logic", .rst_shift
= 2 },
1478 static struct omap_hwmod omap44xx_iva_hwmod
= {
1480 .class = &omap44xx_iva_hwmod_class
,
1481 .clkdm_name
= "ivahd_clkdm",
1482 .mpu_irqs
= omap44xx_iva_irqs
,
1483 .rst_lines
= omap44xx_iva_resets
,
1484 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_iva_resets
),
1485 .main_clk
= "iva_fck",
1488 .clkctrl_offs
= OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET
,
1489 .rstctrl_offs
= OMAP4_RM_IVAHD_RSTCTRL_OFFSET
,
1490 .context_offs
= OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET
,
1491 .modulemode
= MODULEMODE_HWCTRL
,
1498 * keyboard controller
1501 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc
= {
1503 .sysc_offs
= 0x0010,
1504 .syss_offs
= 0x0014,
1505 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1506 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
1507 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1508 SYSS_HAS_RESET_STATUS
),
1509 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1510 .sysc_fields
= &omap_hwmod_sysc_type1
,
1513 static struct omap_hwmod_class omap44xx_kbd_hwmod_class
= {
1515 .sysc
= &omap44xx_kbd_sysc
,
1519 static struct omap_hwmod_irq_info omap44xx_kbd_irqs
[] = {
1520 { .irq
= 120 + OMAP44XX_IRQ_GIC_START
},
1524 static struct omap_hwmod omap44xx_kbd_hwmod
= {
1526 .class = &omap44xx_kbd_hwmod_class
,
1527 .clkdm_name
= "l4_wkup_clkdm",
1528 .mpu_irqs
= omap44xx_kbd_irqs
,
1529 .main_clk
= "kbd_fck",
1532 .clkctrl_offs
= OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET
,
1533 .context_offs
= OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET
,
1534 .modulemode
= MODULEMODE_SWCTRL
,
1541 * mailbox module allowing communication between the on-chip processors using a
1542 * queued mailbox-interrupt mechanism.
1545 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc
= {
1547 .sysc_offs
= 0x0010,
1548 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1549 SYSC_HAS_SOFTRESET
),
1550 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1551 .sysc_fields
= &omap_hwmod_sysc_type2
,
1554 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class
= {
1556 .sysc
= &omap44xx_mailbox_sysc
,
1560 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs
[] = {
1561 { .irq
= 26 + OMAP44XX_IRQ_GIC_START
},
1565 static struct omap_hwmod omap44xx_mailbox_hwmod
= {
1567 .class = &omap44xx_mailbox_hwmod_class
,
1568 .clkdm_name
= "l4_cfg_clkdm",
1569 .mpu_irqs
= omap44xx_mailbox_irqs
,
1572 .clkctrl_offs
= OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET
,
1573 .context_offs
= OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET
,
1580 * multi channel buffered serial port controller
1583 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc
= {
1584 .sysc_offs
= 0x008c,
1585 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_ENAWAKEUP
|
1586 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1587 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1588 .sysc_fields
= &omap_hwmod_sysc_type1
,
1591 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class
= {
1593 .sysc
= &omap44xx_mcbsp_sysc
,
1594 .rev
= MCBSP_CONFIG_TYPE4
,
1598 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs
[] = {
1599 { .irq
= 17 + OMAP44XX_IRQ_GIC_START
},
1603 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs
[] = {
1604 { .name
= "tx", .dma_req
= 32 + OMAP44XX_DMA_REQ_START
},
1605 { .name
= "rx", .dma_req
= 33 + OMAP44XX_DMA_REQ_START
},
1609 static struct omap_hwmod_opt_clk mcbsp1_opt_clks
[] = {
1610 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1611 { .role
= "prcm_clk", .clk
= "mcbsp1_sync_mux_ck" },
1614 static struct omap_hwmod omap44xx_mcbsp1_hwmod
= {
1616 .class = &omap44xx_mcbsp_hwmod_class
,
1617 .clkdm_name
= "abe_clkdm",
1618 .mpu_irqs
= omap44xx_mcbsp1_irqs
,
1619 .sdma_reqs
= omap44xx_mcbsp1_sdma_reqs
,
1620 .main_clk
= "mcbsp1_fck",
1623 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET
,
1624 .context_offs
= OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET
,
1625 .modulemode
= MODULEMODE_SWCTRL
,
1628 .opt_clks
= mcbsp1_opt_clks
,
1629 .opt_clks_cnt
= ARRAY_SIZE(mcbsp1_opt_clks
),
1633 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs
[] = {
1634 { .irq
= 22 + OMAP44XX_IRQ_GIC_START
},
1638 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs
[] = {
1639 { .name
= "tx", .dma_req
= 16 + OMAP44XX_DMA_REQ_START
},
1640 { .name
= "rx", .dma_req
= 17 + OMAP44XX_DMA_REQ_START
},
1644 static struct omap_hwmod_opt_clk mcbsp2_opt_clks
[] = {
1645 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1646 { .role
= "prcm_clk", .clk
= "mcbsp2_sync_mux_ck" },
1649 static struct omap_hwmod omap44xx_mcbsp2_hwmod
= {
1651 .class = &omap44xx_mcbsp_hwmod_class
,
1652 .clkdm_name
= "abe_clkdm",
1653 .mpu_irqs
= omap44xx_mcbsp2_irqs
,
1654 .sdma_reqs
= omap44xx_mcbsp2_sdma_reqs
,
1655 .main_clk
= "mcbsp2_fck",
1658 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET
,
1659 .context_offs
= OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET
,
1660 .modulemode
= MODULEMODE_SWCTRL
,
1663 .opt_clks
= mcbsp2_opt_clks
,
1664 .opt_clks_cnt
= ARRAY_SIZE(mcbsp2_opt_clks
),
1668 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs
[] = {
1669 { .irq
= 23 + OMAP44XX_IRQ_GIC_START
},
1673 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs
[] = {
1674 { .name
= "tx", .dma_req
= 18 + OMAP44XX_DMA_REQ_START
},
1675 { .name
= "rx", .dma_req
= 19 + OMAP44XX_DMA_REQ_START
},
1679 static struct omap_hwmod_opt_clk mcbsp3_opt_clks
[] = {
1680 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1681 { .role
= "prcm_clk", .clk
= "mcbsp3_sync_mux_ck" },
1684 static struct omap_hwmod omap44xx_mcbsp3_hwmod
= {
1686 .class = &omap44xx_mcbsp_hwmod_class
,
1687 .clkdm_name
= "abe_clkdm",
1688 .mpu_irqs
= omap44xx_mcbsp3_irqs
,
1689 .sdma_reqs
= omap44xx_mcbsp3_sdma_reqs
,
1690 .main_clk
= "mcbsp3_fck",
1693 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET
,
1694 .context_offs
= OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET
,
1695 .modulemode
= MODULEMODE_SWCTRL
,
1698 .opt_clks
= mcbsp3_opt_clks
,
1699 .opt_clks_cnt
= ARRAY_SIZE(mcbsp3_opt_clks
),
1703 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs
[] = {
1704 { .irq
= 16 + OMAP44XX_IRQ_GIC_START
},
1708 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs
[] = {
1709 { .name
= "tx", .dma_req
= 30 + OMAP44XX_DMA_REQ_START
},
1710 { .name
= "rx", .dma_req
= 31 + OMAP44XX_DMA_REQ_START
},
1714 static struct omap_hwmod_opt_clk mcbsp4_opt_clks
[] = {
1715 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1716 { .role
= "prcm_clk", .clk
= "mcbsp4_sync_mux_ck" },
1719 static struct omap_hwmod omap44xx_mcbsp4_hwmod
= {
1721 .class = &omap44xx_mcbsp_hwmod_class
,
1722 .clkdm_name
= "l4_per_clkdm",
1723 .mpu_irqs
= omap44xx_mcbsp4_irqs
,
1724 .sdma_reqs
= omap44xx_mcbsp4_sdma_reqs
,
1725 .main_clk
= "mcbsp4_fck",
1728 .clkctrl_offs
= OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET
,
1729 .context_offs
= OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET
,
1730 .modulemode
= MODULEMODE_SWCTRL
,
1733 .opt_clks
= mcbsp4_opt_clks
,
1734 .opt_clks_cnt
= ARRAY_SIZE(mcbsp4_opt_clks
),
1739 * multi channel pdm controller (proprietary interface with phoenix power
1743 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc
= {
1745 .sysc_offs
= 0x0010,
1746 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1747 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1748 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1750 .sysc_fields
= &omap_hwmod_sysc_type2
,
1753 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class
= {
1755 .sysc
= &omap44xx_mcpdm_sysc
,
1759 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs
[] = {
1760 { .irq
= 112 + OMAP44XX_IRQ_GIC_START
},
1764 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs
[] = {
1765 { .name
= "up_link", .dma_req
= 64 + OMAP44XX_DMA_REQ_START
},
1766 { .name
= "dn_link", .dma_req
= 65 + OMAP44XX_DMA_REQ_START
},
1770 static struct omap_hwmod omap44xx_mcpdm_hwmod
= {
1772 .class = &omap44xx_mcpdm_hwmod_class
,
1773 .clkdm_name
= "abe_clkdm",
1774 .mpu_irqs
= omap44xx_mcpdm_irqs
,
1775 .sdma_reqs
= omap44xx_mcpdm_sdma_reqs
,
1776 .main_clk
= "mcpdm_fck",
1779 .clkctrl_offs
= OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET
,
1780 .context_offs
= OMAP4_RM_ABE_PDM_CONTEXT_OFFSET
,
1781 .modulemode
= MODULEMODE_SWCTRL
,
1788 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1792 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc
= {
1794 .sysc_offs
= 0x0010,
1795 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1796 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1797 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1799 .sysc_fields
= &omap_hwmod_sysc_type2
,
1802 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class
= {
1804 .sysc
= &omap44xx_mcspi_sysc
,
1805 .rev
= OMAP4_MCSPI_REV
,
1809 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs
[] = {
1810 { .irq
= 65 + OMAP44XX_IRQ_GIC_START
},
1814 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs
[] = {
1815 { .name
= "tx0", .dma_req
= 34 + OMAP44XX_DMA_REQ_START
},
1816 { .name
= "rx0", .dma_req
= 35 + OMAP44XX_DMA_REQ_START
},
1817 { .name
= "tx1", .dma_req
= 36 + OMAP44XX_DMA_REQ_START
},
1818 { .name
= "rx1", .dma_req
= 37 + OMAP44XX_DMA_REQ_START
},
1819 { .name
= "tx2", .dma_req
= 38 + OMAP44XX_DMA_REQ_START
},
1820 { .name
= "rx2", .dma_req
= 39 + OMAP44XX_DMA_REQ_START
},
1821 { .name
= "tx3", .dma_req
= 40 + OMAP44XX_DMA_REQ_START
},
1822 { .name
= "rx3", .dma_req
= 41 + OMAP44XX_DMA_REQ_START
},
1826 /* mcspi1 dev_attr */
1827 static struct omap2_mcspi_dev_attr mcspi1_dev_attr
= {
1828 .num_chipselect
= 4,
1831 static struct omap_hwmod omap44xx_mcspi1_hwmod
= {
1833 .class = &omap44xx_mcspi_hwmod_class
,
1834 .clkdm_name
= "l4_per_clkdm",
1835 .mpu_irqs
= omap44xx_mcspi1_irqs
,
1836 .sdma_reqs
= omap44xx_mcspi1_sdma_reqs
,
1837 .main_clk
= "mcspi1_fck",
1840 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
,
1841 .context_offs
= OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET
,
1842 .modulemode
= MODULEMODE_SWCTRL
,
1845 .dev_attr
= &mcspi1_dev_attr
,
1849 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs
[] = {
1850 { .irq
= 66 + OMAP44XX_IRQ_GIC_START
},
1854 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs
[] = {
1855 { .name
= "tx0", .dma_req
= 42 + OMAP44XX_DMA_REQ_START
},
1856 { .name
= "rx0", .dma_req
= 43 + OMAP44XX_DMA_REQ_START
},
1857 { .name
= "tx1", .dma_req
= 44 + OMAP44XX_DMA_REQ_START
},
1858 { .name
= "rx1", .dma_req
= 45 + OMAP44XX_DMA_REQ_START
},
1862 /* mcspi2 dev_attr */
1863 static struct omap2_mcspi_dev_attr mcspi2_dev_attr
= {
1864 .num_chipselect
= 2,
1867 static struct omap_hwmod omap44xx_mcspi2_hwmod
= {
1869 .class = &omap44xx_mcspi_hwmod_class
,
1870 .clkdm_name
= "l4_per_clkdm",
1871 .mpu_irqs
= omap44xx_mcspi2_irqs
,
1872 .sdma_reqs
= omap44xx_mcspi2_sdma_reqs
,
1873 .main_clk
= "mcspi2_fck",
1876 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
,
1877 .context_offs
= OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET
,
1878 .modulemode
= MODULEMODE_SWCTRL
,
1881 .dev_attr
= &mcspi2_dev_attr
,
1885 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs
[] = {
1886 { .irq
= 91 + OMAP44XX_IRQ_GIC_START
},
1890 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs
[] = {
1891 { .name
= "tx0", .dma_req
= 14 + OMAP44XX_DMA_REQ_START
},
1892 { .name
= "rx0", .dma_req
= 15 + OMAP44XX_DMA_REQ_START
},
1893 { .name
= "tx1", .dma_req
= 22 + OMAP44XX_DMA_REQ_START
},
1894 { .name
= "rx1", .dma_req
= 23 + OMAP44XX_DMA_REQ_START
},
1898 /* mcspi3 dev_attr */
1899 static struct omap2_mcspi_dev_attr mcspi3_dev_attr
= {
1900 .num_chipselect
= 2,
1903 static struct omap_hwmod omap44xx_mcspi3_hwmod
= {
1905 .class = &omap44xx_mcspi_hwmod_class
,
1906 .clkdm_name
= "l4_per_clkdm",
1907 .mpu_irqs
= omap44xx_mcspi3_irqs
,
1908 .sdma_reqs
= omap44xx_mcspi3_sdma_reqs
,
1909 .main_clk
= "mcspi3_fck",
1912 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
,
1913 .context_offs
= OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET
,
1914 .modulemode
= MODULEMODE_SWCTRL
,
1917 .dev_attr
= &mcspi3_dev_attr
,
1921 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs
[] = {
1922 { .irq
= 48 + OMAP44XX_IRQ_GIC_START
},
1926 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs
[] = {
1927 { .name
= "tx0", .dma_req
= 69 + OMAP44XX_DMA_REQ_START
},
1928 { .name
= "rx0", .dma_req
= 70 + OMAP44XX_DMA_REQ_START
},
1932 /* mcspi4 dev_attr */
1933 static struct omap2_mcspi_dev_attr mcspi4_dev_attr
= {
1934 .num_chipselect
= 1,
1937 static struct omap_hwmod omap44xx_mcspi4_hwmod
= {
1939 .class = &omap44xx_mcspi_hwmod_class
,
1940 .clkdm_name
= "l4_per_clkdm",
1941 .mpu_irqs
= omap44xx_mcspi4_irqs
,
1942 .sdma_reqs
= omap44xx_mcspi4_sdma_reqs
,
1943 .main_clk
= "mcspi4_fck",
1946 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
,
1947 .context_offs
= OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET
,
1948 .modulemode
= MODULEMODE_SWCTRL
,
1951 .dev_attr
= &mcspi4_dev_attr
,
1956 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1959 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc
= {
1961 .sysc_offs
= 0x0010,
1962 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
1963 SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1964 SYSC_HAS_SOFTRESET
),
1965 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1966 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1967 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1968 .sysc_fields
= &omap_hwmod_sysc_type2
,
1971 static struct omap_hwmod_class omap44xx_mmc_hwmod_class
= {
1973 .sysc
= &omap44xx_mmc_sysc
,
1977 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs
[] = {
1978 { .irq
= 83 + OMAP44XX_IRQ_GIC_START
},
1982 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs
[] = {
1983 { .name
= "tx", .dma_req
= 60 + OMAP44XX_DMA_REQ_START
},
1984 { .name
= "rx", .dma_req
= 61 + OMAP44XX_DMA_REQ_START
},
1989 static struct omap_mmc_dev_attr mmc1_dev_attr
= {
1990 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
1993 static struct omap_hwmod omap44xx_mmc1_hwmod
= {
1995 .class = &omap44xx_mmc_hwmod_class
,
1996 .clkdm_name
= "l3_init_clkdm",
1997 .mpu_irqs
= omap44xx_mmc1_irqs
,
1998 .sdma_reqs
= omap44xx_mmc1_sdma_reqs
,
1999 .main_clk
= "mmc1_fck",
2002 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET
,
2003 .context_offs
= OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET
,
2004 .modulemode
= MODULEMODE_SWCTRL
,
2007 .dev_attr
= &mmc1_dev_attr
,
2011 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs
[] = {
2012 { .irq
= 86 + OMAP44XX_IRQ_GIC_START
},
2016 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs
[] = {
2017 { .name
= "tx", .dma_req
= 46 + OMAP44XX_DMA_REQ_START
},
2018 { .name
= "rx", .dma_req
= 47 + OMAP44XX_DMA_REQ_START
},
2022 static struct omap_hwmod omap44xx_mmc2_hwmod
= {
2024 .class = &omap44xx_mmc_hwmod_class
,
2025 .clkdm_name
= "l3_init_clkdm",
2026 .mpu_irqs
= omap44xx_mmc2_irqs
,
2027 .sdma_reqs
= omap44xx_mmc2_sdma_reqs
,
2028 .main_clk
= "mmc2_fck",
2031 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET
,
2032 .context_offs
= OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET
,
2033 .modulemode
= MODULEMODE_SWCTRL
,
2039 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs
[] = {
2040 { .irq
= 94 + OMAP44XX_IRQ_GIC_START
},
2044 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs
[] = {
2045 { .name
= "tx", .dma_req
= 76 + OMAP44XX_DMA_REQ_START
},
2046 { .name
= "rx", .dma_req
= 77 + OMAP44XX_DMA_REQ_START
},
2050 static struct omap_hwmod omap44xx_mmc3_hwmod
= {
2052 .class = &omap44xx_mmc_hwmod_class
,
2053 .clkdm_name
= "l4_per_clkdm",
2054 .mpu_irqs
= omap44xx_mmc3_irqs
,
2055 .sdma_reqs
= omap44xx_mmc3_sdma_reqs
,
2056 .main_clk
= "mmc3_fck",
2059 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET
,
2060 .context_offs
= OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET
,
2061 .modulemode
= MODULEMODE_SWCTRL
,
2067 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs
[] = {
2068 { .irq
= 96 + OMAP44XX_IRQ_GIC_START
},
2072 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs
[] = {
2073 { .name
= "tx", .dma_req
= 56 + OMAP44XX_DMA_REQ_START
},
2074 { .name
= "rx", .dma_req
= 57 + OMAP44XX_DMA_REQ_START
},
2078 static struct omap_hwmod omap44xx_mmc4_hwmod
= {
2080 .class = &omap44xx_mmc_hwmod_class
,
2081 .clkdm_name
= "l4_per_clkdm",
2082 .mpu_irqs
= omap44xx_mmc4_irqs
,
2083 .sdma_reqs
= omap44xx_mmc4_sdma_reqs
,
2084 .main_clk
= "mmc4_fck",
2087 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET
,
2088 .context_offs
= OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET
,
2089 .modulemode
= MODULEMODE_SWCTRL
,
2095 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs
[] = {
2096 { .irq
= 59 + OMAP44XX_IRQ_GIC_START
},
2100 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs
[] = {
2101 { .name
= "tx", .dma_req
= 58 + OMAP44XX_DMA_REQ_START
},
2102 { .name
= "rx", .dma_req
= 59 + OMAP44XX_DMA_REQ_START
},
2106 static struct omap_hwmod omap44xx_mmc5_hwmod
= {
2108 .class = &omap44xx_mmc_hwmod_class
,
2109 .clkdm_name
= "l4_per_clkdm",
2110 .mpu_irqs
= omap44xx_mmc5_irqs
,
2111 .sdma_reqs
= omap44xx_mmc5_sdma_reqs
,
2112 .main_clk
= "mmc5_fck",
2115 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET
,
2116 .context_offs
= OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET
,
2117 .modulemode
= MODULEMODE_SWCTRL
,
2127 static struct omap_hwmod_class omap44xx_mpu_hwmod_class
= {
2132 static struct omap_hwmod_irq_info omap44xx_mpu_irqs
[] = {
2133 { .name
= "pl310", .irq
= 0 + OMAP44XX_IRQ_GIC_START
},
2134 { .name
= "cti0", .irq
= 1 + OMAP44XX_IRQ_GIC_START
},
2135 { .name
= "cti1", .irq
= 2 + OMAP44XX_IRQ_GIC_START
},
2139 static struct omap_hwmod omap44xx_mpu_hwmod
= {
2141 .class = &omap44xx_mpu_hwmod_class
,
2142 .clkdm_name
= "mpuss_clkdm",
2143 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
2144 .mpu_irqs
= omap44xx_mpu_irqs
,
2145 .main_clk
= "dpll_mpu_m2_ck",
2148 .clkctrl_offs
= OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET
,
2149 .context_offs
= OMAP4_RM_MPU_MPU_CONTEXT_OFFSET
,
2155 * 'smartreflex' class
2156 * smartreflex module (monitor silicon performance and outputs a measure of
2157 * performance error)
2160 /* The IP is not compliant to type1 / type2 scheme */
2161 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex
= {
2166 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc
= {
2167 .sysc_offs
= 0x0038,
2168 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
),
2169 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2171 .sysc_fields
= &omap_hwmod_sysc_type_smartreflex
,
2174 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class
= {
2175 .name
= "smartreflex",
2176 .sysc
= &omap44xx_smartreflex_sysc
,
2180 /* smartreflex_core */
2181 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr
= {
2182 .sensor_voltdm_name
= "core",
2185 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs
[] = {
2186 { .irq
= 19 + OMAP44XX_IRQ_GIC_START
},
2190 static struct omap_hwmod omap44xx_smartreflex_core_hwmod
= {
2191 .name
= "smartreflex_core",
2192 .class = &omap44xx_smartreflex_hwmod_class
,
2193 .clkdm_name
= "l4_ao_clkdm",
2194 .mpu_irqs
= omap44xx_smartreflex_core_irqs
,
2196 .main_clk
= "smartreflex_core_fck",
2199 .clkctrl_offs
= OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET
,
2200 .context_offs
= OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET
,
2201 .modulemode
= MODULEMODE_SWCTRL
,
2204 .dev_attr
= &smartreflex_core_dev_attr
,
2207 /* smartreflex_iva */
2208 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr
= {
2209 .sensor_voltdm_name
= "iva",
2212 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs
[] = {
2213 { .irq
= 102 + OMAP44XX_IRQ_GIC_START
},
2217 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod
= {
2218 .name
= "smartreflex_iva",
2219 .class = &omap44xx_smartreflex_hwmod_class
,
2220 .clkdm_name
= "l4_ao_clkdm",
2221 .mpu_irqs
= omap44xx_smartreflex_iva_irqs
,
2222 .main_clk
= "smartreflex_iva_fck",
2225 .clkctrl_offs
= OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET
,
2226 .context_offs
= OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET
,
2227 .modulemode
= MODULEMODE_SWCTRL
,
2230 .dev_attr
= &smartreflex_iva_dev_attr
,
2233 /* smartreflex_mpu */
2234 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr
= {
2235 .sensor_voltdm_name
= "mpu",
2238 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs
[] = {
2239 { .irq
= 18 + OMAP44XX_IRQ_GIC_START
},
2243 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod
= {
2244 .name
= "smartreflex_mpu",
2245 .class = &omap44xx_smartreflex_hwmod_class
,
2246 .clkdm_name
= "l4_ao_clkdm",
2247 .mpu_irqs
= omap44xx_smartreflex_mpu_irqs
,
2248 .main_clk
= "smartreflex_mpu_fck",
2251 .clkctrl_offs
= OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET
,
2252 .context_offs
= OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET
,
2253 .modulemode
= MODULEMODE_SWCTRL
,
2256 .dev_attr
= &smartreflex_mpu_dev_attr
,
2261 * spinlock provides hardware assistance for synchronizing the processes
2262 * running on multiple processors
2265 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc
= {
2267 .sysc_offs
= 0x0010,
2268 .syss_offs
= 0x0014,
2269 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
2270 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
2271 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
2272 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2274 .sysc_fields
= &omap_hwmod_sysc_type1
,
2277 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class
= {
2279 .sysc
= &omap44xx_spinlock_sysc
,
2283 static struct omap_hwmod omap44xx_spinlock_hwmod
= {
2285 .class = &omap44xx_spinlock_hwmod_class
,
2286 .clkdm_name
= "l4_cfg_clkdm",
2289 .clkctrl_offs
= OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET
,
2290 .context_offs
= OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET
,
2297 * general purpose timer module with accurate 1ms tick
2298 * This class contains several variants: ['timer_1ms', 'timer']
2301 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc
= {
2303 .sysc_offs
= 0x0010,
2304 .syss_offs
= 0x0014,
2305 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
2306 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
2307 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
2308 SYSS_HAS_RESET_STATUS
),
2309 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2310 .sysc_fields
= &omap_hwmod_sysc_type1
,
2313 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class
= {
2315 .sysc
= &omap44xx_timer_1ms_sysc
,
2318 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc
= {
2320 .sysc_offs
= 0x0010,
2321 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2322 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2323 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2325 .sysc_fields
= &omap_hwmod_sysc_type2
,
2328 static struct omap_hwmod_class omap44xx_timer_hwmod_class
= {
2330 .sysc
= &omap44xx_timer_sysc
,
2333 /* always-on timers dev attribute */
2334 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr
= {
2335 .timer_capability
= OMAP_TIMER_ALWON
,
2338 /* pwm timers dev attribute */
2339 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr
= {
2340 .timer_capability
= OMAP_TIMER_HAS_PWM
,
2344 static struct omap_hwmod_irq_info omap44xx_timer1_irqs
[] = {
2345 { .irq
= 37 + OMAP44XX_IRQ_GIC_START
},
2349 static struct omap_hwmod omap44xx_timer1_hwmod
= {
2351 .class = &omap44xx_timer_1ms_hwmod_class
,
2352 .clkdm_name
= "l4_wkup_clkdm",
2353 .mpu_irqs
= omap44xx_timer1_irqs
,
2354 .main_clk
= "timer1_fck",
2357 .clkctrl_offs
= OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET
,
2358 .context_offs
= OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET
,
2359 .modulemode
= MODULEMODE_SWCTRL
,
2362 .dev_attr
= &capability_alwon_dev_attr
,
2366 static struct omap_hwmod_irq_info omap44xx_timer2_irqs
[] = {
2367 { .irq
= 38 + OMAP44XX_IRQ_GIC_START
},
2371 static struct omap_hwmod omap44xx_timer2_hwmod
= {
2373 .class = &omap44xx_timer_1ms_hwmod_class
,
2374 .clkdm_name
= "l4_per_clkdm",
2375 .mpu_irqs
= omap44xx_timer2_irqs
,
2376 .main_clk
= "timer2_fck",
2379 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET
,
2380 .context_offs
= OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET
,
2381 .modulemode
= MODULEMODE_SWCTRL
,
2384 .dev_attr
= &capability_alwon_dev_attr
,
2388 static struct omap_hwmod_irq_info omap44xx_timer3_irqs
[] = {
2389 { .irq
= 39 + OMAP44XX_IRQ_GIC_START
},
2393 static struct omap_hwmod omap44xx_timer3_hwmod
= {
2395 .class = &omap44xx_timer_hwmod_class
,
2396 .clkdm_name
= "l4_per_clkdm",
2397 .mpu_irqs
= omap44xx_timer3_irqs
,
2398 .main_clk
= "timer3_fck",
2401 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET
,
2402 .context_offs
= OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET
,
2403 .modulemode
= MODULEMODE_SWCTRL
,
2406 .dev_attr
= &capability_alwon_dev_attr
,
2410 static struct omap_hwmod_irq_info omap44xx_timer4_irqs
[] = {
2411 { .irq
= 40 + OMAP44XX_IRQ_GIC_START
},
2415 static struct omap_hwmod omap44xx_timer4_hwmod
= {
2417 .class = &omap44xx_timer_hwmod_class
,
2418 .clkdm_name
= "l4_per_clkdm",
2419 .mpu_irqs
= omap44xx_timer4_irqs
,
2420 .main_clk
= "timer4_fck",
2423 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET
,
2424 .context_offs
= OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET
,
2425 .modulemode
= MODULEMODE_SWCTRL
,
2428 .dev_attr
= &capability_alwon_dev_attr
,
2432 static struct omap_hwmod_irq_info omap44xx_timer5_irqs
[] = {
2433 { .irq
= 41 + OMAP44XX_IRQ_GIC_START
},
2437 static struct omap_hwmod omap44xx_timer5_hwmod
= {
2439 .class = &omap44xx_timer_hwmod_class
,
2440 .clkdm_name
= "abe_clkdm",
2441 .mpu_irqs
= omap44xx_timer5_irqs
,
2442 .main_clk
= "timer5_fck",
2445 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET
,
2446 .context_offs
= OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET
,
2447 .modulemode
= MODULEMODE_SWCTRL
,
2450 .dev_attr
= &capability_alwon_dev_attr
,
2454 static struct omap_hwmod_irq_info omap44xx_timer6_irqs
[] = {
2455 { .irq
= 42 + OMAP44XX_IRQ_GIC_START
},
2459 static struct omap_hwmod omap44xx_timer6_hwmod
= {
2461 .class = &omap44xx_timer_hwmod_class
,
2462 .clkdm_name
= "abe_clkdm",
2463 .mpu_irqs
= omap44xx_timer6_irqs
,
2465 .main_clk
= "timer6_fck",
2468 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET
,
2469 .context_offs
= OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET
,
2470 .modulemode
= MODULEMODE_SWCTRL
,
2473 .dev_attr
= &capability_alwon_dev_attr
,
2477 static struct omap_hwmod_irq_info omap44xx_timer7_irqs
[] = {
2478 { .irq
= 43 + OMAP44XX_IRQ_GIC_START
},
2482 static struct omap_hwmod omap44xx_timer7_hwmod
= {
2484 .class = &omap44xx_timer_hwmod_class
,
2485 .clkdm_name
= "abe_clkdm",
2486 .mpu_irqs
= omap44xx_timer7_irqs
,
2487 .main_clk
= "timer7_fck",
2490 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET
,
2491 .context_offs
= OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET
,
2492 .modulemode
= MODULEMODE_SWCTRL
,
2495 .dev_attr
= &capability_alwon_dev_attr
,
2499 static struct omap_hwmod_irq_info omap44xx_timer8_irqs
[] = {
2500 { .irq
= 44 + OMAP44XX_IRQ_GIC_START
},
2504 static struct omap_hwmod omap44xx_timer8_hwmod
= {
2506 .class = &omap44xx_timer_hwmod_class
,
2507 .clkdm_name
= "abe_clkdm",
2508 .mpu_irqs
= omap44xx_timer8_irqs
,
2509 .main_clk
= "timer8_fck",
2512 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET
,
2513 .context_offs
= OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET
,
2514 .modulemode
= MODULEMODE_SWCTRL
,
2517 .dev_attr
= &capability_pwm_dev_attr
,
2521 static struct omap_hwmod_irq_info omap44xx_timer9_irqs
[] = {
2522 { .irq
= 45 + OMAP44XX_IRQ_GIC_START
},
2526 static struct omap_hwmod omap44xx_timer9_hwmod
= {
2528 .class = &omap44xx_timer_hwmod_class
,
2529 .clkdm_name
= "l4_per_clkdm",
2530 .mpu_irqs
= omap44xx_timer9_irqs
,
2531 .main_clk
= "timer9_fck",
2534 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET
,
2535 .context_offs
= OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET
,
2536 .modulemode
= MODULEMODE_SWCTRL
,
2539 .dev_attr
= &capability_pwm_dev_attr
,
2543 static struct omap_hwmod_irq_info omap44xx_timer10_irqs
[] = {
2544 { .irq
= 46 + OMAP44XX_IRQ_GIC_START
},
2548 static struct omap_hwmod omap44xx_timer10_hwmod
= {
2550 .class = &omap44xx_timer_1ms_hwmod_class
,
2551 .clkdm_name
= "l4_per_clkdm",
2552 .mpu_irqs
= omap44xx_timer10_irqs
,
2553 .main_clk
= "timer10_fck",
2556 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET
,
2557 .context_offs
= OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET
,
2558 .modulemode
= MODULEMODE_SWCTRL
,
2561 .dev_attr
= &capability_pwm_dev_attr
,
2565 static struct omap_hwmod_irq_info omap44xx_timer11_irqs
[] = {
2566 { .irq
= 47 + OMAP44XX_IRQ_GIC_START
},
2570 static struct omap_hwmod omap44xx_timer11_hwmod
= {
2572 .class = &omap44xx_timer_hwmod_class
,
2573 .clkdm_name
= "l4_per_clkdm",
2574 .mpu_irqs
= omap44xx_timer11_irqs
,
2575 .main_clk
= "timer11_fck",
2578 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET
,
2579 .context_offs
= OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET
,
2580 .modulemode
= MODULEMODE_SWCTRL
,
2583 .dev_attr
= &capability_pwm_dev_attr
,
2588 * universal asynchronous receiver/transmitter (uart)
2591 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc
= {
2593 .sysc_offs
= 0x0054,
2594 .syss_offs
= 0x0058,
2595 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
2596 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
2597 SYSS_HAS_RESET_STATUS
),
2598 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2600 .sysc_fields
= &omap_hwmod_sysc_type1
,
2603 static struct omap_hwmod_class omap44xx_uart_hwmod_class
= {
2605 .sysc
= &omap44xx_uart_sysc
,
2609 static struct omap_hwmod_irq_info omap44xx_uart1_irqs
[] = {
2610 { .irq
= 72 + OMAP44XX_IRQ_GIC_START
},
2614 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs
[] = {
2615 { .name
= "tx", .dma_req
= 48 + OMAP44XX_DMA_REQ_START
},
2616 { .name
= "rx", .dma_req
= 49 + OMAP44XX_DMA_REQ_START
},
2620 static struct omap_hwmod omap44xx_uart1_hwmod
= {
2622 .class = &omap44xx_uart_hwmod_class
,
2623 .clkdm_name
= "l4_per_clkdm",
2624 .mpu_irqs
= omap44xx_uart1_irqs
,
2625 .sdma_reqs
= omap44xx_uart1_sdma_reqs
,
2626 .main_clk
= "uart1_fck",
2629 .clkctrl_offs
= OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET
,
2630 .context_offs
= OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET
,
2631 .modulemode
= MODULEMODE_SWCTRL
,
2637 static struct omap_hwmod_irq_info omap44xx_uart2_irqs
[] = {
2638 { .irq
= 73 + OMAP44XX_IRQ_GIC_START
},
2642 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs
[] = {
2643 { .name
= "tx", .dma_req
= 50 + OMAP44XX_DMA_REQ_START
},
2644 { .name
= "rx", .dma_req
= 51 + OMAP44XX_DMA_REQ_START
},
2648 static struct omap_hwmod omap44xx_uart2_hwmod
= {
2650 .class = &omap44xx_uart_hwmod_class
,
2651 .clkdm_name
= "l4_per_clkdm",
2652 .mpu_irqs
= omap44xx_uart2_irqs
,
2653 .sdma_reqs
= omap44xx_uart2_sdma_reqs
,
2654 .main_clk
= "uart2_fck",
2657 .clkctrl_offs
= OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET
,
2658 .context_offs
= OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET
,
2659 .modulemode
= MODULEMODE_SWCTRL
,
2665 static struct omap_hwmod_irq_info omap44xx_uart3_irqs
[] = {
2666 { .irq
= 74 + OMAP44XX_IRQ_GIC_START
},
2670 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs
[] = {
2671 { .name
= "tx", .dma_req
= 52 + OMAP44XX_DMA_REQ_START
},
2672 { .name
= "rx", .dma_req
= 53 + OMAP44XX_DMA_REQ_START
},
2676 static struct omap_hwmod omap44xx_uart3_hwmod
= {
2678 .class = &omap44xx_uart_hwmod_class
,
2679 .clkdm_name
= "l4_per_clkdm",
2680 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
2681 .mpu_irqs
= omap44xx_uart3_irqs
,
2682 .sdma_reqs
= omap44xx_uart3_sdma_reqs
,
2683 .main_clk
= "uart3_fck",
2686 .clkctrl_offs
= OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET
,
2687 .context_offs
= OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET
,
2688 .modulemode
= MODULEMODE_SWCTRL
,
2694 static struct omap_hwmod_irq_info omap44xx_uart4_irqs
[] = {
2695 { .irq
= 70 + OMAP44XX_IRQ_GIC_START
},
2699 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs
[] = {
2700 { .name
= "tx", .dma_req
= 54 + OMAP44XX_DMA_REQ_START
},
2701 { .name
= "rx", .dma_req
= 55 + OMAP44XX_DMA_REQ_START
},
2705 static struct omap_hwmod omap44xx_uart4_hwmod
= {
2707 .class = &omap44xx_uart_hwmod_class
,
2708 .clkdm_name
= "l4_per_clkdm",
2709 .mpu_irqs
= omap44xx_uart4_irqs
,
2710 .sdma_reqs
= omap44xx_uart4_sdma_reqs
,
2711 .main_clk
= "uart4_fck",
2714 .clkctrl_offs
= OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET
,
2715 .context_offs
= OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET
,
2716 .modulemode
= MODULEMODE_SWCTRL
,
2722 * 'usb_host_hs' class
2723 * high-speed multi-port usb host controller
2726 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc
= {
2728 .sysc_offs
= 0x0010,
2729 .syss_offs
= 0x0014,
2730 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
2731 SYSC_HAS_SOFTRESET
),
2732 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2733 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
2734 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
2735 .sysc_fields
= &omap_hwmod_sysc_type2
,
2738 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class
= {
2739 .name
= "usb_host_hs",
2740 .sysc
= &omap44xx_usb_host_hs_sysc
,
2744 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs
[] = {
2745 { .name
= "ohci-irq", .irq
= 76 + OMAP44XX_IRQ_GIC_START
},
2746 { .name
= "ehci-irq", .irq
= 77 + OMAP44XX_IRQ_GIC_START
},
2750 static struct omap_hwmod omap44xx_usb_host_hs_hwmod
= {
2751 .name
= "usb_host_hs",
2752 .class = &omap44xx_usb_host_hs_hwmod_class
,
2753 .clkdm_name
= "l3_init_clkdm",
2754 .main_clk
= "usb_host_hs_fck",
2757 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET
,
2758 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET
,
2759 .modulemode
= MODULEMODE_SWCTRL
,
2762 .mpu_irqs
= omap44xx_usb_host_hs_irqs
,
2765 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2769 * In the following configuration :
2770 * - USBHOST module is set to smart-idle mode
2771 * - PRCM asserts idle_req to the USBHOST module ( This typically
2772 * happens when the system is going to a low power mode : all ports
2773 * have been suspended, the master part of the USBHOST module has
2774 * entered the standby state, and SW has cut the functional clocks)
2775 * - an USBHOST interrupt occurs before the module is able to answer
2776 * idle_ack, typically a remote wakeup IRQ.
2777 * Then the USB HOST module will enter a deadlock situation where it
2778 * is no more accessible nor functional.
2781 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2785 * Errata: USB host EHCI may stall when entering smart-standby mode
2789 * When the USBHOST module is set to smart-standby mode, and when it is
2790 * ready to enter the standby state (i.e. all ports are suspended and
2791 * all attached devices are in suspend mode), then it can wrongly assert
2792 * the Mstandby signal too early while there are still some residual OCP
2793 * transactions ongoing. If this condition occurs, the internal state
2794 * machine may go to an undefined state and the USB link may be stuck
2795 * upon the next resume.
2798 * Don't use smart standby; use only force standby,
2799 * hence HWMOD_SWSUP_MSTANDBY
2803 * During system boot; If the hwmod framework resets the module
2804 * the module will have smart idle settings; which can lead to deadlock
2805 * (above Errata Id:i660); so, dont reset the module during boot;
2806 * Use HWMOD_INIT_NO_RESET.
2809 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
|
2810 HWMOD_INIT_NO_RESET
,
2814 * 'usb_otg_hs' class
2815 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
2818 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc
= {
2820 .sysc_offs
= 0x0404,
2821 .syss_offs
= 0x0408,
2822 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
2823 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
2824 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
2825 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2826 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
2828 .sysc_fields
= &omap_hwmod_sysc_type1
,
2831 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class
= {
2832 .name
= "usb_otg_hs",
2833 .sysc
= &omap44xx_usb_otg_hs_sysc
,
2837 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs
[] = {
2838 { .name
= "mc", .irq
= 92 + OMAP44XX_IRQ_GIC_START
},
2839 { .name
= "dma", .irq
= 93 + OMAP44XX_IRQ_GIC_START
},
2843 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks
[] = {
2844 { .role
= "xclk", .clk
= "usb_otg_hs_xclk" },
2847 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod
= {
2848 .name
= "usb_otg_hs",
2849 .class = &omap44xx_usb_otg_hs_hwmod_class
,
2850 .clkdm_name
= "l3_init_clkdm",
2851 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
2852 .mpu_irqs
= omap44xx_usb_otg_hs_irqs
,
2853 .main_clk
= "usb_otg_hs_ick",
2856 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET
,
2857 .context_offs
= OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET
,
2858 .modulemode
= MODULEMODE_HWCTRL
,
2861 .opt_clks
= usb_otg_hs_opt_clks
,
2862 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_hs_opt_clks
),
2866 * 'usb_tll_hs' class
2867 * usb_tll_hs module is the adapter on the usb_host_hs ports
2870 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc
= {
2872 .sysc_offs
= 0x0010,
2873 .syss_offs
= 0x0014,
2874 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
2875 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
2877 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2878 .sysc_fields
= &omap_hwmod_sysc_type1
,
2881 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class
= {
2882 .name
= "usb_tll_hs",
2883 .sysc
= &omap44xx_usb_tll_hs_sysc
,
2886 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs
[] = {
2887 { .name
= "tll-irq", .irq
= 78 + OMAP44XX_IRQ_GIC_START
},
2891 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod
= {
2892 .name
= "usb_tll_hs",
2893 .class = &omap44xx_usb_tll_hs_hwmod_class
,
2894 .clkdm_name
= "l3_init_clkdm",
2895 .mpu_irqs
= omap44xx_usb_tll_hs_irqs
,
2896 .main_clk
= "usb_tll_hs_ick",
2899 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET
,
2900 .context_offs
= OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET
,
2901 .modulemode
= MODULEMODE_HWCTRL
,
2908 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
2909 * overflow condition
2912 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc
= {
2914 .sysc_offs
= 0x0010,
2915 .syss_offs
= 0x0014,
2916 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
2917 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
2918 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2920 .sysc_fields
= &omap_hwmod_sysc_type1
,
2923 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class
= {
2925 .sysc
= &omap44xx_wd_timer_sysc
,
2926 .pre_shutdown
= &omap2_wd_timer_disable
,
2930 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs
[] = {
2931 { .irq
= 80 + OMAP44XX_IRQ_GIC_START
},
2935 static struct omap_hwmod omap44xx_wd_timer2_hwmod
= {
2936 .name
= "wd_timer2",
2937 .class = &omap44xx_wd_timer_hwmod_class
,
2938 .clkdm_name
= "l4_wkup_clkdm",
2939 .mpu_irqs
= omap44xx_wd_timer2_irqs
,
2940 .main_clk
= "wd_timer2_fck",
2943 .clkctrl_offs
= OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET
,
2944 .context_offs
= OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET
,
2945 .modulemode
= MODULEMODE_SWCTRL
,
2951 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs
[] = {
2952 { .irq
= 36 + OMAP44XX_IRQ_GIC_START
},
2956 static struct omap_hwmod omap44xx_wd_timer3_hwmod
= {
2957 .name
= "wd_timer3",
2958 .class = &omap44xx_wd_timer_hwmod_class
,
2959 .clkdm_name
= "abe_clkdm",
2960 .mpu_irqs
= omap44xx_wd_timer3_irqs
,
2961 .main_clk
= "wd_timer3_fck",
2964 .clkctrl_offs
= OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET
,
2965 .context_offs
= OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET
,
2966 .modulemode
= MODULEMODE_SWCTRL
,
2976 /* l3_main_1 -> dmm */
2977 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm
= {
2978 .master
= &omap44xx_l3_main_1_hwmod
,
2979 .slave
= &omap44xx_dmm_hwmod
,
2981 .user
= OCP_USER_SDMA
,
2984 static struct omap_hwmod_addr_space omap44xx_dmm_addrs
[] = {
2986 .pa_start
= 0x4e000000,
2987 .pa_end
= 0x4e0007ff,
2988 .flags
= ADDR_TYPE_RT
2994 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm
= {
2995 .master
= &omap44xx_mpu_hwmod
,
2996 .slave
= &omap44xx_dmm_hwmod
,
2998 .addr
= omap44xx_dmm_addrs
,
2999 .user
= OCP_USER_MPU
,
3002 /* dmm -> emif_fw */
3003 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw
= {
3004 .master
= &omap44xx_dmm_hwmod
,
3005 .slave
= &omap44xx_emif_fw_hwmod
,
3007 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3010 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs
[] = {
3012 .pa_start
= 0x4a20c000,
3013 .pa_end
= 0x4a20c0ff,
3014 .flags
= ADDR_TYPE_RT
3019 /* l4_cfg -> emif_fw */
3020 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw
= {
3021 .master
= &omap44xx_l4_cfg_hwmod
,
3022 .slave
= &omap44xx_emif_fw_hwmod
,
3024 .addr
= omap44xx_emif_fw_addrs
,
3025 .user
= OCP_USER_MPU
,
3028 /* iva -> l3_instr */
3029 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr
= {
3030 .master
= &omap44xx_iva_hwmod
,
3031 .slave
= &omap44xx_l3_instr_hwmod
,
3033 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3036 /* l3_main_3 -> l3_instr */
3037 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr
= {
3038 .master
= &omap44xx_l3_main_3_hwmod
,
3039 .slave
= &omap44xx_l3_instr_hwmod
,
3041 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3044 /* dsp -> l3_main_1 */
3045 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1
= {
3046 .master
= &omap44xx_dsp_hwmod
,
3047 .slave
= &omap44xx_l3_main_1_hwmod
,
3049 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3052 /* dss -> l3_main_1 */
3053 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1
= {
3054 .master
= &omap44xx_dss_hwmod
,
3055 .slave
= &omap44xx_l3_main_1_hwmod
,
3057 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3060 /* l3_main_2 -> l3_main_1 */
3061 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1
= {
3062 .master
= &omap44xx_l3_main_2_hwmod
,
3063 .slave
= &omap44xx_l3_main_1_hwmod
,
3065 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3068 /* l4_cfg -> l3_main_1 */
3069 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1
= {
3070 .master
= &omap44xx_l4_cfg_hwmod
,
3071 .slave
= &omap44xx_l3_main_1_hwmod
,
3073 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3076 /* mmc1 -> l3_main_1 */
3077 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1
= {
3078 .master
= &omap44xx_mmc1_hwmod
,
3079 .slave
= &omap44xx_l3_main_1_hwmod
,
3081 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3084 /* mmc2 -> l3_main_1 */
3085 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1
= {
3086 .master
= &omap44xx_mmc2_hwmod
,
3087 .slave
= &omap44xx_l3_main_1_hwmod
,
3089 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3092 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs
[] = {
3094 .pa_start
= 0x44000000,
3095 .pa_end
= 0x44000fff,
3096 .flags
= ADDR_TYPE_RT
3101 /* mpu -> l3_main_1 */
3102 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1
= {
3103 .master
= &omap44xx_mpu_hwmod
,
3104 .slave
= &omap44xx_l3_main_1_hwmod
,
3106 .addr
= omap44xx_l3_main_1_addrs
,
3107 .user
= OCP_USER_MPU
,
3110 /* dma_system -> l3_main_2 */
3111 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2
= {
3112 .master
= &omap44xx_dma_system_hwmod
,
3113 .slave
= &omap44xx_l3_main_2_hwmod
,
3115 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3118 /* fdif -> l3_main_2 */
3119 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2
= {
3120 .master
= &omap44xx_fdif_hwmod
,
3121 .slave
= &omap44xx_l3_main_2_hwmod
,
3123 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3126 /* hsi -> l3_main_2 */
3127 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2
= {
3128 .master
= &omap44xx_hsi_hwmod
,
3129 .slave
= &omap44xx_l3_main_2_hwmod
,
3131 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3134 /* ipu -> l3_main_2 */
3135 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2
= {
3136 .master
= &omap44xx_ipu_hwmod
,
3137 .slave
= &omap44xx_l3_main_2_hwmod
,
3139 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3142 /* iss -> l3_main_2 */
3143 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2
= {
3144 .master
= &omap44xx_iss_hwmod
,
3145 .slave
= &omap44xx_l3_main_2_hwmod
,
3147 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3150 /* iva -> l3_main_2 */
3151 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2
= {
3152 .master
= &omap44xx_iva_hwmod
,
3153 .slave
= &omap44xx_l3_main_2_hwmod
,
3155 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3158 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs
[] = {
3160 .pa_start
= 0x44800000,
3161 .pa_end
= 0x44801fff,
3162 .flags
= ADDR_TYPE_RT
3167 /* l3_main_1 -> l3_main_2 */
3168 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2
= {
3169 .master
= &omap44xx_l3_main_1_hwmod
,
3170 .slave
= &omap44xx_l3_main_2_hwmod
,
3172 .addr
= omap44xx_l3_main_2_addrs
,
3173 .user
= OCP_USER_MPU
,
3176 /* l4_cfg -> l3_main_2 */
3177 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2
= {
3178 .master
= &omap44xx_l4_cfg_hwmod
,
3179 .slave
= &omap44xx_l3_main_2_hwmod
,
3181 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3184 /* usb_host_hs -> l3_main_2 */
3185 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2
= {
3186 .master
= &omap44xx_usb_host_hs_hwmod
,
3187 .slave
= &omap44xx_l3_main_2_hwmod
,
3189 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3192 /* usb_otg_hs -> l3_main_2 */
3193 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2
= {
3194 .master
= &omap44xx_usb_otg_hs_hwmod
,
3195 .slave
= &omap44xx_l3_main_2_hwmod
,
3197 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3200 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs
[] = {
3202 .pa_start
= 0x45000000,
3203 .pa_end
= 0x45000fff,
3204 .flags
= ADDR_TYPE_RT
3209 /* l3_main_1 -> l3_main_3 */
3210 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3
= {
3211 .master
= &omap44xx_l3_main_1_hwmod
,
3212 .slave
= &omap44xx_l3_main_3_hwmod
,
3214 .addr
= omap44xx_l3_main_3_addrs
,
3215 .user
= OCP_USER_MPU
,
3218 /* l3_main_2 -> l3_main_3 */
3219 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3
= {
3220 .master
= &omap44xx_l3_main_2_hwmod
,
3221 .slave
= &omap44xx_l3_main_3_hwmod
,
3223 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3226 /* l4_cfg -> l3_main_3 */
3227 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3
= {
3228 .master
= &omap44xx_l4_cfg_hwmod
,
3229 .slave
= &omap44xx_l3_main_3_hwmod
,
3231 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3234 /* aess -> l4_abe */
3235 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe
= {
3236 .master
= &omap44xx_aess_hwmod
,
3237 .slave
= &omap44xx_l4_abe_hwmod
,
3238 .clk
= "ocp_abe_iclk",
3239 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3243 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe
= {
3244 .master
= &omap44xx_dsp_hwmod
,
3245 .slave
= &omap44xx_l4_abe_hwmod
,
3246 .clk
= "ocp_abe_iclk",
3247 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3250 /* l3_main_1 -> l4_abe */
3251 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe
= {
3252 .master
= &omap44xx_l3_main_1_hwmod
,
3253 .slave
= &omap44xx_l4_abe_hwmod
,
3255 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3259 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe
= {
3260 .master
= &omap44xx_mpu_hwmod
,
3261 .slave
= &omap44xx_l4_abe_hwmod
,
3262 .clk
= "ocp_abe_iclk",
3263 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3266 /* l3_main_1 -> l4_cfg */
3267 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg
= {
3268 .master
= &omap44xx_l3_main_1_hwmod
,
3269 .slave
= &omap44xx_l4_cfg_hwmod
,
3271 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3274 /* l3_main_2 -> l4_per */
3275 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per
= {
3276 .master
= &omap44xx_l3_main_2_hwmod
,
3277 .slave
= &omap44xx_l4_per_hwmod
,
3279 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3282 /* l4_cfg -> l4_wkup */
3283 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup
= {
3284 .master
= &omap44xx_l4_cfg_hwmod
,
3285 .slave
= &omap44xx_l4_wkup_hwmod
,
3287 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3290 /* mpu -> mpu_private */
3291 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private
= {
3292 .master
= &omap44xx_mpu_hwmod
,
3293 .slave
= &omap44xx_mpu_private_hwmod
,
3295 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3298 static struct omap_hwmod_addr_space omap44xx_aess_addrs
[] = {
3300 .pa_start
= 0x401f1000,
3301 .pa_end
= 0x401f13ff,
3302 .flags
= ADDR_TYPE_RT
3307 /* l4_abe -> aess */
3308 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess
= {
3309 .master
= &omap44xx_l4_abe_hwmod
,
3310 .slave
= &omap44xx_aess_hwmod
,
3311 .clk
= "ocp_abe_iclk",
3312 .addr
= omap44xx_aess_addrs
,
3313 .user
= OCP_USER_MPU
,
3316 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs
[] = {
3318 .pa_start
= 0x490f1000,
3319 .pa_end
= 0x490f13ff,
3320 .flags
= ADDR_TYPE_RT
3325 /* l4_abe -> aess (dma) */
3326 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma
= {
3327 .master
= &omap44xx_l4_abe_hwmod
,
3328 .slave
= &omap44xx_aess_hwmod
,
3329 .clk
= "ocp_abe_iclk",
3330 .addr
= omap44xx_aess_dma_addrs
,
3331 .user
= OCP_USER_SDMA
,
3334 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs
[] = {
3336 .pa_start
= 0x4a304000,
3337 .pa_end
= 0x4a30401f,
3338 .flags
= ADDR_TYPE_RT
3343 /* l4_wkup -> counter_32k */
3344 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k
= {
3345 .master
= &omap44xx_l4_wkup_hwmod
,
3346 .slave
= &omap44xx_counter_32k_hwmod
,
3347 .clk
= "l4_wkup_clk_mux_ck",
3348 .addr
= omap44xx_counter_32k_addrs
,
3349 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3352 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs
[] = {
3354 .pa_start
= 0x4a056000,
3355 .pa_end
= 0x4a056fff,
3356 .flags
= ADDR_TYPE_RT
3361 /* l4_cfg -> dma_system */
3362 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system
= {
3363 .master
= &omap44xx_l4_cfg_hwmod
,
3364 .slave
= &omap44xx_dma_system_hwmod
,
3366 .addr
= omap44xx_dma_system_addrs
,
3367 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3370 static struct omap_hwmod_addr_space omap44xx_dmic_addrs
[] = {
3373 .pa_start
= 0x4012e000,
3374 .pa_end
= 0x4012e07f,
3375 .flags
= ADDR_TYPE_RT
3380 /* l4_abe -> dmic */
3381 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic
= {
3382 .master
= &omap44xx_l4_abe_hwmod
,
3383 .slave
= &omap44xx_dmic_hwmod
,
3384 .clk
= "ocp_abe_iclk",
3385 .addr
= omap44xx_dmic_addrs
,
3386 .user
= OCP_USER_MPU
,
3389 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs
[] = {
3392 .pa_start
= 0x4902e000,
3393 .pa_end
= 0x4902e07f,
3394 .flags
= ADDR_TYPE_RT
3399 /* l4_abe -> dmic (dma) */
3400 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma
= {
3401 .master
= &omap44xx_l4_abe_hwmod
,
3402 .slave
= &omap44xx_dmic_hwmod
,
3403 .clk
= "ocp_abe_iclk",
3404 .addr
= omap44xx_dmic_dma_addrs
,
3405 .user
= OCP_USER_SDMA
,
3409 static struct omap_hwmod_ocp_if omap44xx_dsp__iva
= {
3410 .master
= &omap44xx_dsp_hwmod
,
3411 .slave
= &omap44xx_iva_hwmod
,
3412 .clk
= "dpll_iva_m5x2_ck",
3413 .user
= OCP_USER_DSP
,
3417 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp
= {
3418 .master
= &omap44xx_l4_cfg_hwmod
,
3419 .slave
= &omap44xx_dsp_hwmod
,
3421 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3424 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs
[] = {
3426 .pa_start
= 0x58000000,
3427 .pa_end
= 0x5800007f,
3428 .flags
= ADDR_TYPE_RT
3433 /* l3_main_2 -> dss */
3434 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss
= {
3435 .master
= &omap44xx_l3_main_2_hwmod
,
3436 .slave
= &omap44xx_dss_hwmod
,
3438 .addr
= omap44xx_dss_dma_addrs
,
3439 .user
= OCP_USER_SDMA
,
3442 static struct omap_hwmod_addr_space omap44xx_dss_addrs
[] = {
3444 .pa_start
= 0x48040000,
3445 .pa_end
= 0x4804007f,
3446 .flags
= ADDR_TYPE_RT
3452 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss
= {
3453 .master
= &omap44xx_l4_per_hwmod
,
3454 .slave
= &omap44xx_dss_hwmod
,
3456 .addr
= omap44xx_dss_addrs
,
3457 .user
= OCP_USER_MPU
,
3460 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs
[] = {
3462 .pa_start
= 0x58001000,
3463 .pa_end
= 0x58001fff,
3464 .flags
= ADDR_TYPE_RT
3469 /* l3_main_2 -> dss_dispc */
3470 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc
= {
3471 .master
= &omap44xx_l3_main_2_hwmod
,
3472 .slave
= &omap44xx_dss_dispc_hwmod
,
3474 .addr
= omap44xx_dss_dispc_dma_addrs
,
3475 .user
= OCP_USER_SDMA
,
3478 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs
[] = {
3480 .pa_start
= 0x48041000,
3481 .pa_end
= 0x48041fff,
3482 .flags
= ADDR_TYPE_RT
3487 /* l4_per -> dss_dispc */
3488 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc
= {
3489 .master
= &omap44xx_l4_per_hwmod
,
3490 .slave
= &omap44xx_dss_dispc_hwmod
,
3492 .addr
= omap44xx_dss_dispc_addrs
,
3493 .user
= OCP_USER_MPU
,
3496 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs
[] = {
3498 .pa_start
= 0x58004000,
3499 .pa_end
= 0x580041ff,
3500 .flags
= ADDR_TYPE_RT
3505 /* l3_main_2 -> dss_dsi1 */
3506 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1
= {
3507 .master
= &omap44xx_l3_main_2_hwmod
,
3508 .slave
= &omap44xx_dss_dsi1_hwmod
,
3510 .addr
= omap44xx_dss_dsi1_dma_addrs
,
3511 .user
= OCP_USER_SDMA
,
3514 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs
[] = {
3516 .pa_start
= 0x48044000,
3517 .pa_end
= 0x480441ff,
3518 .flags
= ADDR_TYPE_RT
3523 /* l4_per -> dss_dsi1 */
3524 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1
= {
3525 .master
= &omap44xx_l4_per_hwmod
,
3526 .slave
= &omap44xx_dss_dsi1_hwmod
,
3528 .addr
= omap44xx_dss_dsi1_addrs
,
3529 .user
= OCP_USER_MPU
,
3532 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs
[] = {
3534 .pa_start
= 0x58005000,
3535 .pa_end
= 0x580051ff,
3536 .flags
= ADDR_TYPE_RT
3541 /* l3_main_2 -> dss_dsi2 */
3542 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2
= {
3543 .master
= &omap44xx_l3_main_2_hwmod
,
3544 .slave
= &omap44xx_dss_dsi2_hwmod
,
3546 .addr
= omap44xx_dss_dsi2_dma_addrs
,
3547 .user
= OCP_USER_SDMA
,
3550 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs
[] = {
3552 .pa_start
= 0x48045000,
3553 .pa_end
= 0x480451ff,
3554 .flags
= ADDR_TYPE_RT
3559 /* l4_per -> dss_dsi2 */
3560 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2
= {
3561 .master
= &omap44xx_l4_per_hwmod
,
3562 .slave
= &omap44xx_dss_dsi2_hwmod
,
3564 .addr
= omap44xx_dss_dsi2_addrs
,
3565 .user
= OCP_USER_MPU
,
3568 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs
[] = {
3570 .pa_start
= 0x58006000,
3571 .pa_end
= 0x58006fff,
3572 .flags
= ADDR_TYPE_RT
3577 /* l3_main_2 -> dss_hdmi */
3578 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi
= {
3579 .master
= &omap44xx_l3_main_2_hwmod
,
3580 .slave
= &omap44xx_dss_hdmi_hwmod
,
3582 .addr
= omap44xx_dss_hdmi_dma_addrs
,
3583 .user
= OCP_USER_SDMA
,
3586 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs
[] = {
3588 .pa_start
= 0x48046000,
3589 .pa_end
= 0x48046fff,
3590 .flags
= ADDR_TYPE_RT
3595 /* l4_per -> dss_hdmi */
3596 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi
= {
3597 .master
= &omap44xx_l4_per_hwmod
,
3598 .slave
= &omap44xx_dss_hdmi_hwmod
,
3600 .addr
= omap44xx_dss_hdmi_addrs
,
3601 .user
= OCP_USER_MPU
,
3604 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs
[] = {
3606 .pa_start
= 0x58002000,
3607 .pa_end
= 0x580020ff,
3608 .flags
= ADDR_TYPE_RT
3613 /* l3_main_2 -> dss_rfbi */
3614 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi
= {
3615 .master
= &omap44xx_l3_main_2_hwmod
,
3616 .slave
= &omap44xx_dss_rfbi_hwmod
,
3618 .addr
= omap44xx_dss_rfbi_dma_addrs
,
3619 .user
= OCP_USER_SDMA
,
3622 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs
[] = {
3624 .pa_start
= 0x48042000,
3625 .pa_end
= 0x480420ff,
3626 .flags
= ADDR_TYPE_RT
3631 /* l4_per -> dss_rfbi */
3632 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi
= {
3633 .master
= &omap44xx_l4_per_hwmod
,
3634 .slave
= &omap44xx_dss_rfbi_hwmod
,
3636 .addr
= omap44xx_dss_rfbi_addrs
,
3637 .user
= OCP_USER_MPU
,
3640 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs
[] = {
3642 .pa_start
= 0x58003000,
3643 .pa_end
= 0x580030ff,
3644 .flags
= ADDR_TYPE_RT
3649 /* l3_main_2 -> dss_venc */
3650 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc
= {
3651 .master
= &omap44xx_l3_main_2_hwmod
,
3652 .slave
= &omap44xx_dss_venc_hwmod
,
3654 .addr
= omap44xx_dss_venc_dma_addrs
,
3655 .user
= OCP_USER_SDMA
,
3658 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs
[] = {
3660 .pa_start
= 0x48043000,
3661 .pa_end
= 0x480430ff,
3662 .flags
= ADDR_TYPE_RT
3667 /* l4_per -> dss_venc */
3668 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc
= {
3669 .master
= &omap44xx_l4_per_hwmod
,
3670 .slave
= &omap44xx_dss_venc_hwmod
,
3672 .addr
= omap44xx_dss_venc_addrs
,
3673 .user
= OCP_USER_MPU
,
3676 static struct omap_hwmod_addr_space omap44xx_fdif_addrs
[] = {
3678 .pa_start
= 0x4a10a000,
3679 .pa_end
= 0x4a10a1ff,
3680 .flags
= ADDR_TYPE_RT
3685 /* l4_cfg -> fdif */
3686 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif
= {
3687 .master
= &omap44xx_l4_cfg_hwmod
,
3688 .slave
= &omap44xx_fdif_hwmod
,
3690 .addr
= omap44xx_fdif_addrs
,
3691 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3694 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs
[] = {
3696 .pa_start
= 0x4a310000,
3697 .pa_end
= 0x4a3101ff,
3698 .flags
= ADDR_TYPE_RT
3703 /* l4_wkup -> gpio1 */
3704 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1
= {
3705 .master
= &omap44xx_l4_wkup_hwmod
,
3706 .slave
= &omap44xx_gpio1_hwmod
,
3707 .clk
= "l4_wkup_clk_mux_ck",
3708 .addr
= omap44xx_gpio1_addrs
,
3709 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3712 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs
[] = {
3714 .pa_start
= 0x48055000,
3715 .pa_end
= 0x480551ff,
3716 .flags
= ADDR_TYPE_RT
3721 /* l4_per -> gpio2 */
3722 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2
= {
3723 .master
= &omap44xx_l4_per_hwmod
,
3724 .slave
= &omap44xx_gpio2_hwmod
,
3726 .addr
= omap44xx_gpio2_addrs
,
3727 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3730 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs
[] = {
3732 .pa_start
= 0x48057000,
3733 .pa_end
= 0x480571ff,
3734 .flags
= ADDR_TYPE_RT
3739 /* l4_per -> gpio3 */
3740 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3
= {
3741 .master
= &omap44xx_l4_per_hwmod
,
3742 .slave
= &omap44xx_gpio3_hwmod
,
3744 .addr
= omap44xx_gpio3_addrs
,
3745 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3748 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs
[] = {
3750 .pa_start
= 0x48059000,
3751 .pa_end
= 0x480591ff,
3752 .flags
= ADDR_TYPE_RT
3757 /* l4_per -> gpio4 */
3758 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4
= {
3759 .master
= &omap44xx_l4_per_hwmod
,
3760 .slave
= &omap44xx_gpio4_hwmod
,
3762 .addr
= omap44xx_gpio4_addrs
,
3763 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3766 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs
[] = {
3768 .pa_start
= 0x4805b000,
3769 .pa_end
= 0x4805b1ff,
3770 .flags
= ADDR_TYPE_RT
3775 /* l4_per -> gpio5 */
3776 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5
= {
3777 .master
= &omap44xx_l4_per_hwmod
,
3778 .slave
= &omap44xx_gpio5_hwmod
,
3780 .addr
= omap44xx_gpio5_addrs
,
3781 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3784 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs
[] = {
3786 .pa_start
= 0x4805d000,
3787 .pa_end
= 0x4805d1ff,
3788 .flags
= ADDR_TYPE_RT
3793 /* l4_per -> gpio6 */
3794 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6
= {
3795 .master
= &omap44xx_l4_per_hwmod
,
3796 .slave
= &omap44xx_gpio6_hwmod
,
3798 .addr
= omap44xx_gpio6_addrs
,
3799 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3802 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs
[] = {
3804 .pa_start
= 0x50000000,
3805 .pa_end
= 0x500003ff,
3806 .flags
= ADDR_TYPE_RT
3811 /* l3_main_2 -> gpmc */
3812 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc
= {
3813 .master
= &omap44xx_l3_main_2_hwmod
,
3814 .slave
= &omap44xx_gpmc_hwmod
,
3816 .addr
= omap44xx_gpmc_addrs
,
3817 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3820 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs
[] = {
3822 .pa_start
= 0x480b2000,
3823 .pa_end
= 0x480b201f,
3824 .flags
= ADDR_TYPE_RT
3829 /* l4_per -> hdq1w */
3830 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w
= {
3831 .master
= &omap44xx_l4_per_hwmod
,
3832 .slave
= &omap44xx_hdq1w_hwmod
,
3834 .addr
= omap44xx_hdq1w_addrs
,
3835 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3838 static struct omap_hwmod_addr_space omap44xx_hsi_addrs
[] = {
3840 .pa_start
= 0x4a058000,
3841 .pa_end
= 0x4a05bfff,
3842 .flags
= ADDR_TYPE_RT
3848 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi
= {
3849 .master
= &omap44xx_l4_cfg_hwmod
,
3850 .slave
= &omap44xx_hsi_hwmod
,
3852 .addr
= omap44xx_hsi_addrs
,
3853 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3856 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs
[] = {
3858 .pa_start
= 0x48070000,
3859 .pa_end
= 0x480700ff,
3860 .flags
= ADDR_TYPE_RT
3865 /* l4_per -> i2c1 */
3866 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1
= {
3867 .master
= &omap44xx_l4_per_hwmod
,
3868 .slave
= &omap44xx_i2c1_hwmod
,
3870 .addr
= omap44xx_i2c1_addrs
,
3871 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3874 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs
[] = {
3876 .pa_start
= 0x48072000,
3877 .pa_end
= 0x480720ff,
3878 .flags
= ADDR_TYPE_RT
3883 /* l4_per -> i2c2 */
3884 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2
= {
3885 .master
= &omap44xx_l4_per_hwmod
,
3886 .slave
= &omap44xx_i2c2_hwmod
,
3888 .addr
= omap44xx_i2c2_addrs
,
3889 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3892 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs
[] = {
3894 .pa_start
= 0x48060000,
3895 .pa_end
= 0x480600ff,
3896 .flags
= ADDR_TYPE_RT
3901 /* l4_per -> i2c3 */
3902 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3
= {
3903 .master
= &omap44xx_l4_per_hwmod
,
3904 .slave
= &omap44xx_i2c3_hwmod
,
3906 .addr
= omap44xx_i2c3_addrs
,
3907 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3910 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs
[] = {
3912 .pa_start
= 0x48350000,
3913 .pa_end
= 0x483500ff,
3914 .flags
= ADDR_TYPE_RT
3919 /* l4_per -> i2c4 */
3920 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4
= {
3921 .master
= &omap44xx_l4_per_hwmod
,
3922 .slave
= &omap44xx_i2c4_hwmod
,
3924 .addr
= omap44xx_i2c4_addrs
,
3925 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3928 /* l3_main_2 -> ipu */
3929 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu
= {
3930 .master
= &omap44xx_l3_main_2_hwmod
,
3931 .slave
= &omap44xx_ipu_hwmod
,
3933 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3936 static struct omap_hwmod_addr_space omap44xx_iss_addrs
[] = {
3938 .pa_start
= 0x52000000,
3939 .pa_end
= 0x520000ff,
3940 .flags
= ADDR_TYPE_RT
3945 /* l3_main_2 -> iss */
3946 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss
= {
3947 .master
= &omap44xx_l3_main_2_hwmod
,
3948 .slave
= &omap44xx_iss_hwmod
,
3950 .addr
= omap44xx_iss_addrs
,
3951 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3954 static struct omap_hwmod_addr_space omap44xx_iva_addrs
[] = {
3956 .pa_start
= 0x5a000000,
3957 .pa_end
= 0x5a07ffff,
3958 .flags
= ADDR_TYPE_RT
3963 /* l3_main_2 -> iva */
3964 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva
= {
3965 .master
= &omap44xx_l3_main_2_hwmod
,
3966 .slave
= &omap44xx_iva_hwmod
,
3968 .addr
= omap44xx_iva_addrs
,
3969 .user
= OCP_USER_MPU
,
3972 static struct omap_hwmod_addr_space omap44xx_kbd_addrs
[] = {
3974 .pa_start
= 0x4a31c000,
3975 .pa_end
= 0x4a31c07f,
3976 .flags
= ADDR_TYPE_RT
3981 /* l4_wkup -> kbd */
3982 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd
= {
3983 .master
= &omap44xx_l4_wkup_hwmod
,
3984 .slave
= &omap44xx_kbd_hwmod
,
3985 .clk
= "l4_wkup_clk_mux_ck",
3986 .addr
= omap44xx_kbd_addrs
,
3987 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3990 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs
[] = {
3992 .pa_start
= 0x4a0f4000,
3993 .pa_end
= 0x4a0f41ff,
3994 .flags
= ADDR_TYPE_RT
3999 /* l4_cfg -> mailbox */
4000 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox
= {
4001 .master
= &omap44xx_l4_cfg_hwmod
,
4002 .slave
= &omap44xx_mailbox_hwmod
,
4004 .addr
= omap44xx_mailbox_addrs
,
4005 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4008 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs
[] = {
4011 .pa_start
= 0x40122000,
4012 .pa_end
= 0x401220ff,
4013 .flags
= ADDR_TYPE_RT
4018 /* l4_abe -> mcbsp1 */
4019 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1
= {
4020 .master
= &omap44xx_l4_abe_hwmod
,
4021 .slave
= &omap44xx_mcbsp1_hwmod
,
4022 .clk
= "ocp_abe_iclk",
4023 .addr
= omap44xx_mcbsp1_addrs
,
4024 .user
= OCP_USER_MPU
,
4027 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs
[] = {
4030 .pa_start
= 0x49022000,
4031 .pa_end
= 0x490220ff,
4032 .flags
= ADDR_TYPE_RT
4037 /* l4_abe -> mcbsp1 (dma) */
4038 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma
= {
4039 .master
= &omap44xx_l4_abe_hwmod
,
4040 .slave
= &omap44xx_mcbsp1_hwmod
,
4041 .clk
= "ocp_abe_iclk",
4042 .addr
= omap44xx_mcbsp1_dma_addrs
,
4043 .user
= OCP_USER_SDMA
,
4046 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs
[] = {
4049 .pa_start
= 0x40124000,
4050 .pa_end
= 0x401240ff,
4051 .flags
= ADDR_TYPE_RT
4056 /* l4_abe -> mcbsp2 */
4057 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2
= {
4058 .master
= &omap44xx_l4_abe_hwmod
,
4059 .slave
= &omap44xx_mcbsp2_hwmod
,
4060 .clk
= "ocp_abe_iclk",
4061 .addr
= omap44xx_mcbsp2_addrs
,
4062 .user
= OCP_USER_MPU
,
4065 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs
[] = {
4068 .pa_start
= 0x49024000,
4069 .pa_end
= 0x490240ff,
4070 .flags
= ADDR_TYPE_RT
4075 /* l4_abe -> mcbsp2 (dma) */
4076 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma
= {
4077 .master
= &omap44xx_l4_abe_hwmod
,
4078 .slave
= &omap44xx_mcbsp2_hwmod
,
4079 .clk
= "ocp_abe_iclk",
4080 .addr
= omap44xx_mcbsp2_dma_addrs
,
4081 .user
= OCP_USER_SDMA
,
4084 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs
[] = {
4087 .pa_start
= 0x40126000,
4088 .pa_end
= 0x401260ff,
4089 .flags
= ADDR_TYPE_RT
4094 /* l4_abe -> mcbsp3 */
4095 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3
= {
4096 .master
= &omap44xx_l4_abe_hwmod
,
4097 .slave
= &omap44xx_mcbsp3_hwmod
,
4098 .clk
= "ocp_abe_iclk",
4099 .addr
= omap44xx_mcbsp3_addrs
,
4100 .user
= OCP_USER_MPU
,
4103 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs
[] = {
4106 .pa_start
= 0x49026000,
4107 .pa_end
= 0x490260ff,
4108 .flags
= ADDR_TYPE_RT
4113 /* l4_abe -> mcbsp3 (dma) */
4114 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma
= {
4115 .master
= &omap44xx_l4_abe_hwmod
,
4116 .slave
= &omap44xx_mcbsp3_hwmod
,
4117 .clk
= "ocp_abe_iclk",
4118 .addr
= omap44xx_mcbsp3_dma_addrs
,
4119 .user
= OCP_USER_SDMA
,
4122 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs
[] = {
4124 .pa_start
= 0x48096000,
4125 .pa_end
= 0x480960ff,
4126 .flags
= ADDR_TYPE_RT
4131 /* l4_per -> mcbsp4 */
4132 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4
= {
4133 .master
= &omap44xx_l4_per_hwmod
,
4134 .slave
= &omap44xx_mcbsp4_hwmod
,
4136 .addr
= omap44xx_mcbsp4_addrs
,
4137 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4140 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs
[] = {
4142 .pa_start
= 0x40132000,
4143 .pa_end
= 0x4013207f,
4144 .flags
= ADDR_TYPE_RT
4149 /* l4_abe -> mcpdm */
4150 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm
= {
4151 .master
= &omap44xx_l4_abe_hwmod
,
4152 .slave
= &omap44xx_mcpdm_hwmod
,
4153 .clk
= "ocp_abe_iclk",
4154 .addr
= omap44xx_mcpdm_addrs
,
4155 .user
= OCP_USER_MPU
,
4158 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs
[] = {
4160 .pa_start
= 0x49032000,
4161 .pa_end
= 0x4903207f,
4162 .flags
= ADDR_TYPE_RT
4167 /* l4_abe -> mcpdm (dma) */
4168 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma
= {
4169 .master
= &omap44xx_l4_abe_hwmod
,
4170 .slave
= &omap44xx_mcpdm_hwmod
,
4171 .clk
= "ocp_abe_iclk",
4172 .addr
= omap44xx_mcpdm_dma_addrs
,
4173 .user
= OCP_USER_SDMA
,
4176 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs
[] = {
4178 .pa_start
= 0x48098000,
4179 .pa_end
= 0x480981ff,
4180 .flags
= ADDR_TYPE_RT
4185 /* l4_per -> mcspi1 */
4186 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1
= {
4187 .master
= &omap44xx_l4_per_hwmod
,
4188 .slave
= &omap44xx_mcspi1_hwmod
,
4190 .addr
= omap44xx_mcspi1_addrs
,
4191 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4194 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs
[] = {
4196 .pa_start
= 0x4809a000,
4197 .pa_end
= 0x4809a1ff,
4198 .flags
= ADDR_TYPE_RT
4203 /* l4_per -> mcspi2 */
4204 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2
= {
4205 .master
= &omap44xx_l4_per_hwmod
,
4206 .slave
= &omap44xx_mcspi2_hwmod
,
4208 .addr
= omap44xx_mcspi2_addrs
,
4209 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4212 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs
[] = {
4214 .pa_start
= 0x480b8000,
4215 .pa_end
= 0x480b81ff,
4216 .flags
= ADDR_TYPE_RT
4221 /* l4_per -> mcspi3 */
4222 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3
= {
4223 .master
= &omap44xx_l4_per_hwmod
,
4224 .slave
= &omap44xx_mcspi3_hwmod
,
4226 .addr
= omap44xx_mcspi3_addrs
,
4227 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4230 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs
[] = {
4232 .pa_start
= 0x480ba000,
4233 .pa_end
= 0x480ba1ff,
4234 .flags
= ADDR_TYPE_RT
4239 /* l4_per -> mcspi4 */
4240 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4
= {
4241 .master
= &omap44xx_l4_per_hwmod
,
4242 .slave
= &omap44xx_mcspi4_hwmod
,
4244 .addr
= omap44xx_mcspi4_addrs
,
4245 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4248 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs
[] = {
4250 .pa_start
= 0x4809c000,
4251 .pa_end
= 0x4809c3ff,
4252 .flags
= ADDR_TYPE_RT
4257 /* l4_per -> mmc1 */
4258 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1
= {
4259 .master
= &omap44xx_l4_per_hwmod
,
4260 .slave
= &omap44xx_mmc1_hwmod
,
4262 .addr
= omap44xx_mmc1_addrs
,
4263 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4266 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs
[] = {
4268 .pa_start
= 0x480b4000,
4269 .pa_end
= 0x480b43ff,
4270 .flags
= ADDR_TYPE_RT
4275 /* l4_per -> mmc2 */
4276 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2
= {
4277 .master
= &omap44xx_l4_per_hwmod
,
4278 .slave
= &omap44xx_mmc2_hwmod
,
4280 .addr
= omap44xx_mmc2_addrs
,
4281 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4284 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs
[] = {
4286 .pa_start
= 0x480ad000,
4287 .pa_end
= 0x480ad3ff,
4288 .flags
= ADDR_TYPE_RT
4293 /* l4_per -> mmc3 */
4294 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3
= {
4295 .master
= &omap44xx_l4_per_hwmod
,
4296 .slave
= &omap44xx_mmc3_hwmod
,
4298 .addr
= omap44xx_mmc3_addrs
,
4299 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4302 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs
[] = {
4304 .pa_start
= 0x480d1000,
4305 .pa_end
= 0x480d13ff,
4306 .flags
= ADDR_TYPE_RT
4311 /* l4_per -> mmc4 */
4312 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4
= {
4313 .master
= &omap44xx_l4_per_hwmod
,
4314 .slave
= &omap44xx_mmc4_hwmod
,
4316 .addr
= omap44xx_mmc4_addrs
,
4317 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4320 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs
[] = {
4322 .pa_start
= 0x480d5000,
4323 .pa_end
= 0x480d53ff,
4324 .flags
= ADDR_TYPE_RT
4329 /* l4_per -> mmc5 */
4330 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5
= {
4331 .master
= &omap44xx_l4_per_hwmod
,
4332 .slave
= &omap44xx_mmc5_hwmod
,
4334 .addr
= omap44xx_mmc5_addrs
,
4335 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4338 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs
[] = {
4340 .pa_start
= 0x4a0dd000,
4341 .pa_end
= 0x4a0dd03f,
4342 .flags
= ADDR_TYPE_RT
4347 /* l4_cfg -> smartreflex_core */
4348 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core
= {
4349 .master
= &omap44xx_l4_cfg_hwmod
,
4350 .slave
= &omap44xx_smartreflex_core_hwmod
,
4352 .addr
= omap44xx_smartreflex_core_addrs
,
4353 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4356 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs
[] = {
4358 .pa_start
= 0x4a0db000,
4359 .pa_end
= 0x4a0db03f,
4360 .flags
= ADDR_TYPE_RT
4365 /* l4_cfg -> smartreflex_iva */
4366 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva
= {
4367 .master
= &omap44xx_l4_cfg_hwmod
,
4368 .slave
= &omap44xx_smartreflex_iva_hwmod
,
4370 .addr
= omap44xx_smartreflex_iva_addrs
,
4371 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4374 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs
[] = {
4376 .pa_start
= 0x4a0d9000,
4377 .pa_end
= 0x4a0d903f,
4378 .flags
= ADDR_TYPE_RT
4383 /* l4_cfg -> smartreflex_mpu */
4384 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu
= {
4385 .master
= &omap44xx_l4_cfg_hwmod
,
4386 .slave
= &omap44xx_smartreflex_mpu_hwmod
,
4388 .addr
= omap44xx_smartreflex_mpu_addrs
,
4389 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4392 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs
[] = {
4394 .pa_start
= 0x4a0f6000,
4395 .pa_end
= 0x4a0f6fff,
4396 .flags
= ADDR_TYPE_RT
4401 /* l4_cfg -> spinlock */
4402 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock
= {
4403 .master
= &omap44xx_l4_cfg_hwmod
,
4404 .slave
= &omap44xx_spinlock_hwmod
,
4406 .addr
= omap44xx_spinlock_addrs
,
4407 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4410 static struct omap_hwmod_addr_space omap44xx_timer1_addrs
[] = {
4412 .pa_start
= 0x4a318000,
4413 .pa_end
= 0x4a31807f,
4414 .flags
= ADDR_TYPE_RT
4419 /* l4_wkup -> timer1 */
4420 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1
= {
4421 .master
= &omap44xx_l4_wkup_hwmod
,
4422 .slave
= &omap44xx_timer1_hwmod
,
4423 .clk
= "l4_wkup_clk_mux_ck",
4424 .addr
= omap44xx_timer1_addrs
,
4425 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4428 static struct omap_hwmod_addr_space omap44xx_timer2_addrs
[] = {
4430 .pa_start
= 0x48032000,
4431 .pa_end
= 0x4803207f,
4432 .flags
= ADDR_TYPE_RT
4437 /* l4_per -> timer2 */
4438 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2
= {
4439 .master
= &omap44xx_l4_per_hwmod
,
4440 .slave
= &omap44xx_timer2_hwmod
,
4442 .addr
= omap44xx_timer2_addrs
,
4443 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4446 static struct omap_hwmod_addr_space omap44xx_timer3_addrs
[] = {
4448 .pa_start
= 0x48034000,
4449 .pa_end
= 0x4803407f,
4450 .flags
= ADDR_TYPE_RT
4455 /* l4_per -> timer3 */
4456 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3
= {
4457 .master
= &omap44xx_l4_per_hwmod
,
4458 .slave
= &omap44xx_timer3_hwmod
,
4460 .addr
= omap44xx_timer3_addrs
,
4461 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4464 static struct omap_hwmod_addr_space omap44xx_timer4_addrs
[] = {
4466 .pa_start
= 0x48036000,
4467 .pa_end
= 0x4803607f,
4468 .flags
= ADDR_TYPE_RT
4473 /* l4_per -> timer4 */
4474 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4
= {
4475 .master
= &omap44xx_l4_per_hwmod
,
4476 .slave
= &omap44xx_timer4_hwmod
,
4478 .addr
= omap44xx_timer4_addrs
,
4479 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4482 static struct omap_hwmod_addr_space omap44xx_timer5_addrs
[] = {
4484 .pa_start
= 0x40138000,
4485 .pa_end
= 0x4013807f,
4486 .flags
= ADDR_TYPE_RT
4491 /* l4_abe -> timer5 */
4492 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5
= {
4493 .master
= &omap44xx_l4_abe_hwmod
,
4494 .slave
= &omap44xx_timer5_hwmod
,
4495 .clk
= "ocp_abe_iclk",
4496 .addr
= omap44xx_timer5_addrs
,
4497 .user
= OCP_USER_MPU
,
4500 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs
[] = {
4502 .pa_start
= 0x49038000,
4503 .pa_end
= 0x4903807f,
4504 .flags
= ADDR_TYPE_RT
4509 /* l4_abe -> timer5 (dma) */
4510 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma
= {
4511 .master
= &omap44xx_l4_abe_hwmod
,
4512 .slave
= &omap44xx_timer5_hwmod
,
4513 .clk
= "ocp_abe_iclk",
4514 .addr
= omap44xx_timer5_dma_addrs
,
4515 .user
= OCP_USER_SDMA
,
4518 static struct omap_hwmod_addr_space omap44xx_timer6_addrs
[] = {
4520 .pa_start
= 0x4013a000,
4521 .pa_end
= 0x4013a07f,
4522 .flags
= ADDR_TYPE_RT
4527 /* l4_abe -> timer6 */
4528 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6
= {
4529 .master
= &omap44xx_l4_abe_hwmod
,
4530 .slave
= &omap44xx_timer6_hwmod
,
4531 .clk
= "ocp_abe_iclk",
4532 .addr
= omap44xx_timer6_addrs
,
4533 .user
= OCP_USER_MPU
,
4536 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs
[] = {
4538 .pa_start
= 0x4903a000,
4539 .pa_end
= 0x4903a07f,
4540 .flags
= ADDR_TYPE_RT
4545 /* l4_abe -> timer6 (dma) */
4546 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma
= {
4547 .master
= &omap44xx_l4_abe_hwmod
,
4548 .slave
= &omap44xx_timer6_hwmod
,
4549 .clk
= "ocp_abe_iclk",
4550 .addr
= omap44xx_timer6_dma_addrs
,
4551 .user
= OCP_USER_SDMA
,
4554 static struct omap_hwmod_addr_space omap44xx_timer7_addrs
[] = {
4556 .pa_start
= 0x4013c000,
4557 .pa_end
= 0x4013c07f,
4558 .flags
= ADDR_TYPE_RT
4563 /* l4_abe -> timer7 */
4564 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7
= {
4565 .master
= &omap44xx_l4_abe_hwmod
,
4566 .slave
= &omap44xx_timer7_hwmod
,
4567 .clk
= "ocp_abe_iclk",
4568 .addr
= omap44xx_timer7_addrs
,
4569 .user
= OCP_USER_MPU
,
4572 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs
[] = {
4574 .pa_start
= 0x4903c000,
4575 .pa_end
= 0x4903c07f,
4576 .flags
= ADDR_TYPE_RT
4581 /* l4_abe -> timer7 (dma) */
4582 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma
= {
4583 .master
= &omap44xx_l4_abe_hwmod
,
4584 .slave
= &omap44xx_timer7_hwmod
,
4585 .clk
= "ocp_abe_iclk",
4586 .addr
= omap44xx_timer7_dma_addrs
,
4587 .user
= OCP_USER_SDMA
,
4590 static struct omap_hwmod_addr_space omap44xx_timer8_addrs
[] = {
4592 .pa_start
= 0x4013e000,
4593 .pa_end
= 0x4013e07f,
4594 .flags
= ADDR_TYPE_RT
4599 /* l4_abe -> timer8 */
4600 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8
= {
4601 .master
= &omap44xx_l4_abe_hwmod
,
4602 .slave
= &omap44xx_timer8_hwmod
,
4603 .clk
= "ocp_abe_iclk",
4604 .addr
= omap44xx_timer8_addrs
,
4605 .user
= OCP_USER_MPU
,
4608 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs
[] = {
4610 .pa_start
= 0x4903e000,
4611 .pa_end
= 0x4903e07f,
4612 .flags
= ADDR_TYPE_RT
4617 /* l4_abe -> timer8 (dma) */
4618 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma
= {
4619 .master
= &omap44xx_l4_abe_hwmod
,
4620 .slave
= &omap44xx_timer8_hwmod
,
4621 .clk
= "ocp_abe_iclk",
4622 .addr
= omap44xx_timer8_dma_addrs
,
4623 .user
= OCP_USER_SDMA
,
4626 static struct omap_hwmod_addr_space omap44xx_timer9_addrs
[] = {
4628 .pa_start
= 0x4803e000,
4629 .pa_end
= 0x4803e07f,
4630 .flags
= ADDR_TYPE_RT
4635 /* l4_per -> timer9 */
4636 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9
= {
4637 .master
= &omap44xx_l4_per_hwmod
,
4638 .slave
= &omap44xx_timer9_hwmod
,
4640 .addr
= omap44xx_timer9_addrs
,
4641 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4644 static struct omap_hwmod_addr_space omap44xx_timer10_addrs
[] = {
4646 .pa_start
= 0x48086000,
4647 .pa_end
= 0x4808607f,
4648 .flags
= ADDR_TYPE_RT
4653 /* l4_per -> timer10 */
4654 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10
= {
4655 .master
= &omap44xx_l4_per_hwmod
,
4656 .slave
= &omap44xx_timer10_hwmod
,
4658 .addr
= omap44xx_timer10_addrs
,
4659 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4662 static struct omap_hwmod_addr_space omap44xx_timer11_addrs
[] = {
4664 .pa_start
= 0x48088000,
4665 .pa_end
= 0x4808807f,
4666 .flags
= ADDR_TYPE_RT
4671 /* l4_per -> timer11 */
4672 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11
= {
4673 .master
= &omap44xx_l4_per_hwmod
,
4674 .slave
= &omap44xx_timer11_hwmod
,
4676 .addr
= omap44xx_timer11_addrs
,
4677 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4680 static struct omap_hwmod_addr_space omap44xx_uart1_addrs
[] = {
4682 .pa_start
= 0x4806a000,
4683 .pa_end
= 0x4806a0ff,
4684 .flags
= ADDR_TYPE_RT
4689 /* l4_per -> uart1 */
4690 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1
= {
4691 .master
= &omap44xx_l4_per_hwmod
,
4692 .slave
= &omap44xx_uart1_hwmod
,
4694 .addr
= omap44xx_uart1_addrs
,
4695 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4698 static struct omap_hwmod_addr_space omap44xx_uart2_addrs
[] = {
4700 .pa_start
= 0x4806c000,
4701 .pa_end
= 0x4806c0ff,
4702 .flags
= ADDR_TYPE_RT
4707 /* l4_per -> uart2 */
4708 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2
= {
4709 .master
= &omap44xx_l4_per_hwmod
,
4710 .slave
= &omap44xx_uart2_hwmod
,
4712 .addr
= omap44xx_uart2_addrs
,
4713 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4716 static struct omap_hwmod_addr_space omap44xx_uart3_addrs
[] = {
4718 .pa_start
= 0x48020000,
4719 .pa_end
= 0x480200ff,
4720 .flags
= ADDR_TYPE_RT
4725 /* l4_per -> uart3 */
4726 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3
= {
4727 .master
= &omap44xx_l4_per_hwmod
,
4728 .slave
= &omap44xx_uart3_hwmod
,
4730 .addr
= omap44xx_uart3_addrs
,
4731 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4734 static struct omap_hwmod_addr_space omap44xx_uart4_addrs
[] = {
4736 .pa_start
= 0x4806e000,
4737 .pa_end
= 0x4806e0ff,
4738 .flags
= ADDR_TYPE_RT
4743 /* l4_per -> uart4 */
4744 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4
= {
4745 .master
= &omap44xx_l4_per_hwmod
,
4746 .slave
= &omap44xx_uart4_hwmod
,
4748 .addr
= omap44xx_uart4_addrs
,
4749 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4752 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs
[] = {
4755 .pa_start
= 0x4a064000,
4756 .pa_end
= 0x4a0647ff,
4757 .flags
= ADDR_TYPE_RT
4761 .pa_start
= 0x4a064800,
4762 .pa_end
= 0x4a064bff,
4766 .pa_start
= 0x4a064c00,
4767 .pa_end
= 0x4a064fff,
4772 /* l4_cfg -> usb_host_hs */
4773 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs
= {
4774 .master
= &omap44xx_l4_cfg_hwmod
,
4775 .slave
= &omap44xx_usb_host_hs_hwmod
,
4777 .addr
= omap44xx_usb_host_hs_addrs
,
4778 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4781 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs
[] = {
4783 .pa_start
= 0x4a0ab000,
4784 .pa_end
= 0x4a0ab003,
4785 .flags
= ADDR_TYPE_RT
4790 /* l4_cfg -> usb_otg_hs */
4791 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs
= {
4792 .master
= &omap44xx_l4_cfg_hwmod
,
4793 .slave
= &omap44xx_usb_otg_hs_hwmod
,
4795 .addr
= omap44xx_usb_otg_hs_addrs
,
4796 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4799 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs
[] = {
4802 .pa_start
= 0x4a062000,
4803 .pa_end
= 0x4a063fff,
4804 .flags
= ADDR_TYPE_RT
4809 /* l4_cfg -> usb_tll_hs */
4810 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs
= {
4811 .master
= &omap44xx_l4_cfg_hwmod
,
4812 .slave
= &omap44xx_usb_tll_hs_hwmod
,
4814 .addr
= omap44xx_usb_tll_hs_addrs
,
4815 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4818 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs
[] = {
4820 .pa_start
= 0x4a314000,
4821 .pa_end
= 0x4a31407f,
4822 .flags
= ADDR_TYPE_RT
4827 /* l4_wkup -> wd_timer2 */
4828 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2
= {
4829 .master
= &omap44xx_l4_wkup_hwmod
,
4830 .slave
= &omap44xx_wd_timer2_hwmod
,
4831 .clk
= "l4_wkup_clk_mux_ck",
4832 .addr
= omap44xx_wd_timer2_addrs
,
4833 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4836 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs
[] = {
4838 .pa_start
= 0x40130000,
4839 .pa_end
= 0x4013007f,
4840 .flags
= ADDR_TYPE_RT
4845 /* l4_abe -> wd_timer3 */
4846 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3
= {
4847 .master
= &omap44xx_l4_abe_hwmod
,
4848 .slave
= &omap44xx_wd_timer3_hwmod
,
4849 .clk
= "ocp_abe_iclk",
4850 .addr
= omap44xx_wd_timer3_addrs
,
4851 .user
= OCP_USER_MPU
,
4854 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs
[] = {
4856 .pa_start
= 0x49030000,
4857 .pa_end
= 0x4903007f,
4858 .flags
= ADDR_TYPE_RT
4863 /* l4_abe -> wd_timer3 (dma) */
4864 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma
= {
4865 .master
= &omap44xx_l4_abe_hwmod
,
4866 .slave
= &omap44xx_wd_timer3_hwmod
,
4867 .clk
= "ocp_abe_iclk",
4868 .addr
= omap44xx_wd_timer3_dma_addrs
,
4869 .user
= OCP_USER_SDMA
,
4872 static struct omap_hwmod_ocp_if
*omap44xx_hwmod_ocp_ifs
[] __initdata
= {
4873 &omap44xx_l3_main_1__dmm
,
4875 &omap44xx_dmm__emif_fw
,
4876 &omap44xx_l4_cfg__emif_fw
,
4877 &omap44xx_iva__l3_instr
,
4878 &omap44xx_l3_main_3__l3_instr
,
4879 &omap44xx_dsp__l3_main_1
,
4880 &omap44xx_dss__l3_main_1
,
4881 &omap44xx_l3_main_2__l3_main_1
,
4882 &omap44xx_l4_cfg__l3_main_1
,
4883 &omap44xx_mmc1__l3_main_1
,
4884 &omap44xx_mmc2__l3_main_1
,
4885 &omap44xx_mpu__l3_main_1
,
4886 &omap44xx_dma_system__l3_main_2
,
4887 &omap44xx_fdif__l3_main_2
,
4888 &omap44xx_hsi__l3_main_2
,
4889 &omap44xx_ipu__l3_main_2
,
4890 &omap44xx_iss__l3_main_2
,
4891 &omap44xx_iva__l3_main_2
,
4892 &omap44xx_l3_main_1__l3_main_2
,
4893 &omap44xx_l4_cfg__l3_main_2
,
4894 &omap44xx_usb_host_hs__l3_main_2
,
4895 &omap44xx_usb_otg_hs__l3_main_2
,
4896 &omap44xx_l3_main_1__l3_main_3
,
4897 &omap44xx_l3_main_2__l3_main_3
,
4898 &omap44xx_l4_cfg__l3_main_3
,
4899 &omap44xx_aess__l4_abe
,
4900 &omap44xx_dsp__l4_abe
,
4901 &omap44xx_l3_main_1__l4_abe
,
4902 &omap44xx_mpu__l4_abe
,
4903 &omap44xx_l3_main_1__l4_cfg
,
4904 &omap44xx_l3_main_2__l4_per
,
4905 &omap44xx_l4_cfg__l4_wkup
,
4906 &omap44xx_mpu__mpu_private
,
4907 &omap44xx_l4_abe__aess
,
4908 &omap44xx_l4_abe__aess_dma
,
4909 &omap44xx_l4_wkup__counter_32k
,
4910 &omap44xx_l4_cfg__dma_system
,
4911 &omap44xx_l4_abe__dmic
,
4912 &omap44xx_l4_abe__dmic_dma
,
4914 &omap44xx_l4_cfg__dsp
,
4915 &omap44xx_l3_main_2__dss
,
4916 &omap44xx_l4_per__dss
,
4917 &omap44xx_l3_main_2__dss_dispc
,
4918 &omap44xx_l4_per__dss_dispc
,
4919 &omap44xx_l3_main_2__dss_dsi1
,
4920 &omap44xx_l4_per__dss_dsi1
,
4921 &omap44xx_l3_main_2__dss_dsi2
,
4922 &omap44xx_l4_per__dss_dsi2
,
4923 &omap44xx_l3_main_2__dss_hdmi
,
4924 &omap44xx_l4_per__dss_hdmi
,
4925 &omap44xx_l3_main_2__dss_rfbi
,
4926 &omap44xx_l4_per__dss_rfbi
,
4927 &omap44xx_l3_main_2__dss_venc
,
4928 &omap44xx_l4_per__dss_venc
,
4929 &omap44xx_l4_cfg__fdif
,
4930 &omap44xx_l4_wkup__gpio1
,
4931 &omap44xx_l4_per__gpio2
,
4932 &omap44xx_l4_per__gpio3
,
4933 &omap44xx_l4_per__gpio4
,
4934 &omap44xx_l4_per__gpio5
,
4935 &omap44xx_l4_per__gpio6
,
4936 &omap44xx_l3_main_2__gpmc
,
4937 &omap44xx_l4_per__hdq1w
,
4938 &omap44xx_l4_cfg__hsi
,
4939 &omap44xx_l4_per__i2c1
,
4940 &omap44xx_l4_per__i2c2
,
4941 &omap44xx_l4_per__i2c3
,
4942 &omap44xx_l4_per__i2c4
,
4943 &omap44xx_l3_main_2__ipu
,
4944 &omap44xx_l3_main_2__iss
,
4945 &omap44xx_l3_main_2__iva
,
4946 &omap44xx_l4_wkup__kbd
,
4947 &omap44xx_l4_cfg__mailbox
,
4948 &omap44xx_l4_abe__mcbsp1
,
4949 &omap44xx_l4_abe__mcbsp1_dma
,
4950 &omap44xx_l4_abe__mcbsp2
,
4951 &omap44xx_l4_abe__mcbsp2_dma
,
4952 &omap44xx_l4_abe__mcbsp3
,
4953 &omap44xx_l4_abe__mcbsp3_dma
,
4954 &omap44xx_l4_per__mcbsp4
,
4955 &omap44xx_l4_abe__mcpdm
,
4956 &omap44xx_l4_abe__mcpdm_dma
,
4957 &omap44xx_l4_per__mcspi1
,
4958 &omap44xx_l4_per__mcspi2
,
4959 &omap44xx_l4_per__mcspi3
,
4960 &omap44xx_l4_per__mcspi4
,
4961 &omap44xx_l4_per__mmc1
,
4962 &omap44xx_l4_per__mmc2
,
4963 &omap44xx_l4_per__mmc3
,
4964 &omap44xx_l4_per__mmc4
,
4965 &omap44xx_l4_per__mmc5
,
4966 &omap44xx_l4_cfg__smartreflex_core
,
4967 &omap44xx_l4_cfg__smartreflex_iva
,
4968 &omap44xx_l4_cfg__smartreflex_mpu
,
4969 &omap44xx_l4_cfg__spinlock
,
4970 &omap44xx_l4_wkup__timer1
,
4971 &omap44xx_l4_per__timer2
,
4972 &omap44xx_l4_per__timer3
,
4973 &omap44xx_l4_per__timer4
,
4974 &omap44xx_l4_abe__timer5
,
4975 &omap44xx_l4_abe__timer5_dma
,
4976 &omap44xx_l4_abe__timer6
,
4977 &omap44xx_l4_abe__timer6_dma
,
4978 &omap44xx_l4_abe__timer7
,
4979 &omap44xx_l4_abe__timer7_dma
,
4980 &omap44xx_l4_abe__timer8
,
4981 &omap44xx_l4_abe__timer8_dma
,
4982 &omap44xx_l4_per__timer9
,
4983 &omap44xx_l4_per__timer10
,
4984 &omap44xx_l4_per__timer11
,
4985 &omap44xx_l4_per__uart1
,
4986 &omap44xx_l4_per__uart2
,
4987 &omap44xx_l4_per__uart3
,
4988 &omap44xx_l4_per__uart4
,
4989 &omap44xx_l4_cfg__usb_host_hs
,
4990 &omap44xx_l4_cfg__usb_otg_hs
,
4991 &omap44xx_l4_cfg__usb_tll_hs
,
4992 &omap44xx_l4_wkup__wd_timer2
,
4993 &omap44xx_l4_abe__wd_timer3
,
4994 &omap44xx_l4_abe__wd_timer3_dma
,
4998 int __init
omap44xx_hwmod_init(void)
5000 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs
);