2 * Hardware modules present on the OMAP54xx chips
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/power/smartreflex.h>
23 #include <linux/omap-dma.h>
25 #include "omap_hwmod.h"
26 #include "omap_hwmod_common_data.h"
32 /* Base offset for all OMAP5 interrupts external to MPUSS */
33 #define OMAP54XX_IRQ_GIC_START 32
35 /* Base offset for all OMAP5 dma requests */
36 #define OMAP54XX_DMA_REQ_START 1
47 static struct omap_hwmod_class omap54xx_dmm_hwmod_class
= {
52 static struct omap_hwmod omap54xx_dmm_hwmod
= {
54 .class = &omap54xx_dmm_hwmod_class
,
55 .clkdm_name
= "emif_clkdm",
58 .clkctrl_offs
= OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET
,
59 .context_offs
= OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET
,
66 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
68 static struct omap_hwmod_class omap54xx_l3_hwmod_class
= {
73 static struct omap_hwmod omap54xx_l3_instr_hwmod
= {
75 .class = &omap54xx_l3_hwmod_class
,
76 .clkdm_name
= "l3instr_clkdm",
79 .clkctrl_offs
= OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
,
80 .context_offs
= OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
,
81 .modulemode
= MODULEMODE_HWCTRL
,
87 static struct omap_hwmod omap54xx_l3_main_1_hwmod
= {
89 .class = &omap54xx_l3_hwmod_class
,
90 .clkdm_name
= "l3main1_clkdm",
93 .clkctrl_offs
= OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET
,
94 .context_offs
= OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET
,
100 static struct omap_hwmod omap54xx_l3_main_2_hwmod
= {
102 .class = &omap54xx_l3_hwmod_class
,
103 .clkdm_name
= "l3main2_clkdm",
106 .clkctrl_offs
= OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET
,
107 .context_offs
= OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET
,
113 static struct omap_hwmod omap54xx_l3_main_3_hwmod
= {
115 .class = &omap54xx_l3_hwmod_class
,
116 .clkdm_name
= "l3instr_clkdm",
119 .clkctrl_offs
= OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET
,
120 .context_offs
= OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET
,
121 .modulemode
= MODULEMODE_HWCTRL
,
128 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
130 static struct omap_hwmod_class omap54xx_l4_hwmod_class
= {
135 static struct omap_hwmod omap54xx_l4_abe_hwmod
= {
137 .class = &omap54xx_l4_hwmod_class
,
138 .clkdm_name
= "abe_clkdm",
141 .clkctrl_offs
= OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET
,
142 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
148 static struct omap_hwmod omap54xx_l4_cfg_hwmod
= {
150 .class = &omap54xx_l4_hwmod_class
,
151 .clkdm_name
= "l4cfg_clkdm",
154 .clkctrl_offs
= OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
,
155 .context_offs
= OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
,
161 static struct omap_hwmod omap54xx_l4_per_hwmod
= {
163 .class = &omap54xx_l4_hwmod_class
,
164 .clkdm_name
= "l4per_clkdm",
167 .clkctrl_offs
= OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET
,
168 .context_offs
= OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET
,
174 static struct omap_hwmod omap54xx_l4_wkup_hwmod
= {
176 .class = &omap54xx_l4_hwmod_class
,
177 .clkdm_name
= "wkupaon_clkdm",
180 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET
,
181 .context_offs
= OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET
,
188 * instance(s): mpu_private
190 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class
= {
195 static struct omap_hwmod omap54xx_mpu_private_hwmod
= {
196 .name
= "mpu_private",
197 .class = &omap54xx_mpu_bus_hwmod_class
,
198 .clkdm_name
= "mpu_clkdm",
201 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
208 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
211 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc
= {
214 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
215 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
),
216 .sysc_fields
= &omap_hwmod_sysc_type1
,
219 static struct omap_hwmod_class omap54xx_counter_hwmod_class
= {
221 .sysc
= &omap54xx_counter_sysc
,
225 static struct omap_hwmod omap54xx_counter_32k_hwmod
= {
226 .name
= "counter_32k",
227 .class = &omap54xx_counter_hwmod_class
,
228 .clkdm_name
= "wkupaon_clkdm",
229 .flags
= HWMOD_SWSUP_SIDLE
,
230 .main_clk
= "wkupaon_iclk_mux",
233 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET
,
234 .context_offs
= OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET
,
241 * dma controller for data exchange between memory to memory (i.e. internal or
242 * external memory) and gp peripherals to memory or memory to gp peripherals
245 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc
= {
249 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
250 SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
251 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
252 SYSS_HAS_RESET_STATUS
),
253 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
254 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
255 .sysc_fields
= &omap_hwmod_sysc_type1
,
258 static struct omap_hwmod_class omap54xx_dma_hwmod_class
= {
260 .sysc
= &omap54xx_dma_sysc
,
264 static struct omap_dma_dev_attr dma_dev_attr
= {
265 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
266 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
271 static struct omap_hwmod omap54xx_dma_system_hwmod
= {
272 .name
= "dma_system",
273 .class = &omap54xx_dma_hwmod_class
,
274 .clkdm_name
= "dma_clkdm",
275 .main_clk
= "l3_iclk_div",
278 .clkctrl_offs
= OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET
,
279 .context_offs
= OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET
,
282 .dev_attr
= &dma_dev_attr
,
287 * digital microphone controller
290 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc
= {
293 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
294 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
295 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
297 .sysc_fields
= &omap_hwmod_sysc_type2
,
300 static struct omap_hwmod_class omap54xx_dmic_hwmod_class
= {
302 .sysc
= &omap54xx_dmic_sysc
,
306 static struct omap_hwmod omap54xx_dmic_hwmod
= {
308 .class = &omap54xx_dmic_hwmod_class
,
309 .clkdm_name
= "abe_clkdm",
310 .main_clk
= "dmic_gfclk",
313 .clkctrl_offs
= OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET
,
314 .context_offs
= OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET
,
315 .modulemode
= MODULEMODE_SWCTRL
,
324 static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc
= {
327 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
330 static struct omap_hwmod_class omap54xx_dss_hwmod_class
= {
332 .sysc
= &omap54xx_dss_sysc
,
333 .reset
= omap_dss_reset
,
337 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
338 { .role
= "32khz_clk", .clk
= "dss_32khz_clk" },
339 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
340 { .role
= "hdmi_clk", .clk
= "dss_48mhz_clk" },
343 static struct omap_hwmod omap54xx_dss_hwmod
= {
345 .class = &omap54xx_dss_hwmod_class
,
346 .clkdm_name
= "dss_clkdm",
347 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
348 .main_clk
= "dss_dss_clk",
351 .clkctrl_offs
= OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET
,
352 .context_offs
= OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET
,
353 .modulemode
= MODULEMODE_SWCTRL
,
356 .opt_clks
= dss_opt_clks
,
357 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
365 static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc
= {
369 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
370 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_MIDLEMODE
|
371 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
372 SYSS_HAS_RESET_STATUS
),
373 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
374 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
375 .sysc_fields
= &omap_hwmod_sysc_type1
,
378 static struct omap_hwmod_class omap54xx_dispc_hwmod_class
= {
380 .sysc
= &omap54xx_dispc_sysc
,
384 static struct omap_hwmod_opt_clk dss_dispc_opt_clks
[] = {
385 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
388 /* dss_dispc dev_attr */
389 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr
= {
390 .has_framedonetv_irq
= 1,
394 static struct omap_hwmod omap54xx_dss_dispc_hwmod
= {
396 .class = &omap54xx_dispc_hwmod_class
,
397 .clkdm_name
= "dss_clkdm",
398 .main_clk
= "dss_dss_clk",
401 .clkctrl_offs
= OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET
,
402 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
405 .opt_clks
= dss_dispc_opt_clks
,
406 .opt_clks_cnt
= ARRAY_SIZE(dss_dispc_opt_clks
),
407 .dev_attr
= &dss_dispc_dev_attr
,
408 .parent_hwmod
= &omap54xx_dss_hwmod
,
413 * display serial interface controller
416 static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc
= {
420 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
421 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
422 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
423 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
424 .sysc_fields
= &omap_hwmod_sysc_type1
,
427 static struct omap_hwmod_class omap54xx_dsi1_hwmod_class
= {
429 .sysc
= &omap54xx_dsi1_sysc
,
433 static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks
[] = {
434 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
437 static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod
= {
439 .class = &omap54xx_dsi1_hwmod_class
,
440 .clkdm_name
= "dss_clkdm",
441 .main_clk
= "dss_dss_clk",
444 .clkctrl_offs
= OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET
,
445 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
448 .opt_clks
= dss_dsi1_a_opt_clks
,
449 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi1_a_opt_clks
),
450 .parent_hwmod
= &omap54xx_dss_hwmod
,
454 static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks
[] = {
455 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
458 static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod
= {
460 .class = &omap54xx_dsi1_hwmod_class
,
461 .clkdm_name
= "dss_clkdm",
462 .main_clk
= "dss_dss_clk",
465 .clkctrl_offs
= OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET
,
466 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
469 .opt_clks
= dss_dsi1_c_opt_clks
,
470 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi1_c_opt_clks
),
471 .parent_hwmod
= &omap54xx_dss_hwmod
,
479 static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc
= {
482 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
484 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
486 .sysc_fields
= &omap_hwmod_sysc_type2
,
489 static struct omap_hwmod_class omap54xx_hdmi_hwmod_class
= {
491 .sysc
= &omap54xx_hdmi_sysc
,
494 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks
[] = {
495 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
498 static struct omap_hwmod omap54xx_dss_hdmi_hwmod
= {
500 .class = &omap54xx_hdmi_hwmod_class
,
501 .clkdm_name
= "dss_clkdm",
502 .main_clk
= "dss_48mhz_clk",
505 .clkctrl_offs
= OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET
,
506 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
509 .opt_clks
= dss_hdmi_opt_clks
,
510 .opt_clks_cnt
= ARRAY_SIZE(dss_hdmi_opt_clks
),
511 .parent_hwmod
= &omap54xx_dss_hwmod
,
516 * remote frame buffer interface
519 static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc
= {
523 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
524 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
525 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
526 .sysc_fields
= &omap_hwmod_sysc_type1
,
529 static struct omap_hwmod_class omap54xx_rfbi_hwmod_class
= {
531 .sysc
= &omap54xx_rfbi_sysc
,
535 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks
[] = {
536 { .role
= "ick", .clk
= "l3_iclk_div" },
539 static struct omap_hwmod omap54xx_dss_rfbi_hwmod
= {
541 .class = &omap54xx_rfbi_hwmod_class
,
542 .clkdm_name
= "dss_clkdm",
545 .clkctrl_offs
= OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET
,
546 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
549 .opt_clks
= dss_rfbi_opt_clks
,
550 .opt_clks_cnt
= ARRAY_SIZE(dss_rfbi_opt_clks
),
551 .parent_hwmod
= &omap54xx_dss_hwmod
,
556 * external memory interface no1 (wrapper)
559 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc
= {
563 static struct omap_hwmod_class omap54xx_emif_hwmod_class
= {
565 .sysc
= &omap54xx_emif_sysc
,
569 static struct omap_hwmod omap54xx_emif1_hwmod
= {
571 .class = &omap54xx_emif_hwmod_class
,
572 .clkdm_name
= "emif_clkdm",
573 .flags
= HWMOD_INIT_NO_IDLE
,
574 .main_clk
= "dpll_core_h11x2_ck",
577 .clkctrl_offs
= OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET
,
578 .context_offs
= OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET
,
579 .modulemode
= MODULEMODE_HWCTRL
,
585 static struct omap_hwmod omap54xx_emif2_hwmod
= {
587 .class = &omap54xx_emif_hwmod_class
,
588 .clkdm_name
= "emif_clkdm",
589 .flags
= HWMOD_INIT_NO_IDLE
,
590 .main_clk
= "dpll_core_h11x2_ck",
593 .clkctrl_offs
= OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET
,
594 .context_offs
= OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET
,
595 .modulemode
= MODULEMODE_HWCTRL
,
602 * keyboard controller
605 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc
= {
608 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
610 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
611 .sysc_fields
= &omap_hwmod_sysc_type1
,
614 static struct omap_hwmod_class omap54xx_kbd_hwmod_class
= {
616 .sysc
= &omap54xx_kbd_sysc
,
620 static struct omap_hwmod omap54xx_kbd_hwmod
= {
622 .class = &omap54xx_kbd_hwmod_class
,
623 .clkdm_name
= "wkupaon_clkdm",
624 .main_clk
= "sys_32k_ck",
627 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET
,
628 .context_offs
= OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET
,
629 .modulemode
= MODULEMODE_SWCTRL
,
636 * mailbox module allowing communication between the on-chip processors using a
637 * queued mailbox-interrupt mechanism.
640 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc
= {
643 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
645 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
646 .sysc_fields
= &omap_hwmod_sysc_type2
,
649 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class
= {
651 .sysc
= &omap54xx_mailbox_sysc
,
655 static struct omap_hwmod omap54xx_mailbox_hwmod
= {
657 .class = &omap54xx_mailbox_hwmod_class
,
658 .clkdm_name
= "l4cfg_clkdm",
661 .clkctrl_offs
= OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET
,
662 .context_offs
= OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET
,
669 * multi channel buffered serial port controller
672 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc
= {
675 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_ENAWAKEUP
|
676 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
677 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
678 .sysc_fields
= &omap_hwmod_sysc_type1
,
681 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class
= {
683 .sysc
= &omap54xx_mcbsp_sysc
,
687 static struct omap_hwmod_opt_clk mcbsp1_opt_clks
[] = {
688 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
689 { .role
= "prcm_fck", .clk
= "mcbsp1_sync_mux_ck" },
692 static struct omap_hwmod omap54xx_mcbsp1_hwmod
= {
694 .class = &omap54xx_mcbsp_hwmod_class
,
695 .clkdm_name
= "abe_clkdm",
696 .main_clk
= "mcbsp1_gfclk",
699 .clkctrl_offs
= OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET
,
700 .context_offs
= OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET
,
701 .modulemode
= MODULEMODE_SWCTRL
,
704 .opt_clks
= mcbsp1_opt_clks
,
705 .opt_clks_cnt
= ARRAY_SIZE(mcbsp1_opt_clks
),
709 static struct omap_hwmod_opt_clk mcbsp2_opt_clks
[] = {
710 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
711 { .role
= "prcm_fck", .clk
= "mcbsp2_sync_mux_ck" },
714 static struct omap_hwmod omap54xx_mcbsp2_hwmod
= {
716 .class = &omap54xx_mcbsp_hwmod_class
,
717 .clkdm_name
= "abe_clkdm",
718 .main_clk
= "mcbsp2_gfclk",
721 .clkctrl_offs
= OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET
,
722 .context_offs
= OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET
,
723 .modulemode
= MODULEMODE_SWCTRL
,
726 .opt_clks
= mcbsp2_opt_clks
,
727 .opt_clks_cnt
= ARRAY_SIZE(mcbsp2_opt_clks
),
731 static struct omap_hwmod_opt_clk mcbsp3_opt_clks
[] = {
732 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
733 { .role
= "prcm_fck", .clk
= "mcbsp3_sync_mux_ck" },
736 static struct omap_hwmod omap54xx_mcbsp3_hwmod
= {
738 .class = &omap54xx_mcbsp_hwmod_class
,
739 .clkdm_name
= "abe_clkdm",
740 .main_clk
= "mcbsp3_gfclk",
743 .clkctrl_offs
= OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET
,
744 .context_offs
= OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET
,
745 .modulemode
= MODULEMODE_SWCTRL
,
748 .opt_clks
= mcbsp3_opt_clks
,
749 .opt_clks_cnt
= ARRAY_SIZE(mcbsp3_opt_clks
),
754 * multi channel pdm controller (proprietary interface with phoenix power
758 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc
= {
761 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
762 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
763 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
765 .sysc_fields
= &omap_hwmod_sysc_type2
,
768 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class
= {
770 .sysc
= &omap54xx_mcpdm_sysc
,
774 static struct omap_hwmod omap54xx_mcpdm_hwmod
= {
776 .class = &omap54xx_mcpdm_hwmod_class
,
777 .clkdm_name
= "abe_clkdm",
779 * It's suspected that the McPDM requires an off-chip main
780 * functional clock, controlled via I2C. This IP block is
781 * currently reset very early during boot, before I2C is
782 * available, so it doesn't seem that we have any choice in
783 * the kernel other than to avoid resetting it. XXX This is
784 * really a hardware issue workaround: every IP block should
785 * be able to source its main functional clock from either
786 * on-chip or off-chip sources. McPDM seems to be the only
790 .flags
= HWMOD_EXT_OPT_MAIN_CLK
| HWMOD_SWSUP_SIDLE
,
791 .main_clk
= "pad_clks_ck",
794 .clkctrl_offs
= OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET
,
795 .context_offs
= OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET
,
796 .modulemode
= MODULEMODE_SWCTRL
,
803 * multichannel serial port interface (mcspi) / master/slave synchronous serial
807 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc
= {
810 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
811 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
812 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
814 .sysc_fields
= &omap_hwmod_sysc_type2
,
817 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class
= {
819 .sysc
= &omap54xx_mcspi_sysc
,
823 static struct omap_hwmod omap54xx_mcspi1_hwmod
= {
825 .class = &omap54xx_mcspi_hwmod_class
,
826 .clkdm_name
= "l4per_clkdm",
827 .main_clk
= "func_48m_fclk",
830 .clkctrl_offs
= OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
,
831 .context_offs
= OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET
,
832 .modulemode
= MODULEMODE_SWCTRL
,
838 static struct omap_hwmod omap54xx_mcspi2_hwmod
= {
840 .class = &omap54xx_mcspi_hwmod_class
,
841 .clkdm_name
= "l4per_clkdm",
842 .main_clk
= "func_48m_fclk",
845 .clkctrl_offs
= OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
,
846 .context_offs
= OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET
,
847 .modulemode
= MODULEMODE_SWCTRL
,
853 static struct omap_hwmod omap54xx_mcspi3_hwmod
= {
855 .class = &omap54xx_mcspi_hwmod_class
,
856 .clkdm_name
= "l4per_clkdm",
857 .main_clk
= "func_48m_fclk",
860 .clkctrl_offs
= OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
,
861 .context_offs
= OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET
,
862 .modulemode
= MODULEMODE_SWCTRL
,
868 static struct omap_hwmod omap54xx_mcspi4_hwmod
= {
870 .class = &omap54xx_mcspi_hwmod_class
,
871 .clkdm_name
= "l4per_clkdm",
872 .main_clk
= "func_48m_fclk",
875 .clkctrl_offs
= OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
,
876 .context_offs
= OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET
,
877 .modulemode
= MODULEMODE_SWCTRL
,
884 * The memory management unit performs virtual to physical address translation
885 * for its requestors.
888 static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc
= {
892 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
893 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
894 SYSS_HAS_RESET_STATUS
),
895 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
896 .sysc_fields
= &omap_hwmod_sysc_type1
,
899 static struct omap_hwmod_class omap54xx_mmu_hwmod_class
= {
901 .sysc
= &omap54xx_mmu_sysc
,
904 static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets
[] = {
905 { .name
= "mmu_cache", .rst_shift
= 1 },
908 static struct omap_hwmod omap54xx_mmu_dsp_hwmod
= {
910 .class = &omap54xx_mmu_hwmod_class
,
911 .clkdm_name
= "dsp_clkdm",
912 .rst_lines
= omap54xx_mmu_dsp_resets
,
913 .rst_lines_cnt
= ARRAY_SIZE(omap54xx_mmu_dsp_resets
),
914 .main_clk
= "dpll_iva_h11x2_ck",
917 .clkctrl_offs
= OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET
,
918 .rstctrl_offs
= OMAP54XX_RM_DSP_RSTCTRL_OFFSET
,
919 .context_offs
= OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET
,
920 .modulemode
= MODULEMODE_HWCTRL
,
926 static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets
[] = {
927 { .name
= "mmu_cache", .rst_shift
= 2 },
930 static struct omap_hwmod omap54xx_mmu_ipu_hwmod
= {
932 .class = &omap54xx_mmu_hwmod_class
,
933 .clkdm_name
= "ipu_clkdm",
934 .rst_lines
= omap54xx_mmu_ipu_resets
,
935 .rst_lines_cnt
= ARRAY_SIZE(omap54xx_mmu_ipu_resets
),
936 .main_clk
= "dpll_core_h22x2_ck",
939 .clkctrl_offs
= OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET
,
940 .rstctrl_offs
= OMAP54XX_RM_IPU_RSTCTRL_OFFSET
,
941 .context_offs
= OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET
,
942 .modulemode
= MODULEMODE_HWCTRL
,
952 static struct omap_hwmod_class omap54xx_mpu_hwmod_class
= {
957 static struct omap_hwmod omap54xx_mpu_hwmod
= {
959 .class = &omap54xx_mpu_hwmod_class
,
960 .clkdm_name
= "mpu_clkdm",
961 .flags
= HWMOD_INIT_NO_IDLE
,
962 .main_clk
= "dpll_mpu_m2_ck",
965 .clkctrl_offs
= OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET
,
966 .context_offs
= OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET
,
973 * spinlock provides hardware assistance for synchronizing the processes
974 * running on multiple processors
977 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc
= {
981 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
982 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
983 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
984 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
985 .sysc_fields
= &omap_hwmod_sysc_type1
,
988 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class
= {
990 .sysc
= &omap54xx_spinlock_sysc
,
994 static struct omap_hwmod omap54xx_spinlock_hwmod
= {
996 .class = &omap54xx_spinlock_hwmod_class
,
997 .clkdm_name
= "l4cfg_clkdm",
1000 .clkctrl_offs
= OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET
,
1001 .context_offs
= OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET
,
1008 * bridge to transform ocp interface protocol to scp (serial control port)
1012 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc
= {
1014 .sysc_offs
= 0x0010,
1015 .syss_offs
= 0x0014,
1016 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
1017 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1018 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1019 .sysc_fields
= &omap_hwmod_sysc_type1
,
1022 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class
= {
1024 .sysc
= &omap54xx_ocp2scp_sysc
,
1028 static struct omap_hwmod omap54xx_ocp2scp1_hwmod
= {
1030 .class = &omap54xx_ocp2scp_hwmod_class
,
1031 .clkdm_name
= "l3init_clkdm",
1032 .main_clk
= "l4_root_clk_div",
1035 .clkctrl_offs
= OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET
,
1036 .context_offs
= OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET
,
1037 .modulemode
= MODULEMODE_HWCTRL
,
1044 * general purpose timer module with accurate 1ms tick
1045 * This class contains several variants: ['timer_1ms', 'timer']
1048 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc
= {
1050 .sysc_offs
= 0x0010,
1051 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1052 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1053 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1055 .sysc_fields
= &omap_hwmod_sysc_type2
,
1058 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class
= {
1060 .sysc
= &omap54xx_timer_1ms_sysc
,
1063 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc
= {
1065 .sysc_offs
= 0x0010,
1066 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1067 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1068 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1070 .sysc_fields
= &omap_hwmod_sysc_type2
,
1073 static struct omap_hwmod_class omap54xx_timer_hwmod_class
= {
1075 .sysc
= &omap54xx_timer_sysc
,
1079 static struct omap_hwmod omap54xx_timer1_hwmod
= {
1081 .class = &omap54xx_timer_1ms_hwmod_class
,
1082 .clkdm_name
= "wkupaon_clkdm",
1083 .main_clk
= "timer1_gfclk_mux",
1084 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
1087 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET
,
1088 .context_offs
= OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET
,
1089 .modulemode
= MODULEMODE_SWCTRL
,
1095 static struct omap_hwmod omap54xx_timer2_hwmod
= {
1097 .class = &omap54xx_timer_1ms_hwmod_class
,
1098 .clkdm_name
= "l4per_clkdm",
1099 .main_clk
= "timer2_gfclk_mux",
1100 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
1103 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET
,
1104 .context_offs
= OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET
,
1105 .modulemode
= MODULEMODE_SWCTRL
,
1111 static struct omap_hwmod omap54xx_timer3_hwmod
= {
1113 .class = &omap54xx_timer_hwmod_class
,
1114 .clkdm_name
= "l4per_clkdm",
1115 .main_clk
= "timer3_gfclk_mux",
1118 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET
,
1119 .context_offs
= OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET
,
1120 .modulemode
= MODULEMODE_SWCTRL
,
1126 static struct omap_hwmod omap54xx_timer4_hwmod
= {
1128 .class = &omap54xx_timer_hwmod_class
,
1129 .clkdm_name
= "l4per_clkdm",
1130 .main_clk
= "timer4_gfclk_mux",
1133 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET
,
1134 .context_offs
= OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET
,
1135 .modulemode
= MODULEMODE_SWCTRL
,
1141 static struct omap_hwmod omap54xx_timer5_hwmod
= {
1143 .class = &omap54xx_timer_hwmod_class
,
1144 .clkdm_name
= "abe_clkdm",
1145 .main_clk
= "timer5_gfclk_mux",
1148 .clkctrl_offs
= OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET
,
1149 .context_offs
= OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET
,
1150 .modulemode
= MODULEMODE_SWCTRL
,
1156 static struct omap_hwmod omap54xx_timer6_hwmod
= {
1158 .class = &omap54xx_timer_hwmod_class
,
1159 .clkdm_name
= "abe_clkdm",
1160 .main_clk
= "timer6_gfclk_mux",
1163 .clkctrl_offs
= OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET
,
1164 .context_offs
= OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET
,
1165 .modulemode
= MODULEMODE_SWCTRL
,
1171 static struct omap_hwmod omap54xx_timer7_hwmod
= {
1173 .class = &omap54xx_timer_hwmod_class
,
1174 .clkdm_name
= "abe_clkdm",
1175 .main_clk
= "timer7_gfclk_mux",
1178 .clkctrl_offs
= OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET
,
1179 .context_offs
= OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET
,
1180 .modulemode
= MODULEMODE_SWCTRL
,
1186 static struct omap_hwmod omap54xx_timer8_hwmod
= {
1188 .class = &omap54xx_timer_hwmod_class
,
1189 .clkdm_name
= "abe_clkdm",
1190 .main_clk
= "timer8_gfclk_mux",
1193 .clkctrl_offs
= OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET
,
1194 .context_offs
= OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET
,
1195 .modulemode
= MODULEMODE_SWCTRL
,
1201 static struct omap_hwmod omap54xx_timer9_hwmod
= {
1203 .class = &omap54xx_timer_hwmod_class
,
1204 .clkdm_name
= "l4per_clkdm",
1205 .main_clk
= "timer9_gfclk_mux",
1208 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET
,
1209 .context_offs
= OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET
,
1210 .modulemode
= MODULEMODE_SWCTRL
,
1216 static struct omap_hwmod omap54xx_timer10_hwmod
= {
1218 .class = &omap54xx_timer_1ms_hwmod_class
,
1219 .clkdm_name
= "l4per_clkdm",
1220 .main_clk
= "timer10_gfclk_mux",
1221 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
1224 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET
,
1225 .context_offs
= OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET
,
1226 .modulemode
= MODULEMODE_SWCTRL
,
1232 static struct omap_hwmod omap54xx_timer11_hwmod
= {
1234 .class = &omap54xx_timer_hwmod_class
,
1235 .clkdm_name
= "l4per_clkdm",
1236 .main_clk
= "timer11_gfclk_mux",
1239 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET
,
1240 .context_offs
= OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET
,
1241 .modulemode
= MODULEMODE_SWCTRL
,
1247 * 'usb_host_hs' class
1248 * high-speed multi-port usb host controller
1251 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc
= {
1253 .sysc_offs
= 0x0010,
1254 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1255 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1256 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1257 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1258 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1259 .sysc_fields
= &omap_hwmod_sysc_type2
,
1262 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class
= {
1263 .name
= "usb_host_hs",
1264 .sysc
= &omap54xx_usb_host_hs_sysc
,
1267 static struct omap_hwmod omap54xx_usb_host_hs_hwmod
= {
1268 .name
= "usb_host_hs",
1269 .class = &omap54xx_usb_host_hs_hwmod_class
,
1270 .clkdm_name
= "l3init_clkdm",
1272 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1276 * In the following configuration :
1277 * - USBHOST module is set to smart-idle mode
1278 * - PRCM asserts idle_req to the USBHOST module ( This typically
1279 * happens when the system is going to a low power mode : all ports
1280 * have been suspended, the master part of the USBHOST module has
1281 * entered the standby state, and SW has cut the functional clocks)
1282 * - an USBHOST interrupt occurs before the module is able to answer
1283 * idle_ack, typically a remote wakeup IRQ.
1284 * Then the USB HOST module will enter a deadlock situation where it
1285 * is no more accessible nor functional.
1288 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1292 * Errata: USB host EHCI may stall when entering smart-standby mode
1296 * When the USBHOST module is set to smart-standby mode, and when it is
1297 * ready to enter the standby state (i.e. all ports are suspended and
1298 * all attached devices are in suspend mode), then it can wrongly assert
1299 * the Mstandby signal too early while there are still some residual OCP
1300 * transactions ongoing. If this condition occurs, the internal state
1301 * machine may go to an undefined state and the USB link may be stuck
1302 * upon the next resume.
1305 * Don't use smart standby; use only force standby,
1306 * hence HWMOD_SWSUP_MSTANDBY
1309 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
1310 .main_clk
= "l3init_60m_fclk",
1313 .clkctrl_offs
= OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET
,
1314 .context_offs
= OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET
,
1315 .modulemode
= MODULEMODE_SWCTRL
,
1321 * 'usb_tll_hs' class
1322 * usb_tll_hs module is the adapter on the usb_host_hs ports
1325 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc
= {
1327 .sysc_offs
= 0x0010,
1328 .syss_offs
= 0x0014,
1329 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1330 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
1331 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1332 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1333 .sysc_fields
= &omap_hwmod_sysc_type1
,
1336 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class
= {
1337 .name
= "usb_tll_hs",
1338 .sysc
= &omap54xx_usb_tll_hs_sysc
,
1341 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod
= {
1342 .name
= "usb_tll_hs",
1343 .class = &omap54xx_usb_tll_hs_hwmod_class
,
1344 .clkdm_name
= "l3init_clkdm",
1345 .main_clk
= "l4_root_clk_div",
1348 .clkctrl_offs
= OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET
,
1349 .context_offs
= OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET
,
1350 .modulemode
= MODULEMODE_HWCTRL
,
1356 * 'usb_otg_ss' class
1357 * 2.0 super speed (usb_otg_ss) controller
1360 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc
= {
1362 .sysc_offs
= 0x0010,
1363 .sysc_flags
= (SYSC_HAS_DMADISABLE
| SYSC_HAS_MIDLEMODE
|
1364 SYSC_HAS_SIDLEMODE
),
1365 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1366 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1367 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1368 .sysc_fields
= &omap_hwmod_sysc_type2
,
1371 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class
= {
1372 .name
= "usb_otg_ss",
1373 .sysc
= &omap54xx_usb_otg_ss_sysc
,
1377 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks
[] = {
1378 { .role
= "refclk960m", .clk
= "usb_otg_ss_refclk960m" },
1381 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod
= {
1382 .name
= "usb_otg_ss",
1383 .class = &omap54xx_usb_otg_ss_hwmod_class
,
1384 .clkdm_name
= "l3init_clkdm",
1385 .flags
= HWMOD_SWSUP_SIDLE
,
1386 .main_clk
= "dpll_core_h13x2_ck",
1389 .clkctrl_offs
= OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET
,
1390 .context_offs
= OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET
,
1391 .modulemode
= MODULEMODE_HWCTRL
,
1394 .opt_clks
= usb_otg_ss_opt_clks
,
1395 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_ss_opt_clks
),
1400 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1401 * overflow condition
1404 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc
= {
1406 .sysc_offs
= 0x0010,
1407 .syss_offs
= 0x0014,
1408 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
1409 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1410 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1412 .sysc_fields
= &omap_hwmod_sysc_type1
,
1415 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class
= {
1417 .sysc
= &omap54xx_wd_timer_sysc
,
1418 .pre_shutdown
= &omap2_wd_timer_disable
,
1422 static struct omap_hwmod omap54xx_wd_timer2_hwmod
= {
1423 .name
= "wd_timer2",
1424 .class = &omap54xx_wd_timer_hwmod_class
,
1425 .clkdm_name
= "wkupaon_clkdm",
1426 .main_clk
= "sys_32k_ck",
1429 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET
,
1430 .context_offs
= OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET
,
1431 .modulemode
= MODULEMODE_SWCTRL
,
1438 * bridge to transform ocp interface protocol to scp (serial control port)
1442 static struct omap_hwmod omap54xx_ocp2scp3_hwmod
;
1443 /* l4_cfg -> ocp2scp3 */
1444 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3
= {
1445 .master
= &omap54xx_l4_cfg_hwmod
,
1446 .slave
= &omap54xx_ocp2scp3_hwmod
,
1447 .clk
= "l4_root_clk_div",
1448 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1451 static struct omap_hwmod omap54xx_ocp2scp3_hwmod
= {
1453 .class = &omap54xx_ocp2scp_hwmod_class
,
1454 .clkdm_name
= "l3init_clkdm",
1457 .clkctrl_offs
= OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET
,
1458 .context_offs
= OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET
,
1459 .modulemode
= MODULEMODE_HWCTRL
,
1466 * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
1469 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc
= {
1471 .sysc_offs
= 0x0000,
1472 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
1473 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1474 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1475 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1476 .sysc_fields
= &omap_hwmod_sysc_type2
,
1479 static struct omap_hwmod_class omap54xx_sata_hwmod_class
= {
1481 .sysc
= &omap54xx_sata_sysc
,
1485 static struct omap_hwmod omap54xx_sata_hwmod
= {
1487 .class = &omap54xx_sata_hwmod_class
,
1488 .clkdm_name
= "l3init_clkdm",
1489 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
1490 .main_clk
= "func_48m_fclk",
1494 .clkctrl_offs
= OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET
,
1495 .context_offs
= OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET
,
1496 .modulemode
= MODULEMODE_SWCTRL
,
1501 /* l4_cfg -> sata */
1502 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata
= {
1503 .master
= &omap54xx_l4_cfg_hwmod
,
1504 .slave
= &omap54xx_sata_hwmod
,
1505 .clk
= "l3_iclk_div",
1506 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1513 /* l3_main_1 -> dmm */
1514 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm
= {
1515 .master
= &omap54xx_l3_main_1_hwmod
,
1516 .slave
= &omap54xx_dmm_hwmod
,
1517 .clk
= "l3_iclk_div",
1518 .user
= OCP_USER_SDMA
,
1521 /* l3_main_3 -> l3_instr */
1522 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr
= {
1523 .master
= &omap54xx_l3_main_3_hwmod
,
1524 .slave
= &omap54xx_l3_instr_hwmod
,
1525 .clk
= "l3_iclk_div",
1526 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1529 /* l3_main_2 -> l3_main_1 */
1530 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1
= {
1531 .master
= &omap54xx_l3_main_2_hwmod
,
1532 .slave
= &omap54xx_l3_main_1_hwmod
,
1533 .clk
= "l3_iclk_div",
1534 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1537 /* l4_cfg -> l3_main_1 */
1538 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1
= {
1539 .master
= &omap54xx_l4_cfg_hwmod
,
1540 .slave
= &omap54xx_l3_main_1_hwmod
,
1541 .clk
= "l3_iclk_div",
1542 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1545 /* l4_cfg -> mmu_dsp */
1546 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp
= {
1547 .master
= &omap54xx_l4_cfg_hwmod
,
1548 .slave
= &omap54xx_mmu_dsp_hwmod
,
1549 .clk
= "l4_root_clk_div",
1550 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1553 /* mpu -> l3_main_1 */
1554 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1
= {
1555 .master
= &omap54xx_mpu_hwmod
,
1556 .slave
= &omap54xx_l3_main_1_hwmod
,
1557 .clk
= "l3_iclk_div",
1558 .user
= OCP_USER_MPU
,
1561 /* l3_main_1 -> l3_main_2 */
1562 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2
= {
1563 .master
= &omap54xx_l3_main_1_hwmod
,
1564 .slave
= &omap54xx_l3_main_2_hwmod
,
1565 .clk
= "l3_iclk_div",
1566 .user
= OCP_USER_MPU
,
1569 /* l4_cfg -> l3_main_2 */
1570 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2
= {
1571 .master
= &omap54xx_l4_cfg_hwmod
,
1572 .slave
= &omap54xx_l3_main_2_hwmod
,
1573 .clk
= "l3_iclk_div",
1574 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1577 /* l3_main_2 -> mmu_ipu */
1578 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu
= {
1579 .master
= &omap54xx_l3_main_2_hwmod
,
1580 .slave
= &omap54xx_mmu_ipu_hwmod
,
1581 .clk
= "l3_iclk_div",
1582 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1585 /* l3_main_1 -> l3_main_3 */
1586 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3
= {
1587 .master
= &omap54xx_l3_main_1_hwmod
,
1588 .slave
= &omap54xx_l3_main_3_hwmod
,
1589 .clk
= "l3_iclk_div",
1590 .user
= OCP_USER_MPU
,
1593 /* l3_main_2 -> l3_main_3 */
1594 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3
= {
1595 .master
= &omap54xx_l3_main_2_hwmod
,
1596 .slave
= &omap54xx_l3_main_3_hwmod
,
1597 .clk
= "l3_iclk_div",
1598 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1601 /* l4_cfg -> l3_main_3 */
1602 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3
= {
1603 .master
= &omap54xx_l4_cfg_hwmod
,
1604 .slave
= &omap54xx_l3_main_3_hwmod
,
1605 .clk
= "l3_iclk_div",
1606 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1609 /* l3_main_1 -> l4_abe */
1610 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe
= {
1611 .master
= &omap54xx_l3_main_1_hwmod
,
1612 .slave
= &omap54xx_l4_abe_hwmod
,
1614 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1618 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe
= {
1619 .master
= &omap54xx_mpu_hwmod
,
1620 .slave
= &omap54xx_l4_abe_hwmod
,
1622 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1625 /* l3_main_1 -> l4_cfg */
1626 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg
= {
1627 .master
= &omap54xx_l3_main_1_hwmod
,
1628 .slave
= &omap54xx_l4_cfg_hwmod
,
1629 .clk
= "l4_root_clk_div",
1630 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1633 /* l3_main_2 -> l4_per */
1634 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per
= {
1635 .master
= &omap54xx_l3_main_2_hwmod
,
1636 .slave
= &omap54xx_l4_per_hwmod
,
1637 .clk
= "l4_root_clk_div",
1638 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1641 /* l3_main_1 -> l4_wkup */
1642 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup
= {
1643 .master
= &omap54xx_l3_main_1_hwmod
,
1644 .slave
= &omap54xx_l4_wkup_hwmod
,
1645 .clk
= "wkupaon_iclk_mux",
1646 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1649 /* mpu -> mpu_private */
1650 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private
= {
1651 .master
= &omap54xx_mpu_hwmod
,
1652 .slave
= &omap54xx_mpu_private_hwmod
,
1653 .clk
= "l3_iclk_div",
1654 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1657 /* l4_wkup -> counter_32k */
1658 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k
= {
1659 .master
= &omap54xx_l4_wkup_hwmod
,
1660 .slave
= &omap54xx_counter_32k_hwmod
,
1661 .clk
= "wkupaon_iclk_mux",
1662 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1665 /* l4_cfg -> dma_system */
1666 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system
= {
1667 .master
= &omap54xx_l4_cfg_hwmod
,
1668 .slave
= &omap54xx_dma_system_hwmod
,
1669 .clk
= "l4_root_clk_div",
1670 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1673 /* l4_abe -> dmic */
1674 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic
= {
1675 .master
= &omap54xx_l4_abe_hwmod
,
1676 .slave
= &omap54xx_dmic_hwmod
,
1678 .user
= OCP_USER_MPU
,
1681 /* l3_main_2 -> dss */
1682 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss
= {
1683 .master
= &omap54xx_l3_main_2_hwmod
,
1684 .slave
= &omap54xx_dss_hwmod
,
1685 .clk
= "l3_iclk_div",
1686 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1689 /* l3_main_2 -> dss_dispc */
1690 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc
= {
1691 .master
= &omap54xx_l3_main_2_hwmod
,
1692 .slave
= &omap54xx_dss_dispc_hwmod
,
1693 .clk
= "l3_iclk_div",
1694 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1697 /* l3_main_2 -> dss_dsi1_a */
1698 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a
= {
1699 .master
= &omap54xx_l3_main_2_hwmod
,
1700 .slave
= &omap54xx_dss_dsi1_a_hwmod
,
1701 .clk
= "l3_iclk_div",
1702 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1705 /* l3_main_2 -> dss_dsi1_c */
1706 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c
= {
1707 .master
= &omap54xx_l3_main_2_hwmod
,
1708 .slave
= &omap54xx_dss_dsi1_c_hwmod
,
1709 .clk
= "l3_iclk_div",
1710 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1713 /* l3_main_2 -> dss_hdmi */
1714 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi
= {
1715 .master
= &omap54xx_l3_main_2_hwmod
,
1716 .slave
= &omap54xx_dss_hdmi_hwmod
,
1717 .clk
= "l3_iclk_div",
1718 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1721 /* l3_main_2 -> dss_rfbi */
1722 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi
= {
1723 .master
= &omap54xx_l3_main_2_hwmod
,
1724 .slave
= &omap54xx_dss_rfbi_hwmod
,
1725 .clk
= "l3_iclk_div",
1726 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1730 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1
= {
1731 .master
= &omap54xx_mpu_hwmod
,
1732 .slave
= &omap54xx_emif1_hwmod
,
1733 .clk
= "dpll_core_h11x2_ck",
1734 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1738 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2
= {
1739 .master
= &omap54xx_mpu_hwmod
,
1740 .slave
= &omap54xx_emif2_hwmod
,
1741 .clk
= "dpll_core_h11x2_ck",
1742 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1745 /* l4_wkup -> kbd */
1746 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd
= {
1747 .master
= &omap54xx_l4_wkup_hwmod
,
1748 .slave
= &omap54xx_kbd_hwmod
,
1749 .clk
= "wkupaon_iclk_mux",
1750 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1753 /* l4_cfg -> mailbox */
1754 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox
= {
1755 .master
= &omap54xx_l4_cfg_hwmod
,
1756 .slave
= &omap54xx_mailbox_hwmod
,
1757 .clk
= "l4_root_clk_div",
1758 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1761 /* l4_abe -> mcbsp1 */
1762 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1
= {
1763 .master
= &omap54xx_l4_abe_hwmod
,
1764 .slave
= &omap54xx_mcbsp1_hwmod
,
1766 .user
= OCP_USER_MPU
,
1769 /* l4_abe -> mcbsp2 */
1770 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2
= {
1771 .master
= &omap54xx_l4_abe_hwmod
,
1772 .slave
= &omap54xx_mcbsp2_hwmod
,
1774 .user
= OCP_USER_MPU
,
1777 /* l4_abe -> mcbsp3 */
1778 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3
= {
1779 .master
= &omap54xx_l4_abe_hwmod
,
1780 .slave
= &omap54xx_mcbsp3_hwmod
,
1782 .user
= OCP_USER_MPU
,
1785 /* l4_abe -> mcpdm */
1786 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm
= {
1787 .master
= &omap54xx_l4_abe_hwmod
,
1788 .slave
= &omap54xx_mcpdm_hwmod
,
1790 .user
= OCP_USER_MPU
,
1793 /* l4_per -> mcspi1 */
1794 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1
= {
1795 .master
= &omap54xx_l4_per_hwmod
,
1796 .slave
= &omap54xx_mcspi1_hwmod
,
1797 .clk
= "l4_root_clk_div",
1798 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1801 /* l4_per -> mcspi2 */
1802 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2
= {
1803 .master
= &omap54xx_l4_per_hwmod
,
1804 .slave
= &omap54xx_mcspi2_hwmod
,
1805 .clk
= "l4_root_clk_div",
1806 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1809 /* l4_per -> mcspi3 */
1810 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3
= {
1811 .master
= &omap54xx_l4_per_hwmod
,
1812 .slave
= &omap54xx_mcspi3_hwmod
,
1813 .clk
= "l4_root_clk_div",
1814 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1817 /* l4_per -> mcspi4 */
1818 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4
= {
1819 .master
= &omap54xx_l4_per_hwmod
,
1820 .slave
= &omap54xx_mcspi4_hwmod
,
1821 .clk
= "l4_root_clk_div",
1822 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1826 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu
= {
1827 .master
= &omap54xx_l4_cfg_hwmod
,
1828 .slave
= &omap54xx_mpu_hwmod
,
1829 .clk
= "l4_root_clk_div",
1830 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1833 /* l4_cfg -> spinlock */
1834 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock
= {
1835 .master
= &omap54xx_l4_cfg_hwmod
,
1836 .slave
= &omap54xx_spinlock_hwmod
,
1837 .clk
= "l4_root_clk_div",
1838 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1841 /* l4_cfg -> ocp2scp1 */
1842 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1
= {
1843 .master
= &omap54xx_l4_cfg_hwmod
,
1844 .slave
= &omap54xx_ocp2scp1_hwmod
,
1845 .clk
= "l4_root_clk_div",
1846 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1849 /* l4_wkup -> timer1 */
1850 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1
= {
1851 .master
= &omap54xx_l4_wkup_hwmod
,
1852 .slave
= &omap54xx_timer1_hwmod
,
1853 .clk
= "wkupaon_iclk_mux",
1854 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1857 /* l4_per -> timer2 */
1858 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2
= {
1859 .master
= &omap54xx_l4_per_hwmod
,
1860 .slave
= &omap54xx_timer2_hwmod
,
1861 .clk
= "l4_root_clk_div",
1862 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1865 /* l4_per -> timer3 */
1866 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3
= {
1867 .master
= &omap54xx_l4_per_hwmod
,
1868 .slave
= &omap54xx_timer3_hwmod
,
1869 .clk
= "l4_root_clk_div",
1870 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1873 /* l4_per -> timer4 */
1874 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4
= {
1875 .master
= &omap54xx_l4_per_hwmod
,
1876 .slave
= &omap54xx_timer4_hwmod
,
1877 .clk
= "l4_root_clk_div",
1878 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1881 /* l4_abe -> timer5 */
1882 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5
= {
1883 .master
= &omap54xx_l4_abe_hwmod
,
1884 .slave
= &omap54xx_timer5_hwmod
,
1886 .user
= OCP_USER_MPU
,
1889 /* l4_abe -> timer6 */
1890 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6
= {
1891 .master
= &omap54xx_l4_abe_hwmod
,
1892 .slave
= &omap54xx_timer6_hwmod
,
1894 .user
= OCP_USER_MPU
,
1897 /* l4_abe -> timer7 */
1898 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7
= {
1899 .master
= &omap54xx_l4_abe_hwmod
,
1900 .slave
= &omap54xx_timer7_hwmod
,
1902 .user
= OCP_USER_MPU
,
1905 /* l4_abe -> timer8 */
1906 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8
= {
1907 .master
= &omap54xx_l4_abe_hwmod
,
1908 .slave
= &omap54xx_timer8_hwmod
,
1910 .user
= OCP_USER_MPU
,
1913 /* l4_per -> timer9 */
1914 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9
= {
1915 .master
= &omap54xx_l4_per_hwmod
,
1916 .slave
= &omap54xx_timer9_hwmod
,
1917 .clk
= "l4_root_clk_div",
1918 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1921 /* l4_per -> timer10 */
1922 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10
= {
1923 .master
= &omap54xx_l4_per_hwmod
,
1924 .slave
= &omap54xx_timer10_hwmod
,
1925 .clk
= "l4_root_clk_div",
1926 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1929 /* l4_per -> timer11 */
1930 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11
= {
1931 .master
= &omap54xx_l4_per_hwmod
,
1932 .slave
= &omap54xx_timer11_hwmod
,
1933 .clk
= "l4_root_clk_div",
1934 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1937 /* l4_cfg -> usb_host_hs */
1938 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs
= {
1939 .master
= &omap54xx_l4_cfg_hwmod
,
1940 .slave
= &omap54xx_usb_host_hs_hwmod
,
1941 .clk
= "l3_iclk_div",
1942 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1945 /* l4_cfg -> usb_tll_hs */
1946 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs
= {
1947 .master
= &omap54xx_l4_cfg_hwmod
,
1948 .slave
= &omap54xx_usb_tll_hs_hwmod
,
1949 .clk
= "l4_root_clk_div",
1950 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1953 /* l4_cfg -> usb_otg_ss */
1954 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss
= {
1955 .master
= &omap54xx_l4_cfg_hwmod
,
1956 .slave
= &omap54xx_usb_otg_ss_hwmod
,
1957 .clk
= "dpll_core_h13x2_ck",
1958 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1961 /* l4_wkup -> wd_timer2 */
1962 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2
= {
1963 .master
= &omap54xx_l4_wkup_hwmod
,
1964 .slave
= &omap54xx_wd_timer2_hwmod
,
1965 .clk
= "wkupaon_iclk_mux",
1966 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1969 static struct omap_hwmod_ocp_if
*omap54xx_hwmod_ocp_ifs
[] __initdata
= {
1970 &omap54xx_l3_main_1__dmm
,
1971 &omap54xx_l3_main_3__l3_instr
,
1972 &omap54xx_l3_main_2__l3_main_1
,
1973 &omap54xx_l4_cfg__l3_main_1
,
1974 &omap54xx_mpu__l3_main_1
,
1975 &omap54xx_l3_main_1__l3_main_2
,
1976 &omap54xx_l4_cfg__l3_main_2
,
1977 &omap54xx_l3_main_1__l3_main_3
,
1978 &omap54xx_l3_main_2__l3_main_3
,
1979 &omap54xx_l4_cfg__l3_main_3
,
1980 &omap54xx_l3_main_1__l4_abe
,
1981 &omap54xx_mpu__l4_abe
,
1982 &omap54xx_l3_main_1__l4_cfg
,
1983 &omap54xx_l3_main_2__l4_per
,
1984 &omap54xx_l3_main_1__l4_wkup
,
1985 &omap54xx_mpu__mpu_private
,
1986 &omap54xx_l4_wkup__counter_32k
,
1987 &omap54xx_l4_cfg__dma_system
,
1988 &omap54xx_l4_abe__dmic
,
1989 &omap54xx_l4_cfg__mmu_dsp
,
1990 &omap54xx_l3_main_2__dss
,
1991 &omap54xx_l3_main_2__dss_dispc
,
1992 &omap54xx_l3_main_2__dss_dsi1_a
,
1993 &omap54xx_l3_main_2__dss_dsi1_c
,
1994 &omap54xx_l3_main_2__dss_hdmi
,
1995 &omap54xx_l3_main_2__dss_rfbi
,
1996 &omap54xx_mpu__emif1
,
1997 &omap54xx_mpu__emif2
,
1998 &omap54xx_l3_main_2__mmu_ipu
,
1999 &omap54xx_l4_wkup__kbd
,
2000 &omap54xx_l4_cfg__mailbox
,
2001 &omap54xx_l4_abe__mcbsp1
,
2002 &omap54xx_l4_abe__mcbsp2
,
2003 &omap54xx_l4_abe__mcbsp3
,
2004 &omap54xx_l4_abe__mcpdm
,
2005 &omap54xx_l4_per__mcspi1
,
2006 &omap54xx_l4_per__mcspi2
,
2007 &omap54xx_l4_per__mcspi3
,
2008 &omap54xx_l4_per__mcspi4
,
2009 &omap54xx_l4_cfg__mpu
,
2010 &omap54xx_l4_cfg__spinlock
,
2011 &omap54xx_l4_cfg__ocp2scp1
,
2012 &omap54xx_l4_wkup__timer1
,
2013 &omap54xx_l4_per__timer2
,
2014 &omap54xx_l4_per__timer3
,
2015 &omap54xx_l4_per__timer4
,
2016 &omap54xx_l4_abe__timer5
,
2017 &omap54xx_l4_abe__timer6
,
2018 &omap54xx_l4_abe__timer7
,
2019 &omap54xx_l4_abe__timer8
,
2020 &omap54xx_l4_per__timer9
,
2021 &omap54xx_l4_per__timer10
,
2022 &omap54xx_l4_per__timer11
,
2023 &omap54xx_l4_cfg__usb_host_hs
,
2024 &omap54xx_l4_cfg__usb_tll_hs
,
2025 &omap54xx_l4_cfg__usb_otg_ss
,
2026 &omap54xx_l4_wkup__wd_timer2
,
2027 &omap54xx_l4_cfg__ocp2scp3
,
2028 &omap54xx_l4_cfg__sata
,
2032 int __init
omap54xx_hwmod_init(void)
2035 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs
);