2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
32 #include <plat/sram.h>
33 #include <plat/clockdomain.h>
34 #include <plat/powerdomain.h>
35 #include <plat/control.h>
36 #include <plat/serial.h>
37 #include <plat/sdrc.h>
38 #include <plat/prcm.h>
39 #include <plat/gpmc.h>
41 #include <plat/dmtimer.h>
43 #include <asm/tlbflush.h>
46 #include "cm-regbits-34xx.h"
47 #include "prm-regbits-34xx.h"
53 /* Scratchpad offsets */
54 #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
55 #define OMAP343X_TABLE_VALUE_OFFSET 0x30
56 #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
60 u32 wakeup_timer_seconds
;
63 struct powerdomain
*pwrdm
;
68 struct list_head node
;
71 static LIST_HEAD(pwrst_list
);
73 static void (*_omap_sram_idle
)(u32
*addr
, int save_state
);
75 static int (*_omap_save_secure_sram
)(u32
*addr
);
77 static struct powerdomain
*mpu_pwrdm
, *neon_pwrdm
;
78 static struct powerdomain
*core_pwrdm
, *per_pwrdm
;
79 static struct powerdomain
*cam_pwrdm
;
81 static inline void omap3_per_save_context(void)
83 omap_gpio_save_context();
86 static inline void omap3_per_restore_context(void)
88 omap_gpio_restore_context();
91 static void omap3_enable_io_chain(void)
95 if (omap_rev() >= OMAP3430_REV_ES3_1
) {
96 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN
, WKUP_MOD
, PM_WKEN
);
97 /* Do a readback to assure write has been done */
98 prm_read_mod_reg(WKUP_MOD
, PM_WKEN
);
100 while (!(prm_read_mod_reg(WKUP_MOD
, PM_WKST
) &
101 OMAP3430_ST_IO_CHAIN
)) {
103 if (timeout
> 1000) {
104 printk(KERN_ERR
"Wake up daisy chain "
105 "activation failed.\n");
108 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN
,
114 static void omap3_disable_io_chain(void)
116 if (omap_rev() >= OMAP3430_REV_ES3_1
)
117 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN
, WKUP_MOD
, PM_WKEN
);
120 static void omap3_core_save_context(void)
122 u32 control_padconf_off
;
124 /* Save the padconf registers */
125 control_padconf_off
= omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF
);
126 control_padconf_off
|= START_PADCONF_SAVE
;
127 omap_ctrl_writel(control_padconf_off
, OMAP343X_CONTROL_PADCONF_OFF
);
128 /* wait for the save to complete */
129 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS
)
130 & PADCONF_SAVE_DONE
))
134 * Force write last pad into memory, as this can fail in some
135 * cases according to erratas 1.157, 1.185
137 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14
),
138 OMAP343X_CONTROL_MEM_WKUP
+ 0x2a0);
140 /* Save the Interrupt controller context */
141 omap_intc_save_context();
142 /* Save the GPMC context */
143 omap3_gpmc_save_context();
144 /* Save the system control module context, padconf already save above*/
145 omap3_control_save_context();
146 omap_dma_global_context_save();
149 static void omap3_core_restore_context(void)
151 /* Restore the control module context, padconf restored by h/w */
152 omap3_control_restore_context();
153 /* Restore the GPMC context */
154 omap3_gpmc_restore_context();
155 /* Restore the interrupt controller context */
156 omap_intc_restore_context();
157 omap_dma_global_context_restore();
161 * FIXME: This function should be called before entering off-mode after
162 * OMAP3 secure services have been accessed. Currently it is only called
163 * once during boot sequence, but this works as we are not using secure
166 static void omap3_save_secure_ram_context(u32 target_mpu_state
)
170 if (omap_type() != OMAP2_DEVICE_TYPE_GP
) {
172 * MPU next state must be set to POWER_ON temporarily,
173 * otherwise the WFI executed inside the ROM code
174 * will hang the system.
176 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_ON
);
177 ret
= _omap_save_secure_sram((u32
*)
178 __pa(omap3_secure_ram_storage
));
179 pwrdm_set_next_pwrst(mpu_pwrdm
, target_mpu_state
);
180 /* Following is for error tracking, it should not happen */
182 printk(KERN_ERR
"save_secure_sram() returns %08x\n",
191 * PRCM Interrupt Handler Helper Function
193 * The purpose of this function is to clear any wake-up events latched
194 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
195 * may occur whilst attempting to clear a PM_WKST_x register and thus
196 * set another bit in this register. A while loop is used to ensure
197 * that any peripheral wake-up events occurring while attempting to
198 * clear the PM_WKST_x are detected and cleared.
200 static int prcm_clear_mod_irqs(s16 module
, u8 regs
)
202 u32 wkst
, fclk
, iclk
, clken
;
203 u16 wkst_off
= (regs
== 3) ? OMAP3430ES2_PM_WKST3
: PM_WKST1
;
204 u16 fclk_off
= (regs
== 3) ? OMAP3430ES2_CM_FCLKEN3
: CM_FCLKEN1
;
205 u16 iclk_off
= (regs
== 3) ? CM_ICLKEN3
: CM_ICLKEN1
;
206 u16 grpsel_off
= (regs
== 3) ?
207 OMAP3430ES2_PM_MPUGRPSEL3
: OMAP3430_PM_MPUGRPSEL
;
210 wkst
= prm_read_mod_reg(module
, wkst_off
);
211 wkst
&= prm_read_mod_reg(module
, grpsel_off
);
213 iclk
= cm_read_mod_reg(module
, iclk_off
);
214 fclk
= cm_read_mod_reg(module
, fclk_off
);
217 cm_set_mod_reg_bits(clken
, module
, iclk_off
);
219 * For USBHOST, we don't know whether HOST1 or
220 * HOST2 woke us up, so enable both f-clocks
222 if (module
== OMAP3430ES2_USBHOST_MOD
)
223 clken
|= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT
;
224 cm_set_mod_reg_bits(clken
, module
, fclk_off
);
225 prm_write_mod_reg(wkst
, module
, wkst_off
);
226 wkst
= prm_read_mod_reg(module
, wkst_off
);
229 cm_write_mod_reg(iclk
, module
, iclk_off
);
230 cm_write_mod_reg(fclk
, module
, fclk_off
);
236 static int _prcm_int_handle_wakeup(void)
240 c
= prcm_clear_mod_irqs(WKUP_MOD
, 1);
241 c
+= prcm_clear_mod_irqs(CORE_MOD
, 1);
242 c
+= prcm_clear_mod_irqs(OMAP3430_PER_MOD
, 1);
243 if (omap_rev() > OMAP3430_REV_ES1_0
) {
244 c
+= prcm_clear_mod_irqs(CORE_MOD
, 3);
245 c
+= prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD
, 1);
252 * PRCM Interrupt Handler
254 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
255 * interrupts from the PRCM for the MPU. These bits must be cleared in
256 * order to clear the PRCM interrupt. The PRCM interrupt handler is
257 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
258 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
259 * register indicates that a wake-up event is pending for the MPU and
260 * this bit can only be cleared if the all the wake-up events latched
261 * in the various PM_WKST_x registers have been cleared. The interrupt
262 * handler is implemented using a do-while loop so that if a wake-up
263 * event occurred during the processing of the prcm interrupt handler
264 * (setting a bit in the corresponding PM_WKST_x register and thus
265 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
266 * this would be handled.
268 static irqreturn_t
prcm_interrupt_handler (int irq
, void *dev_id
)
274 irqstatus_mpu
= prm_read_mod_reg(OCP_MOD
,
275 OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
277 if (irqstatus_mpu
& (OMAP3430_WKUP_ST
| OMAP3430_IO_ST
)) {
278 c
= _prcm_int_handle_wakeup();
281 * Is the MPU PRCM interrupt handler racing with the
282 * IVA2 PRCM interrupt handler ?
284 WARN(c
== 0, "prcm: WARNING: PRCM indicated MPU wakeup "
285 "but no wakeup sources are marked\n");
287 /* XXX we need to expand our PRCM interrupt handler */
288 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
289 "no code to handle it (%08x)\n", irqstatus_mpu
);
292 prm_write_mod_reg(irqstatus_mpu
, OCP_MOD
,
293 OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
295 } while (prm_read_mod_reg(OCP_MOD
, OMAP3_PRM_IRQSTATUS_MPU_OFFSET
));
300 static void restore_control_register(u32 val
)
302 __asm__
__volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val
));
305 /* Function to restore the table entry that was modified for enabling MMU */
306 static void restore_table_entry(void)
308 u32
*scratchpad_address
;
309 u32 previous_value
, control_reg_value
;
312 scratchpad_address
= OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD
);
314 /* Get address of entry that was modified */
315 address
= (u32
*)__raw_readl(scratchpad_address
+
316 OMAP343X_TABLE_ADDRESS_OFFSET
);
317 /* Get the previous value which needs to be restored */
318 previous_value
= __raw_readl(scratchpad_address
+
319 OMAP343X_TABLE_VALUE_OFFSET
);
320 address
= __va(address
);
321 *address
= previous_value
;
323 control_reg_value
= __raw_readl(scratchpad_address
324 + OMAP343X_CONTROL_REG_VALUE_OFFSET
);
325 /* This will enable caches and prediction */
326 restore_control_register(control_reg_value
);
329 void omap_sram_idle(void)
331 /* Variable to tell what needs to be saved and restored
332 * in omap_sram_idle*/
333 /* save_state = 0 => Nothing to save and restored */
334 /* save_state = 1 => Only L1 and logic lost */
335 /* save_state = 2 => Only L2 lost */
336 /* save_state = 3 => L1, L2 and logic lost */
338 int mpu_next_state
= PWRDM_POWER_ON
;
339 int per_next_state
= PWRDM_POWER_ON
;
340 int core_next_state
= PWRDM_POWER_ON
;
341 int core_prev_state
, per_prev_state
;
343 int per_state_modified
= 0;
345 if (!_omap_sram_idle
)
348 pwrdm_clear_all_prev_pwrst(mpu_pwrdm
);
349 pwrdm_clear_all_prev_pwrst(neon_pwrdm
);
350 pwrdm_clear_all_prev_pwrst(core_pwrdm
);
351 pwrdm_clear_all_prev_pwrst(per_pwrdm
);
353 mpu_next_state
= pwrdm_read_next_pwrst(mpu_pwrdm
);
354 switch (mpu_next_state
) {
356 case PWRDM_POWER_RET
:
357 /* No need to save context */
360 case PWRDM_POWER_OFF
:
365 printk(KERN_ERR
"Invalid mpu state in sram_idle\n");
368 pwrdm_pre_transition();
371 if (pwrdm_read_pwrst(neon_pwrdm
) == PWRDM_POWER_ON
)
372 pwrdm_set_next_pwrst(neon_pwrdm
, mpu_next_state
);
375 per_next_state
= pwrdm_read_next_pwrst(per_pwrdm
);
376 core_next_state
= pwrdm_read_next_pwrst(core_pwrdm
);
377 if (per_next_state
< PWRDM_POWER_ON
) {
378 omap_uart_prepare_idle(2);
379 omap2_gpio_prepare_for_retention();
380 if (per_next_state
== PWRDM_POWER_OFF
) {
381 if (core_next_state
== PWRDM_POWER_ON
) {
382 per_next_state
= PWRDM_POWER_RET
;
383 pwrdm_set_next_pwrst(per_pwrdm
, per_next_state
);
384 per_state_modified
= 1;
386 omap3_per_save_context();
390 if (pwrdm_read_pwrst(cam_pwrdm
) == PWRDM_POWER_ON
)
391 omap2_clkdm_deny_idle(mpu_pwrdm
->pwrdm_clkdms
[0]);
394 if (core_next_state
< PWRDM_POWER_ON
) {
395 omap_uart_prepare_idle(0);
396 omap_uart_prepare_idle(1);
397 if (core_next_state
== PWRDM_POWER_OFF
) {
398 omap3_core_save_context();
399 omap3_prcm_save_context();
401 /* Enable IO-PAD and IO-CHAIN wakeups */
402 prm_set_mod_reg_bits(OMAP3430_EN_IO
, WKUP_MOD
, PM_WKEN
);
403 omap3_enable_io_chain();
405 omap3_intc_prepare_idle();
408 * On EMU/HS devices ROM code restores a SRDC value
409 * from scratchpad which has automatic self refresh on timeout
410 * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
411 * Hence store/restore the SDRC_POWER register here.
413 if (omap_rev() >= OMAP3430_REV_ES3_0
&&
414 omap_type() != OMAP2_DEVICE_TYPE_GP
&&
415 core_next_state
== PWRDM_POWER_OFF
)
416 sdrc_pwr
= sdrc_read_reg(SDRC_POWER
);
419 * omap3_arm_context is the location where ARM registers
420 * get saved. The restore path then reads from this
421 * location and restores them back.
423 _omap_sram_idle(omap3_arm_context
, save_state
);
426 /* Restore normal SDRC POWER settings */
427 if (omap_rev() >= OMAP3430_REV_ES3_0
&&
428 omap_type() != OMAP2_DEVICE_TYPE_GP
&&
429 core_next_state
== PWRDM_POWER_OFF
)
430 sdrc_write_reg(sdrc_pwr
, SDRC_POWER
);
432 /* Restore table entry modified during MMU restoration */
433 if (pwrdm_read_prev_pwrst(mpu_pwrdm
) == PWRDM_POWER_OFF
)
434 restore_table_entry();
437 if (core_next_state
< PWRDM_POWER_ON
) {
438 core_prev_state
= pwrdm_read_prev_pwrst(core_pwrdm
);
439 if (core_prev_state
== PWRDM_POWER_OFF
) {
440 omap3_core_restore_context();
441 omap3_prcm_restore_context();
442 omap3_sram_restore_context();
443 omap2_sms_restore_context();
445 omap_uart_resume_idle(0);
446 omap_uart_resume_idle(1);
447 if (core_next_state
== PWRDM_POWER_OFF
)
448 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF
,
450 OMAP3_PRM_VOLTCTRL_OFFSET
);
452 omap3_intc_resume_idle();
455 if (per_next_state
< PWRDM_POWER_ON
) {
456 per_prev_state
= pwrdm_read_prev_pwrst(per_pwrdm
);
457 if (per_prev_state
== PWRDM_POWER_OFF
)
458 omap3_per_restore_context();
459 omap2_gpio_resume_after_retention();
460 omap_uart_resume_idle(2);
461 if (per_state_modified
)
462 pwrdm_set_next_pwrst(per_pwrdm
, PWRDM_POWER_OFF
);
465 /* Disable IO-PAD and IO-CHAIN wakeup */
466 if (core_next_state
< PWRDM_POWER_ON
) {
467 prm_clear_mod_reg_bits(OMAP3430_EN_IO
, WKUP_MOD
, PM_WKEN
);
468 omap3_disable_io_chain();
471 pwrdm_post_transition();
473 omap2_clkdm_allow_idle(mpu_pwrdm
->pwrdm_clkdms
[0]);
476 int omap3_can_sleep(void)
478 if (!sleep_while_idle
)
480 if (!omap_uart_can_sleep())
485 /* This sets pwrdm state (other than mpu & core. Currently only ON &
486 * RET are supported. Function is assuming that clkdm doesn't have
487 * hw_sup mode enabled. */
488 int set_pwrdm_state(struct powerdomain
*pwrdm
, u32 state
)
491 int sleep_switch
= 0;
494 if (pwrdm
== NULL
|| IS_ERR(pwrdm
))
497 while (!(pwrdm
->pwrsts
& (1 << state
))) {
498 if (state
== PWRDM_POWER_OFF
)
503 cur_state
= pwrdm_read_next_pwrst(pwrdm
);
504 if (cur_state
== state
)
507 if (pwrdm_read_pwrst(pwrdm
) < PWRDM_POWER_ON
) {
508 omap2_clkdm_wakeup(pwrdm
->pwrdm_clkdms
[0]);
510 pwrdm_wait_transition(pwrdm
);
513 ret
= pwrdm_set_next_pwrst(pwrdm
, state
);
515 printk(KERN_ERR
"Unable to set state of powerdomain: %s\n",
521 omap2_clkdm_allow_idle(pwrdm
->pwrdm_clkdms
[0]);
522 pwrdm_wait_transition(pwrdm
);
523 pwrdm_state_switch(pwrdm
);
530 static void omap3_pm_idle(void)
535 if (!omap3_can_sleep())
538 if (omap_irq_pending() || need_resched())
548 #ifdef CONFIG_SUSPEND
549 static suspend_state_t suspend_state
;
551 static void omap2_pm_wakeup_on_timer(u32 seconds
)
553 u32 tick_rate
, cycles
;
558 tick_rate
= clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup
));
559 cycles
= tick_rate
* seconds
;
560 omap_dm_timer_stop(gptimer_wakeup
);
561 omap_dm_timer_set_load_start(gptimer_wakeup
, 0, 0xffffffff - cycles
);
563 pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n",
564 seconds
, cycles
, tick_rate
);
567 static int omap3_pm_prepare(void)
573 static int omap3_pm_suspend(void)
575 struct power_state
*pwrst
;
578 if (wakeup_timer_seconds
)
579 omap2_pm_wakeup_on_timer(wakeup_timer_seconds
);
581 /* Read current next_pwrsts */
582 list_for_each_entry(pwrst
, &pwrst_list
, node
)
583 pwrst
->saved_state
= pwrdm_read_next_pwrst(pwrst
->pwrdm
);
584 /* Set ones wanted by suspend */
585 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
586 if (set_pwrdm_state(pwrst
->pwrdm
, pwrst
->next_state
))
588 if (pwrdm_clear_all_prev_pwrst(pwrst
->pwrdm
))
592 omap_uart_prepare_suspend();
593 omap3_intc_suspend();
598 /* Restore next_pwrsts */
599 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
600 state
= pwrdm_read_prev_pwrst(pwrst
->pwrdm
);
601 if (state
> pwrst
->next_state
) {
602 printk(KERN_INFO
"Powerdomain (%s) didn't enter "
604 pwrst
->pwrdm
->name
, pwrst
->next_state
);
607 set_pwrdm_state(pwrst
->pwrdm
, pwrst
->saved_state
);
610 printk(KERN_ERR
"Could not enter target state in pm_suspend\n");
612 printk(KERN_INFO
"Successfully put all powerdomains "
613 "to target state\n");
618 static int omap3_pm_enter(suspend_state_t unused
)
622 switch (suspend_state
) {
623 case PM_SUSPEND_STANDBY
:
625 ret
= omap3_pm_suspend();
634 static void omap3_pm_finish(void)
639 /* Hooks to enable / disable UART interrupts during suspend */
640 static int omap3_pm_begin(suspend_state_t state
)
642 suspend_state
= state
;
643 omap_uart_enable_irqs(0);
647 static void omap3_pm_end(void)
649 suspend_state
= PM_SUSPEND_ON
;
650 omap_uart_enable_irqs(1);
654 static struct platform_suspend_ops omap_pm_ops
= {
655 .begin
= omap3_pm_begin
,
657 .prepare
= omap3_pm_prepare
,
658 .enter
= omap3_pm_enter
,
659 .finish
= omap3_pm_finish
,
660 .valid
= suspend_valid_only_mem
,
662 #endif /* CONFIG_SUSPEND */
666 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
669 * In cases where IVA2 is activated by bootcode, it may prevent
670 * full-chip retention or off-mode because it is not idle. This
671 * function forces the IVA2 into idle state so it can go
672 * into retention/off and thus allow full-chip retention/off.
675 static void __init
omap3_iva_idle(void)
677 /* ensure IVA2 clock is disabled */
678 cm_write_mod_reg(0, OMAP3430_IVA2_MOD
, CM_FCLKEN
);
680 /* if no clock activity, nothing else to do */
681 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD
, OMAP3430_CM_CLKSTST
) &
682 OMAP3430_CLKACTIVITY_IVA2_MASK
))
686 prm_write_mod_reg(OMAP3430_RST1_IVA2
|
689 OMAP3430_IVA2_MOD
, OMAP2_RM_RSTCTRL
);
691 /* Enable IVA2 clock */
692 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK
,
693 OMAP3430_IVA2_MOD
, CM_FCLKEN
);
695 /* Set IVA2 boot mode to 'idle' */
696 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE
,
697 OMAP343X_CONTROL_IVA2_BOOTMOD
);
700 prm_write_mod_reg(0, OMAP3430_IVA2_MOD
, OMAP2_RM_RSTCTRL
);
702 /* Disable IVA2 clock */
703 cm_write_mod_reg(0, OMAP3430_IVA2_MOD
, CM_FCLKEN
);
706 prm_write_mod_reg(OMAP3430_RST1_IVA2
|
709 OMAP3430_IVA2_MOD
, OMAP2_RM_RSTCTRL
);
712 static void __init
omap3_d2d_idle(void)
716 /* In a stand alone OMAP3430 where there is not a stacked
717 * modem for the D2D Idle Ack and D2D MStandby must be pulled
718 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
719 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
720 mask
= (1 << 4) | (1 << 3); /* pull-up, enabled */
721 padconf
= omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY
);
723 omap_ctrl_writew(padconf
, OMAP3_PADCONF_SAD2D_MSTANDBY
);
725 padconf
= omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK
);
727 omap_ctrl_writew(padconf
, OMAP3_PADCONF_SAD2D_IDLEACK
);
730 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON
|
731 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST
,
732 CORE_MOD
, OMAP2_RM_RSTCTRL
);
733 prm_write_mod_reg(0, CORE_MOD
, OMAP2_RM_RSTCTRL
);
736 static void __init
prcm_setup_regs(void)
738 /* XXX Reset all wkdeps. This should be done when initializing
740 prm_write_mod_reg(0, OMAP3430_IVA2_MOD
, PM_WKDEP
);
741 prm_write_mod_reg(0, MPU_MOD
, PM_WKDEP
);
742 prm_write_mod_reg(0, OMAP3430_DSS_MOD
, PM_WKDEP
);
743 prm_write_mod_reg(0, OMAP3430_NEON_MOD
, PM_WKDEP
);
744 prm_write_mod_reg(0, OMAP3430_CAM_MOD
, PM_WKDEP
);
745 prm_write_mod_reg(0, OMAP3430_PER_MOD
, PM_WKDEP
);
746 if (omap_rev() > OMAP3430_REV_ES1_0
) {
747 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD
, PM_WKDEP
);
748 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD
, PM_WKDEP
);
750 prm_write_mod_reg(0, GFX_MOD
, PM_WKDEP
);
753 * Enable interface clock autoidle for all modules.
754 * Note that in the long run this should be done by clockfw
757 OMAP3430_AUTO_MODEM
|
758 OMAP3430ES2_AUTO_MMC3
|
759 OMAP3430ES2_AUTO_ICR
|
761 OMAP3430_AUTO_SHA12
|
765 OMAP3430_AUTO_MSPRO
|
767 OMAP3430_AUTO_MCSPI4
|
768 OMAP3430_AUTO_MCSPI3
|
769 OMAP3430_AUTO_MCSPI2
|
770 OMAP3430_AUTO_MCSPI1
|
774 OMAP3430_AUTO_UART2
|
775 OMAP3430_AUTO_UART1
|
776 OMAP3430_AUTO_GPT11
|
777 OMAP3430_AUTO_GPT10
|
778 OMAP3430_AUTO_MCBSP5
|
779 OMAP3430_AUTO_MCBSP1
|
780 OMAP3430ES1_AUTO_FAC
| /* This is es1 only */
781 OMAP3430_AUTO_MAILBOXES
|
782 OMAP3430_AUTO_OMAPCTRL
|
783 OMAP3430ES1_AUTO_FSHOSTUSB
|
784 OMAP3430_AUTO_HSOTGUSB
|
785 OMAP3430_AUTO_SAD2D
|
787 CORE_MOD
, CM_AUTOIDLE1
);
793 OMAP3430_AUTO_SHA11
|
795 CORE_MOD
, CM_AUTOIDLE2
);
797 if (omap_rev() > OMAP3430_REV_ES1_0
) {
799 OMAP3430_AUTO_MAD2D
|
800 OMAP3430ES2_AUTO_USBTLL
,
801 CORE_MOD
, CM_AUTOIDLE3
);
807 OMAP3430_AUTO_GPIO1
|
808 OMAP3430_AUTO_32KSYNC
|
809 OMAP3430_AUTO_GPT12
|
811 WKUP_MOD
, CM_AUTOIDLE
);
824 OMAP3430_AUTO_GPIO6
|
825 OMAP3430_AUTO_GPIO5
|
826 OMAP3430_AUTO_GPIO4
|
827 OMAP3430_AUTO_GPIO3
|
828 OMAP3430_AUTO_GPIO2
|
830 OMAP3430_AUTO_UART3
|
839 OMAP3430_AUTO_MCBSP4
|
840 OMAP3430_AUTO_MCBSP3
|
841 OMAP3430_AUTO_MCBSP2
,
845 if (omap_rev() > OMAP3430_REV_ES1_0
) {
847 OMAP3430ES2_AUTO_USBHOST
,
848 OMAP3430ES2_USBHOST_MOD
,
852 omap_ctrl_writel(OMAP3430_AUTOIDLE
, OMAP2_CONTROL_SYSCONFIG
);
855 * Set all plls to autoidle. This is needed until autoidle is
858 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT
,
859 OMAP3430_IVA2_MOD
, CM_AUTOIDLE2
);
860 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT
,
863 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT
) |
864 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT
),
867 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT
,
872 * Enable control of expternal oscillator through
873 * sys_clkreq. In the long run clock framework should
876 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK
,
877 1 << OMAP_AUTOEXTCLKMODE_SHIFT
,
879 OMAP3_PRM_CLKSRC_CTRL_OFFSET
);
881 /* setup wakup source */
882 prm_write_mod_reg(OMAP3430_EN_IO
| OMAP3430_EN_GPIO1
|
883 OMAP3430_EN_GPT1
| OMAP3430_EN_GPT12
,
885 /* No need to write EN_IO, that is always enabled */
886 prm_write_mod_reg(OMAP3430_EN_GPIO1
| OMAP3430_EN_GPT1
|
888 WKUP_MOD
, OMAP3430_PM_MPUGRPSEL
);
889 /* For some reason IO doesn't generate wakeup event even if
890 * it is selected to mpu wakeup goup */
891 prm_write_mod_reg(OMAP3430_IO_EN
| OMAP3430_WKUP_EN
,
892 OCP_MOD
, OMAP3_PRM_IRQENABLE_MPU_OFFSET
);
894 /* Enable PM_WKEN to support DSS LPR */
895 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS
,
896 OMAP3430_DSS_MOD
, PM_WKEN
);
898 /* Enable wakeups in PER */
899 prm_write_mod_reg(OMAP3430_EN_GPIO2
| OMAP3430_EN_GPIO3
|
900 OMAP3430_EN_GPIO4
| OMAP3430_EN_GPIO5
|
901 OMAP3430_EN_GPIO6
| OMAP3430_EN_UART3
|
902 OMAP3430_EN_MCBSP2
| OMAP3430_EN_MCBSP3
|
904 OMAP3430_PER_MOD
, PM_WKEN
);
905 /* and allow them to wake up MPU */
906 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2
| OMAP3430_EN_GPIO3
|
907 OMAP3430_GRPSEL_GPIO4
| OMAP3430_EN_GPIO5
|
908 OMAP3430_GRPSEL_GPIO6
| OMAP3430_EN_UART3
|
909 OMAP3430_EN_MCBSP2
| OMAP3430_EN_MCBSP3
|
911 OMAP3430_PER_MOD
, OMAP3430_PM_MPUGRPSEL
);
913 /* Don't attach IVA interrupts */
914 prm_write_mod_reg(0, WKUP_MOD
, OMAP3430_PM_IVAGRPSEL
);
915 prm_write_mod_reg(0, CORE_MOD
, OMAP3430_PM_IVAGRPSEL1
);
916 prm_write_mod_reg(0, CORE_MOD
, OMAP3430ES2_PM_IVAGRPSEL3
);
917 prm_write_mod_reg(0, OMAP3430_PER_MOD
, OMAP3430_PM_IVAGRPSEL
);
919 /* Clear any pending 'reset' flags */
920 prm_write_mod_reg(0xffffffff, MPU_MOD
, OMAP2_RM_RSTST
);
921 prm_write_mod_reg(0xffffffff, CORE_MOD
, OMAP2_RM_RSTST
);
922 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD
, OMAP2_RM_RSTST
);
923 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD
, OMAP2_RM_RSTST
);
924 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD
, OMAP2_RM_RSTST
);
925 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD
, OMAP2_RM_RSTST
);
926 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD
, OMAP2_RM_RSTST
);
928 /* Clear any pending PRCM interrupts */
929 prm_write_mod_reg(0, OCP_MOD
, OMAP3_PRM_IRQSTATUS_MPU_OFFSET
);
935 void omap3_pm_off_mode_enable(int enable
)
937 struct power_state
*pwrst
;
941 state
= PWRDM_POWER_OFF
;
943 state
= PWRDM_POWER_RET
;
945 #ifdef CONFIG_CPU_IDLE
946 omap3_cpuidle_update_states();
949 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
950 pwrst
->next_state
= state
;
951 set_pwrdm_state(pwrst
->pwrdm
, state
);
955 int omap3_pm_get_suspend_state(struct powerdomain
*pwrdm
)
957 struct power_state
*pwrst
;
959 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
960 if (pwrst
->pwrdm
== pwrdm
)
961 return pwrst
->next_state
;
966 int omap3_pm_set_suspend_state(struct powerdomain
*pwrdm
, int state
)
968 struct power_state
*pwrst
;
970 list_for_each_entry(pwrst
, &pwrst_list
, node
) {
971 if (pwrst
->pwrdm
== pwrdm
) {
972 pwrst
->next_state
= state
;
979 static int __init
pwrdms_setup(struct powerdomain
*pwrdm
, void *unused
)
981 struct power_state
*pwrst
;
986 pwrst
= kmalloc(sizeof(struct power_state
), GFP_ATOMIC
);
989 pwrst
->pwrdm
= pwrdm
;
990 pwrst
->next_state
= PWRDM_POWER_RET
;
991 list_add(&pwrst
->node
, &pwrst_list
);
993 if (pwrdm_has_hdwr_sar(pwrdm
))
994 pwrdm_enable_hdwr_sar(pwrdm
);
996 return set_pwrdm_state(pwrst
->pwrdm
, pwrst
->next_state
);
1000 * Enable hw supervised mode for all clockdomains if it's
1001 * supported. Initiate sleep transition for other clockdomains, if
1004 static int __init
clkdms_setup(struct clockdomain
*clkdm
, void *unused
)
1006 clkdm_clear_all_wkdeps(clkdm
);
1007 clkdm_clear_all_sleepdeps(clkdm
);
1009 if (clkdm
->flags
& CLKDM_CAN_ENABLE_AUTO
)
1010 omap2_clkdm_allow_idle(clkdm
);
1011 else if (clkdm
->flags
& CLKDM_CAN_FORCE_SLEEP
&&
1012 atomic_read(&clkdm
->usecount
) == 0)
1013 omap2_clkdm_sleep(clkdm
);
1017 void omap_push_sram_idle(void)
1019 _omap_sram_idle
= omap_sram_push(omap34xx_cpu_suspend
,
1020 omap34xx_cpu_suspend_sz
);
1021 if (omap_type() != OMAP2_DEVICE_TYPE_GP
)
1022 _omap_save_secure_sram
= omap_sram_push(save_secure_ram_context
,
1023 save_secure_ram_context_sz
);
1026 static int __init
omap3_pm_init(void)
1028 struct power_state
*pwrst
, *tmp
;
1029 struct clockdomain
*neon_clkdm
, *per_clkdm
, *mpu_clkdm
, *core_clkdm
;
1032 if (!cpu_is_omap34xx())
1035 printk(KERN_ERR
"Power Management for TI OMAP3.\n");
1037 /* XXX prcm_setup_regs needs to be before enabling hw
1038 * supervised mode for powerdomains */
1041 ret
= request_irq(INT_34XX_PRCM_MPU_IRQ
,
1042 (irq_handler_t
)prcm_interrupt_handler
,
1043 IRQF_DISABLED
, "prcm", NULL
);
1045 printk(KERN_ERR
"request_irq failed to register for 0x%x\n",
1046 INT_34XX_PRCM_MPU_IRQ
);
1050 ret
= pwrdm_for_each(pwrdms_setup
, NULL
);
1052 printk(KERN_ERR
"Failed to setup powerdomains\n");
1056 (void) clkdm_for_each(clkdms_setup
, NULL
);
1058 mpu_pwrdm
= pwrdm_lookup("mpu_pwrdm");
1059 if (mpu_pwrdm
== NULL
) {
1060 printk(KERN_ERR
"Failed to get mpu_pwrdm\n");
1064 neon_pwrdm
= pwrdm_lookup("neon_pwrdm");
1065 per_pwrdm
= pwrdm_lookup("per_pwrdm");
1066 core_pwrdm
= pwrdm_lookup("core_pwrdm");
1067 cam_pwrdm
= pwrdm_lookup("cam_pwrdm");
1069 neon_clkdm
= clkdm_lookup("neon_clkdm");
1070 mpu_clkdm
= clkdm_lookup("mpu_clkdm");
1071 per_clkdm
= clkdm_lookup("per_clkdm");
1072 core_clkdm
= clkdm_lookup("core_clkdm");
1074 omap_push_sram_idle();
1075 #ifdef CONFIG_SUSPEND
1076 suspend_set_ops(&omap_pm_ops
);
1077 #endif /* CONFIG_SUSPEND */
1079 pm_idle
= omap3_pm_idle
;
1082 clkdm_add_wkdep(neon_clkdm
, mpu_clkdm
);
1084 * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
1085 * IO-pad wakeup. Otherwise it will unnecessarily waste power
1086 * waking up PER with every CORE wakeup - see
1087 * http://marc.info/?l=linux-omap&m=121852150710062&w=2
1089 clkdm_add_wkdep(per_clkdm
, core_clkdm
);
1091 if (omap_type() != OMAP2_DEVICE_TYPE_GP
) {
1092 omap3_secure_ram_storage
=
1093 kmalloc(0x803F, GFP_KERNEL
);
1094 if (!omap3_secure_ram_storage
)
1095 printk(KERN_ERR
"Memory allocation failed when"
1096 "allocating for secure sram context\n");
1098 local_irq_disable();
1099 local_fiq_disable();
1101 omap_dma_global_context_save();
1102 omap3_save_secure_ram_context(PWRDM_POWER_ON
);
1103 omap_dma_global_context_restore();
1109 omap3_save_scratchpad_contents();
1113 free_irq(INT_34XX_PRCM_MPU_IRQ
, NULL
);
1114 list_for_each_entry_safe(pwrst
, tmp
, &pwrst_list
, node
) {
1115 list_del(&pwrst
->node
);
1121 late_initcall(omap3_pm_init
);