]>
git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - arch/arm/mach-omap2/prcm_mpu7xx.h
2 * DRA7xx PRCM MPU instance offset macros
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
22 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
23 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
25 #include "prcm_mpu_44xx_54xx.h"
27 #define DRA7XX_PRCM_MPU_BASE 0x48243000
29 #define DRA7XX_PRCM_MPU_REGADDR(inst, reg) \
30 OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))
32 /* MPU_PRCM instances */
33 #define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
35 #define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
36 #define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
37 #define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
38 #define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
40 /* PRCM_MPU clockdomain register offsets (from instance start) */
41 #define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
42 #define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
47 /* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */
48 #define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
50 /* MPU_PRCM.PRCM_MPU_DEVICE register offsets */
51 #define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010
52 #define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
54 /* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */
55 #define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
56 #define DRA7XX_PM_CPU0_PWRSTST_OFFSET 0x0004
57 #define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010
58 #define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014
59 #define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024
61 /* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */
62 #define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000
63 #define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020
64 #define DRA7XX_CM_CPU0_CPU0_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020)
66 /* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */
67 #define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
68 #define DRA7XX_PM_CPU1_PWRSTST_OFFSET 0x0004
69 #define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010
70 #define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014
71 #define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024
73 /* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */
74 #define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000
75 #define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020
76 #define DRA7XX_CM_CPU1_CPU1_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020)