arch/arm/mach-omap2/prm44xx.c

   1 /*
   2  * OMAP4 PRM module functions
   3  *
   4  * Copyright (C) 2011-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2010 Nokia Corporation
   6  * Benoît Cousson
   7  * Paul Walmsley
   8  * Rajendra Nayak <rnayak@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/delay.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of.h>
  22
  23 #include "soc.h"
  24 #include "iomap.h"
  25 #include "common.h"
  26 #include "vp.h"
  27 #include "prm44xx.h"
  28 #include "prcm43xx.h"
  29 #include "prm-regbits-44xx.h"
  30 #include "prcm44xx.h"
  31 #include "prminst44xx.h"
  32 #include "powerdomain.h"
  33
  34 /* Static data */
  35
  36 static void omap44xx_prm_read_pending_irqs(unsigned long *events);
  37 static void omap44xx_prm_ocp_barrier(void);
  38 static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
  39 static void omap44xx_prm_restore_irqen(u32 *saved_mask);
  40 static void omap44xx_prm_reconfigure_io_chain(void);
  41
  42 static const struct omap_prcm_irq omap4_prcm_irqs[] = {
  43         OMAP_PRCM_IRQ("io",     9,      1),
  44 };
  45
  46 static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
  47         .ack                    = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
  48         .mask                   = OMAP4_PRM_IRQENABLE_MPU_OFFSET,
  49         .pm_ctrl                = OMAP4_PRM_IO_PMCTRL_OFFSET,
  50         .nr_regs                = 2,
  51         .irqs                   = omap4_prcm_irqs,
  52         .nr_irqs                = ARRAY_SIZE(omap4_prcm_irqs),
  53         .irq                    = 11 + OMAP44XX_IRQ_GIC_START,
  54         .xlate_irq              = omap4_xlate_irq,
  55         .read_pending_irqs      = &omap44xx_prm_read_pending_irqs,
  56         .ocp_barrier            = &omap44xx_prm_ocp_barrier,
  57         .save_and_clear_irqen   = &omap44xx_prm_save_and_clear_irqen,
  58         .restore_irqen          = &omap44xx_prm_restore_irqen,
  59         .reconfigure_io_chain   = &omap44xx_prm_reconfigure_io_chain,
  60 };
  61
  62 /*
  63  * omap44xx_prm_reset_src_map - map from bits in the PRM_RSTST
  64  *   hardware register (which are specific to OMAP44xx SoCs) to reset
  65  *   source ID bit shifts (which is an OMAP SoC-independent
  66  *   enumeration)
  67  */
  68 static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
  69         { OMAP4430_GLOBAL_WARM_SW_RST_SHIFT,
  70           OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
  71         { OMAP4430_GLOBAL_COLD_RST_SHIFT,
  72           OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
  73         { OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT,
  74           OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
  75         { OMAP4430_MPU_WDT_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
  76         { OMAP4430_SECURE_WDT_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
  77         { OMAP4430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
  78         { OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT,
  79           OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT },
  80         { OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT,
  81           OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT },
  82         { OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT,
  83           OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT },
  84         { OMAP4430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT },
  85         { OMAP4430_C2C_RST_SHIFT, OMAP_C2C_RST_SRC_ID_SHIFT },
  86         { -1, -1 },
  87 };
  88
  89 /* PRM low-level functions */
  90
  91 /* Read a register in a CM/PRM instance in the PRM module */
  92 static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
  93 {
  94         return readl_relaxed(prm_base.va + inst + reg);
  95 }
  96
  97 /* Write into a register in a CM/PRM instance in the PRM module */
  98 static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
  99 {
 100         writel_relaxed(val, prm_base.va + inst + reg);
 101 }
 102
 103 /* Read-modify-write a register in a PRM module. Caller must lock */
 104 static u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
 105 {
 106         u32 v;
 107
 108         v = omap4_prm_read_inst_reg(inst, reg);
 109         v &= ~mask;
 110         v |= bits;
 111         omap4_prm_write_inst_reg(v, inst, reg);
 112
 113         return v;
 114 }
 115
 116 /* PRM VP */
 117
 118 /*
 119  * struct omap4_vp - OMAP4 VP register access description.
 120  * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
 121  * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
 122  */
 123 struct omap4_vp {
 124         u32 irqstatus_mpu;
 125         u32 tranxdone_status;
 126 };
 127
 128 static struct omap4_vp omap4_vp[] = {
 129         [OMAP4_VP_VDD_MPU_ID] = {
 130                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
 131                 .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
 132         },
 133         [OMAP4_VP_VDD_IVA_ID] = {
 134                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
 135                 .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
 136         },
 137         [OMAP4_VP_VDD_CORE_ID] = {
 138                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
 139                 .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
 140         },
 141 };
 142
 143 static u32 omap4_prm_vp_check_txdone(u8 vp_id)
 144 {
 145         struct omap4_vp *vp = &omap4_vp[vp_id];
 146         u32 irqstatus;
 147
 148         irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 149                                                 OMAP4430_PRM_OCP_SOCKET_INST,
 150                                                 vp->irqstatus_mpu);
 151         return irqstatus & vp->tranxdone_status;
 152 }
 153
 154 static void omap4_prm_vp_clear_txdone(u8 vp_id)
 155 {
 156         struct omap4_vp *vp = &omap4_vp[vp_id];
 157
 158         omap4_prminst_write_inst_reg(vp->tranxdone_status,
 159                                      OMAP4430_PRM_PARTITION,
 160                                      OMAP4430_PRM_OCP_SOCKET_INST,
 161                                      vp->irqstatus_mpu);
 162 };
 163
 164 u32 omap4_prm_vcvp_read(u8 offset)
 165 {
 166         s32 inst = omap4_prmst_get_prm_dev_inst();
 167
 168         if (inst == PRM_INSTANCE_UNKNOWN)
 169                 return 0;
 170
 171         return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 172                                            inst, offset);
 173 }
 174
 175 void omap4_prm_vcvp_write(u32 val, u8 offset)
 176 {
 177         s32 inst = omap4_prmst_get_prm_dev_inst();
 178
 179         if (inst == PRM_INSTANCE_UNKNOWN)
 180                 return;
 181
 182         omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
 183                                      inst, offset);
 184 }
 185
 186 u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
 187 {
 188         s32 inst = omap4_prmst_get_prm_dev_inst();
 189
 190         if (inst == PRM_INSTANCE_UNKNOWN)
 191                 return 0;
 192
 193         return omap4_prminst_rmw_inst_reg_bits(mask, bits,
 194                                                OMAP4430_PRM_PARTITION,
 195                                                inst,
 196                                                offset);
 197 }
 198
 199 static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
 200 {
 201         u32 mask, st;
 202
 203         /* XXX read mask from RAM? */
 204         mask = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 205                                        irqen_offs);
 206         st = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, irqst_offs);
 207
 208         return mask & st;
 209 }
 210
 211 /**
 212  * omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
 213  * @events: ptr to two consecutive u32s, preallocated by caller
 214  *
 215  * Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM
 216  * MPU IRQs, and store the result into the two u32s pointed to by @events.
 217  * No return value.
 218  */
 219 static void omap44xx_prm_read_pending_irqs(unsigned long *events)
 220 {
 221         int i;
 222
 223         for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++)
 224                 events[i] = _read_pending_irq_reg(omap4_prcm_irq_setup.mask +
 225                                 i * 4, omap4_prcm_irq_setup.ack + i * 4);
 226 }
 227
 228 /**
 229  * omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
 230  *
 231  * Force any buffered writes to the PRM IP block to complete.  Needed
 232  * by the PRM IRQ handler, which reads and writes directly to the IP
 233  * block, to avoid race conditions after acknowledging or clearing IRQ
 234  * bits.  No return value.
 235  */
 236 static void omap44xx_prm_ocp_barrier(void)
 237 {
 238         omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 239                                 OMAP4_REVISION_PRM_OFFSET);
 240 }
 241
 242 /**
 243  * omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs
 244  * @saved_mask: ptr to a u32 array to save IRQENABLE bits
 245  *
 246  * Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to
 247  * @saved_mask.  @saved_mask must be allocated by the caller.
 248  * Intended to be used in the PRM interrupt handler suspend callback.
 249  * The OCP barrier is needed to ensure the write to disable PRM
 250  * interrupts reaches the PRM before returning; otherwise, spurious
 251  * interrupts might occur.  No return value.
 252  */
 253 static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
 254 {
 255         int i;
 256         u16 reg;
 257
 258         for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++) {
 259                 reg = omap4_prcm_irq_setup.mask + i * 4;
 260
 261                 saved_mask[i] =
 262                         omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 263                                                 reg);
 264                 omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, reg);
 265         }
 266
 267         /* OCP barrier */
 268         omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 269                                 OMAP4_REVISION_PRM_OFFSET);
 270 }
 271
 272 /**
 273  * omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args
 274  * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
 275  *
 276  * Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from
 277  * @saved_mask.  Intended to be used in the PRM interrupt handler resume
 278  * callback to restore values saved by omap44xx_prm_save_and_clear_irqen().
 279  * No OCP barrier should be needed here; any pending PRM interrupts will fire
 280  * once the writes reach the PRM.  No return value.
 281  */
 282 static void omap44xx_prm_restore_irqen(u32 *saved_mask)
 283 {
 284         int i;
 285
 286         for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++)
 287                 omap4_prm_write_inst_reg(saved_mask[i],
 288                                          OMAP4430_PRM_OCP_SOCKET_INST,
 289                                          omap4_prcm_irq_setup.mask + i * 4);
 290 }
 291
 292 /**
 293  * omap44xx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
 294  *
 295  * Clear any previously-latched I/O wakeup events and ensure that the
 296  * I/O wakeup gates are aligned with the current mux settings.  Works
 297  * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
 298  * deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted.
 299  * No return value. XXX Are the final two steps necessary?
 300  */
 301 static void omap44xx_prm_reconfigure_io_chain(void)
 302 {
 303         int i = 0;
 304         s32 inst = omap4_prmst_get_prm_dev_inst();
 305
 306         if (inst == PRM_INSTANCE_UNKNOWN)
 307                 return;
 308
 309         /* Trigger WUCLKIN enable */
 310         omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
 311                                     OMAP4430_WUCLK_CTRL_MASK,
 312                                     inst,
 313                                     omap4_prcm_irq_setup.pm_ctrl);
 314         omap_test_timeout(
 315                 (((omap4_prm_read_inst_reg(inst,
 316                                            omap4_prcm_irq_setup.pm_ctrl) &
 317                    OMAP4430_WUCLK_STATUS_MASK) >>
 318                   OMAP4430_WUCLK_STATUS_SHIFT) == 1),
 319                 MAX_IOPAD_LATCH_TIME, i);
 320         if (i == MAX_IOPAD_LATCH_TIME)
 321                 pr_warn("PRM: I/O chain clock line assertion timed out\n");
 322
 323         /* Trigger WUCLKIN disable */
 324         omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
 325                                     inst,
 326                                     omap4_prcm_irq_setup.pm_ctrl);
 327         omap_test_timeout(
 328                 (((omap4_prm_read_inst_reg(inst,
 329                                            omap4_prcm_irq_setup.pm_ctrl) &
 330                    OMAP4430_WUCLK_STATUS_MASK) >>
 331                   OMAP4430_WUCLK_STATUS_SHIFT) == 0),
 332                 MAX_IOPAD_LATCH_TIME, i);
 333         if (i == MAX_IOPAD_LATCH_TIME)
 334                 pr_warn("PRM: I/O chain clock line deassertion timed out\n");
 335
 336         return;
 337 }
 338
 339 /**
 340  * omap44xx_prm_read_reset_sources - return the last SoC reset source
 341  *
 342  * Return a u32 representing the last reset sources of the SoC.  The
 343  * returned reset source bits are standardized across OMAP SoCs.
 344  */
 345 static u32 omap44xx_prm_read_reset_sources(void)
 346 {
 347         struct prm_reset_src_map *p;
 348         u32 r = 0;
 349         u32 v;
 350         s32 inst = omap4_prmst_get_prm_dev_inst();
 351
 352         if (inst == PRM_INSTANCE_UNKNOWN)
 353                 return 0;
 354
 355
 356         v = omap4_prm_read_inst_reg(inst,
 357                                     OMAP4_RM_RSTST);
 358
 359         p = omap44xx_prm_reset_src_map;
 360         while (p->reg_shift >= 0 && p->std_shift >= 0) {
 361                 if (v & (1 << p->reg_shift))
 362                         r |= 1 << p->std_shift;
 363                 p++;
 364         }
 365
 366         return r;
 367 }
 368
 369 /**
 370  * omap44xx_prm_was_any_context_lost_old - was module hardware context lost?
 371  * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
 372  * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
 373  * @idx: CONTEXT register offset
 374  *
 375  * Return 1 if any bits were set in the *_CONTEXT_* register
 376  * identified by (@part, @inst, @idx), which means that some context
 377  * was lost for that module; otherwise, return 0.
 378  */
 379 static bool omap44xx_prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
 380 {
 381         return (omap4_prminst_read_inst_reg(part, inst, idx)) ? 1 : 0;
 382 }
 383
 384 /**
 385  * omap44xx_prm_clear_context_lost_flags_old - clear context loss flags
 386  * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
 387  * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
 388  * @idx: CONTEXT register offset
 389  *
 390  * Clear hardware context loss bits for the module identified by
 391  * (@part, @inst, @idx).  No return value.  XXX Writes to reserved bits;
 392  * is there a way to avoid this?
 393  */
 394 static void omap44xx_prm_clear_context_loss_flags_old(u8 part, s16 inst,
 395                                                       u16 idx)
 396 {
 397         omap4_prminst_write_inst_reg(0xffffffff, part, inst, idx);
 398 }
 399
 400 /* Powerdomain low-level functions */
 401
 402 static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
 403 {
 404         omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
 405                                         (pwrst << OMAP_POWERSTATE_SHIFT),
 406                                         pwrdm->prcm_partition,
 407                                         pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
 408         return 0;
 409 }
 410
 411 static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
 412 {
 413         u32 v;
 414
 415         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 416                                         OMAP4_PM_PWSTCTRL);
 417         v &= OMAP_POWERSTATE_MASK;
 418         v >>= OMAP_POWERSTATE_SHIFT;
 419
 420         return v;
 421 }
 422
 423 static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
 424 {
 425         u32 v;
 426
 427         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 428                                         OMAP4_PM_PWSTST);
 429         v &= OMAP_POWERSTATEST_MASK;
 430         v >>= OMAP_POWERSTATEST_SHIFT;
 431
 432         return v;
 433 }
 434
 435 static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
 436 {
 437         u32 v;
 438
 439         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 440                                         OMAP4_PM_PWSTST);
 441         v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
 442         v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
 443
 444         return v;
 445 }
 446
 447 static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
 448 {
 449         omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
 450                                         (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
 451                                         pwrdm->prcm_partition,
 452                                         pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
 453         return 0;
 454 }
 455
 456 static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
 457 {
 458         omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
 459                                         OMAP4430_LASTPOWERSTATEENTERED_MASK,
 460                                         pwrdm->prcm_partition,
 461                                         pwrdm->prcm_offs, OMAP4_PM_PWSTST);
 462         return 0;
 463 }
 464
 465 static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
 466 {
 467         u32 v;
 468
 469         v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
 470         omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
 471                                         pwrdm->prcm_partition, pwrdm->prcm_offs,
 472                                         OMAP4_PM_PWSTCTRL);
 473
 474         return 0;
 475 }
 476
 477 static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
 478                                     u8 pwrst)
 479 {
 480         u32 m;
 481
 482         m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
 483
 484         omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
 485                                         pwrdm->prcm_partition, pwrdm->prcm_offs,
 486                                         OMAP4_PM_PWSTCTRL);
 487
 488         return 0;
 489 }
 490
 491 static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
 492                                      u8 pwrst)
 493 {
 494         u32 m;
 495
 496         m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
 497
 498         omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
 499                                         pwrdm->prcm_partition, pwrdm->prcm_offs,
 500                                         OMAP4_PM_PWSTCTRL);
 501
 502         return 0;
 503 }
 504
 505 static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
 506 {
 507         u32 v;
 508
 509         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 510                                         OMAP4_PM_PWSTST);
 511         v &= OMAP4430_LOGICSTATEST_MASK;
 512         v >>= OMAP4430_LOGICSTATEST_SHIFT;
 513
 514         return v;
 515 }
 516
 517 static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
 518 {
 519         u32 v;
 520
 521         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 522                                         OMAP4_PM_PWSTCTRL);
 523         v &= OMAP4430_LOGICRETSTATE_MASK;
 524         v >>= OMAP4430_LOGICRETSTATE_SHIFT;
 525
 526         return v;
 527 }
 528
 529 /**
 530  * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
 531  * @pwrdm: struct powerdomain * to read the state for
 532  *
 533  * Reads the previous logic powerstate for a powerdomain. This
 534  * function must determine the previous logic powerstate by first
 535  * checking the previous powerstate for the domain. If that was OFF,
 536  * then logic has been lost. If previous state was RETENTION, the
 537  * function reads the setting for the next retention logic state to
 538  * see the actual value.  In every other case, the logic is
 539  * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
 540  * depending whether the logic was retained or not.
 541  */
 542 static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
 543 {
 544         int state;
 545
 546         state = omap4_pwrdm_read_prev_pwrst(pwrdm);
 547
 548         if (state == PWRDM_POWER_OFF)
 549                 return PWRDM_POWER_OFF;
 550
 551         if (state != PWRDM_POWER_RET)
 552                 return PWRDM_POWER_RET;
 553
 554         return omap4_pwrdm_read_logic_retst(pwrdm);
 555 }
 556
 557 static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 558 {
 559         u32 m, v;
 560
 561         m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
 562
 563         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 564                                         OMAP4_PM_PWSTST);
 565         v &= m;
 566         v >>= __ffs(m);
 567
 568         return v;
 569 }
 570
 571 static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
 572 {
 573         u32 m, v;
 574
 575         m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
 576
 577         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 578                                         OMAP4_PM_PWSTCTRL);
 579         v &= m;
 580         v >>= __ffs(m);
 581
 582         return v;
 583 }
 584
 585 /**
 586  * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
 587  * @pwrdm: struct powerdomain * to read mem powerstate for
 588  * @bank: memory bank index
 589  *
 590  * Reads the previous memory powerstate for a powerdomain. This
 591  * function must determine the previous memory powerstate by first
 592  * checking the previous powerstate for the domain. If that was OFF,
 593  * then logic has been lost. If previous state was RETENTION, the
 594  * function reads the setting for the next memory retention state to
 595  * see the actual value.  In every other case, the logic is
 596  * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
 597  * depending whether logic was retained or not.
 598  */
 599 static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 600 {
 601         int state;
 602
 603         state = omap4_pwrdm_read_prev_pwrst(pwrdm);
 604
 605         if (state == PWRDM_POWER_OFF)
 606                 return PWRDM_POWER_OFF;
 607
 608         if (state != PWRDM_POWER_RET)
 609                 return PWRDM_POWER_RET;
 610
 611         return omap4_pwrdm_read_mem_retst(pwrdm, bank);
 612 }
 613
 614 static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
 615 {
 616         u32 c = 0;
 617
 618         /*
 619          * REVISIT: pwrdm_wait_transition() may be better implemented
 620          * via a callback and a periodic timer check -- how long do we expect
 621          * powerdomain transitions to take?
 622          */
 623
 624         /* XXX Is this udelay() value meaningful? */
 625         while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
 626                                             pwrdm->prcm_offs,
 627                                             OMAP4_PM_PWSTST) &
 628                 OMAP_INTRANSITION_MASK) &&
 629                (c++ < PWRDM_TRANSITION_BAILOUT))
 630                 udelay(1);
 631
 632         if (c > PWRDM_TRANSITION_BAILOUT) {
 633                 pr_err("powerdomain: %s: waited too long to complete transition\n",
 634                        pwrdm->name);
 635                 return -EAGAIN;
 636         }
 637
 638         pr_debug("powerdomain: completed transition in %d loops\n", c);
 639
 640         return 0;
 641 }
 642
 643 static int omap4_check_vcvp(void)
 644 {
 645         if (prm_features & PRM_HAS_VOLTAGE)
 646                 return 1;
 647
 648         return 0;
 649 }
 650
 651 struct pwrdm_ops omap4_pwrdm_operations = {
 652         .pwrdm_set_next_pwrst   = omap4_pwrdm_set_next_pwrst,
 653         .pwrdm_read_next_pwrst  = omap4_pwrdm_read_next_pwrst,
 654         .pwrdm_read_pwrst       = omap4_pwrdm_read_pwrst,
 655         .pwrdm_read_prev_pwrst  = omap4_pwrdm_read_prev_pwrst,
 656         .pwrdm_set_lowpwrstchange       = omap4_pwrdm_set_lowpwrstchange,
 657         .pwrdm_clear_all_prev_pwrst     = omap4_pwrdm_clear_all_prev_pwrst,
 658         .pwrdm_set_logic_retst  = omap4_pwrdm_set_logic_retst,
 659         .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
 660         .pwrdm_read_prev_logic_pwrst    = omap4_pwrdm_read_prev_logic_pwrst,
 661         .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
 662         .pwrdm_read_mem_pwrst   = omap4_pwrdm_read_mem_pwrst,
 663         .pwrdm_read_mem_retst   = omap4_pwrdm_read_mem_retst,
 664         .pwrdm_read_prev_mem_pwrst      = omap4_pwrdm_read_prev_mem_pwrst,
 665         .pwrdm_set_mem_onst     = omap4_pwrdm_set_mem_onst,
 666         .pwrdm_set_mem_retst    = omap4_pwrdm_set_mem_retst,
 667         .pwrdm_wait_transition  = omap4_pwrdm_wait_transition,
 668         .pwrdm_has_voltdm       = omap4_check_vcvp,
 669 };
 670
 671 /*
 672  * XXX document
 673  */
 674 static struct prm_ll_data omap44xx_prm_ll_data = {
 675         .read_reset_sources = &omap44xx_prm_read_reset_sources,
 676         .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
 677         .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
 678         .assert_hardreset       = omap4_prminst_assert_hardreset,
 679         .deassert_hardreset     = omap4_prminst_deassert_hardreset,
 680         .is_hardreset_asserted  = omap4_prminst_is_hardreset_asserted,
 681         .reset_system           = omap4_prminst_global_warm_sw_reset,
 682         .vp_check_txdone        = omap4_prm_vp_check_txdone,
 683         .vp_clear_txdone        = omap4_prm_vp_clear_txdone,
 684 };
 685
 686 static const struct omap_prcm_init_data *prm_init_data;
 687
 688 int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
 689 {
 690         omap_prm_base_init();
 691
 692         prm_init_data = data;
 693
 694         if (data->flags & PRM_HAS_IO_WAKEUP)
 695                 prm_features |= PRM_HAS_IO_WAKEUP;
 696
 697         if (data->flags & PRM_HAS_VOLTAGE)
 698                 prm_features |= PRM_HAS_VOLTAGE;
 699
 700         omap4_prminst_set_prm_dev_inst(data->device_inst_offset);
 701
 702         /* Add AM437X specific differences */
 703         if (of_device_is_compatible(data->np, "ti,am4-prcm")) {
 704                 omap4_prcm_irq_setup.nr_irqs = 1;
 705                 omap4_prcm_irq_setup.nr_regs = 1;
 706                 omap4_prcm_irq_setup.pm_ctrl = AM43XX_PRM_IO_PMCTRL_OFFSET;
 707                 omap4_prcm_irq_setup.ack = AM43XX_PRM_IRQSTATUS_MPU_OFFSET;
 708                 omap4_prcm_irq_setup.mask = AM43XX_PRM_IRQENABLE_MPU_OFFSET;
 709         }
 710
 711         return prm_register(&omap44xx_prm_ll_data);
 712 }
 713
 714 static void __exit omap44xx_prm_exit(void)
 715 {
 716         prm_unregister(&omap44xx_prm_ll_data);
 717 }
 718 __exitcall(omap44xx_prm_exit);