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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - arch/arm/mach-omap2/prm54xx.h
2 * OMAP54xx PRM instance offset macros
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
6 * Paul Walmsley (paul@pwsan.com)
7 * Rajendra Nayak (rnayak@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #ifndef __ARCH_ARM_MACH_OMAP2_PRM54XX_H
22 #define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
24 #include "prm44xx_54xx.h"
25 #include "prcm-common.h"
28 #define OMAP54XX_PRM_BASE 0x4ae06000
30 #define OMAP54XX_PRM_REGADDR(inst, reg) \
31 OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg))
35 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP54XX_PRM_CKGEN_INST 0x0100
37 #define OMAP54XX_PRM_MPU_INST 0x0300
38 #define OMAP54XX_PRM_DSP_INST 0x0400
39 #define OMAP54XX_PRM_ABE_INST 0x0500
40 #define OMAP54XX_PRM_COREAON_INST 0x0600
41 #define OMAP54XX_PRM_CORE_INST 0x0700
42 #define OMAP54XX_PRM_IVA_INST 0x1200
43 #define OMAP54XX_PRM_CAM_INST 0x1300
44 #define OMAP54XX_PRM_DSS_INST 0x1400
45 #define OMAP54XX_PRM_GPU_INST 0x1500
46 #define OMAP54XX_PRM_L3INIT_INST 0x1600
47 #define OMAP54XX_PRM_CUSTEFUSE_INST 0x1700
48 #define OMAP54XX_PRM_WKUPAON_INST 0x1800
49 #define OMAP54XX_PRM_WKUPAON_CM_INST 0x1900
50 #define OMAP54XX_PRM_EMU_INST 0x1a00
51 #define OMAP54XX_PRM_EMU_CM_INST 0x1b00
52 #define OMAP54XX_PRM_DEVICE_INST 0x1c00
53 #define OMAP54XX_PRM_INSTR_INST 0x1f00
55 /* PRM clockdomain register offsets (from instance start) */
56 #define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000
57 #define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS 0x0000
61 /* PRM.OCP_SOCKET_PRM register offsets */
62 #define OMAP54XX_REVISION_PRM_OFFSET 0x0000
63 #define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010
64 #define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
65 #define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET 0x0018
66 #define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c
67 #define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET 0x0020
68 #define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET 0x0028
69 #define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET 0x0030
70 #define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET 0x0038
71 #define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
72 #define OMAP54XX_CM_PRM_PROFILING_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040)
73 #define OMAP54XX_PRM_DEBUG_OUT_OFFSET 0x0084
74 #define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET 0x0090
75 #define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET 0x0094
76 #define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET 0x0098
77 #define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET 0x009c
78 #define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET 0x00a0
79 #define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET 0x00a4
81 /* PRM.CKGEN_PRM register offsets */
82 #define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET 0x0000
83 #define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000)
84 #define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008
85 #define OMAP54XX_CM_CLKSEL_WKUPAON OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008)
86 #define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c
87 #define OMAP54XX_CM_CLKSEL_ABE_PLL_REF OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c)
88 #define OMAP54XX_CM_CLKSEL_SYS_OFFSET 0x0010
89 #define OMAP54XX_CM_CLKSEL_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010)
91 /* PRM.MPU_PRM register offsets */
92 #define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
93 #define OMAP54XX_PM_MPU_PWRSTST_OFFSET 0x0004
94 #define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
96 /* PRM.DSP_PRM register offsets */
97 #define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET 0x0000
98 #define OMAP54XX_PM_DSP_PWRSTST_OFFSET 0x0004
99 #define OMAP54XX_RM_DSP_RSTCTRL_OFFSET 0x0010
100 #define OMAP54XX_RM_DSP_RSTST_OFFSET 0x0014
101 #define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET 0x0024
103 /* PRM.ABE_PRM register offsets */
104 #define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET 0x0000
105 #define OMAP54XX_PM_ABE_PWRSTST_OFFSET 0x0004
106 #define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET 0x002c
107 #define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET 0x0030
108 #define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET 0x0034
109 #define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET 0x0038
110 #define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c
111 #define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET 0x0040
112 #define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044
113 #define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048
114 #define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c
115 #define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050
116 #define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054
117 #define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058
118 #define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c
119 #define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET 0x0060
120 #define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET 0x0064
121 #define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068
122 #define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c
123 #define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070
124 #define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074
125 #define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078
126 #define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c
127 #define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080
128 #define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084
129 #define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET 0x0088
130 #define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET 0x008c
132 /* PRM.COREAON_PRM register offsets */
133 #define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0028
134 #define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x002c
135 #define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET 0x0030
136 #define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET 0x0034
137 #define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0038
138 #define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x003c
140 /* PRM.CORE_PRM register offsets */
141 #define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000
142 #define OMAP54XX_PM_CORE_PWRSTST_OFFSET 0x0004
143 #define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024
144 #define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET 0x0124
145 #define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET 0x012c
146 #define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET 0x0134
147 #define OMAP54XX_RM_IPU_RSTCTRL_OFFSET 0x0210
148 #define OMAP54XX_RM_IPU_RSTST_OFFSET 0x0214
149 #define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET 0x0224
150 #define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324
151 #define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424
152 #define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c
153 #define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434
154 #define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c
155 #define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444
156 #define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET 0x0524
157 #define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET 0x052c
158 #define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET 0x0534
159 #define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
160 #define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c
161 #define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634
162 #define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c
163 #define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644
164 #define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET 0x0724
165 #define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c
166 #define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744
167 #define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET 0x0824
168 #define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET 0x082c
169 #define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET 0x0834
170 #define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0928
171 #define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x092c
172 #define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0930
173 #define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0934
174 #define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0938
175 #define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x093c
176 #define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0940
177 #define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0944
178 #define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0948
179 #define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x094c
180 #define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0950
181 #define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0954
182 #define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x095c
183 #define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0960
184 #define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0964
185 #define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0968
186 #define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x096c
187 #define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0970
188 #define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0974
189 #define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0978
190 #define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x097c
191 #define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0980
192 #define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0984
193 #define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x098c
194 #define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x09a0
195 #define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x09a4
196 #define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x09a8
197 #define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x09ac
198 #define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x09b0
199 #define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x09b4
200 #define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x09b8
201 #define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x09bc
202 #define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x09c0
203 #define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x09f0
204 #define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x09f4
205 #define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x09f8
206 #define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x09fc
207 #define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0a00
208 #define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0a04
209 #define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0a08
210 #define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x0a0c
211 #define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0a10
212 #define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0a14
213 #define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0a18
214 #define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x0a1c
215 #define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0a20
216 #define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0a24
217 #define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0a28
218 #define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x0a2c
219 #define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0a40
220 #define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0a44
221 #define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0a48
222 #define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x0a4c
223 #define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0a50
224 #define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0a54
225 #define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x0a58
226 #define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0a5c
227 #define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET 0x0a60
228 #define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET 0x0a64
229 #define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET 0x0a68
230 #define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET 0x0a6c
231 #define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0a70
232 #define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0a74
233 #define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET 0x0a78
234 #define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET 0x0a7c
235 #define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x0aa4
236 #define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x0aac
237 #define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x0ab4
238 #define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x0abc
239 #define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x0ac4
240 #define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET 0x0acc
241 #define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x0adc
243 /* PRM.IVA_PRM register offsets */
244 #define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000
245 #define OMAP54XX_PM_IVA_PWRSTST_OFFSET 0x0004
246 #define OMAP54XX_RM_IVA_RSTCTRL_OFFSET 0x0010
247 #define OMAP54XX_RM_IVA_RSTST_OFFSET 0x0014
248 #define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024
249 #define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c
251 /* PRM.CAM_PRM register offsets */
252 #define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000
253 #define OMAP54XX_PM_CAM_PWRSTST_OFFSET 0x0004
254 #define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET 0x0024
255 #define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c
256 #define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET 0x0034
258 /* PRM.DSS_PRM register offsets */
259 #define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000
260 #define OMAP54XX_PM_DSS_PWRSTST_OFFSET 0x0004
261 #define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020
262 #define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024
263 #define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034
265 /* PRM.GPU_PRM register offsets */
266 #define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000
267 #define OMAP54XX_PM_GPU_PWRSTST_OFFSET 0x0004
268 #define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024
270 /* PRM.L3INIT_PRM register offsets */
271 #define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
272 #define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET 0x0004
273 #define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
274 #define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
275 #define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
276 #define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034
277 #define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038
278 #define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c
279 #define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET 0x0040
280 #define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET 0x0044
281 #define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET 0x0058
282 #define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET 0x005c
283 #define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET 0x0068
284 #define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET 0x006c
285 #define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
286 #define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
287 #define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
288 #define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
289 #define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec
290 #define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET 0x00f0
291 #define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET 0x00f4
293 /* PRM.CUSTEFUSE_PRM register offsets */
294 #define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000
295 #define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004
296 #define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024
298 /* PRM.WKUPAON_PRM register offsets */
299 #define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0024
300 #define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x002c
301 #define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x0030
302 #define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0034
303 #define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0038
304 #define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x003c
305 #define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x0040
306 #define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0044
307 #define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0048
308 #define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x004c
309 #define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0054
310 #define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0064
311 #define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0078
312 #define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x007c
314 /* PRM.WKUPAON_CM register offsets */
315 #define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000
316 #define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020
317 #define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020)
318 #define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028
319 #define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028)
320 #define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030
321 #define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030)
322 #define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038
323 #define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038)
324 #define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040
325 #define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040)
326 #define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048
327 #define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048)
328 #define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050
329 #define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050)
330 #define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060
331 #define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060)
332 #define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078
333 #define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078)
334 #define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090
335 #define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090)
336 #define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098
337 #define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098)
339 /* PRM.EMU_PRM register offsets */
340 #define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000
341 #define OMAP54XX_PM_EMU_PWRSTST_OFFSET 0x0004
342 #define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024
344 /* PRM.EMU_CM register offsets */
345 #define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000
346 #define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008
347 #define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020
348 #define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020)
349 #define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x0028
350 #define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028)
352 /* PRM.DEVICE_PRM register offsets */
353 #define OMAP54XX_PRM_RSTCTRL_OFFSET 0x0000
354 #define OMAP54XX_PRM_RSTST_OFFSET 0x0004
355 #define OMAP54XX_PRM_RSTTIME_OFFSET 0x0008
356 #define OMAP54XX_PRM_CLKREQCTRL_OFFSET 0x000c
357 #define OMAP54XX_PRM_VOLTCTRL_OFFSET 0x0010
358 #define OMAP54XX_PRM_PWRREQCTRL_OFFSET 0x0014
359 #define OMAP54XX_PRM_PSCON_COUNT_OFFSET 0x0018
360 #define OMAP54XX_PRM_IO_COUNT_OFFSET 0x001c
361 #define OMAP54XX_PRM_IO_PMCTRL_OFFSET 0x0020
362 #define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024
363 #define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
364 #define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
365 #define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030
366 #define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
367 #define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
368 #define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c
369 #define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET 0x0040
370 #define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET 0x0044
371 #define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048
372 #define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c
373 #define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050
374 #define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054
375 #define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET 0x0058
376 #define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET 0x005c
377 #define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060
378 #define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064
379 #define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068
380 #define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c
381 #define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET 0x0070
382 #define OMAP54XX_PRM_VP_MM_STATUS_OFFSET 0x0074
383 #define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET 0x0078
384 #define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET 0x007c
385 #define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET 0x0080
386 #define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET 0x0084
387 #define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET 0x0088
388 #define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET 0x008c
389 #define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET 0x0090
390 #define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094
391 #define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET 0x0098
392 #define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x009c
393 #define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET 0x00a0
394 #define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET 0x00a4
395 #define OMAP54XX_PRM_VC_MM_ERRST_OFFSET 0x00a8
396 #define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET 0x00ac
397 #define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET 0x00b0
398 #define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET 0x00b4
399 #define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET 0x00b8
400 #define OMAP54XX_PRM_SRAM_COUNT_OFFSET 0x00bc
401 #define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0
402 #define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4
403 #define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8
404 #define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc
405 #define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0
406 #define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET 0x00d4
407 #define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET 0x00d8
408 #define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc
409 #define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0
410 #define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET 0x00e4
411 #define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET 0x00e8
412 #define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec
413 #define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0
414 #define OMAP54XX_PRM_PHASE1_CNDP_OFFSET 0x00f4
415 #define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8
416 #define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc
417 #define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100
418 #define OMAP54XX_PRM_VOLTST_MPU_OFFSET 0x0110
419 #define OMAP54XX_PRM_VOLTST_MM_OFFSET 0x0114