arch/arm/mach-omap2/sdrc.c

   1 /*
   2  * SMS/SDRC (SDRAM controller) common code for OMAP2/3
   3  *
   4  * Copyright (C) 2005, 2008 Texas Instruments Inc.
   5  * Copyright (C) 2005, 2008 Nokia Corporation
   6  *
   7  * Tony Lindgren <tony@atomide.com>
   8  * Paul Walmsley
   9  * Richard Woodruff <r-woodruff2@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #undef DEBUG
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/device.h>
  20 #include <linux/list.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25
  26 #include <mach/common.h>
  27 #include <mach/clock.h>
  28 #include <mach/sram.h>
  29
  30 #include "prm.h"
  31
  32 #include <mach/sdrc.h>
  33 #include "sdrc.h"
  34
  35 static struct omap_sdrc_params *sdrc_init_params;
  36
  37 void __iomem *omap2_sdrc_base;
  38 void __iomem *omap2_sms_base;
  39
  40 /* SDRC_POWER register bits */
  41 #define SDRC_POWER_EXTCLKDIS_SHIFT              3
  42 #define SDRC_POWER_PWDENA_SHIFT                 2
  43 #define SDRC_POWER_PAGEPOLICY_SHIFT             0
  44
  45 /**
  46  * omap2_sdrc_get_params - return SDRC register values for a given clock rate
  47  * @r: SDRC clock rate (in Hz)
  48  *
  49  * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
  50  * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
  51  * SDRC clock rate 'r'.  These parameters control various timing
  52  * delays in the SDRAM controller that are expressed in terms of the
  53  * number of SDRC clock cycles to wait; hence the clock rate
  54  * dependency. Note that sdrc_init_params must be sorted rate
  55  * descending.  Also assumes that both chip-selects use the same
  56  * timing parameters.  Returns a struct omap_sdrc_params * upon
  57  * success, or NULL upon failure.
  58  */
  59 struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
  60 {
  61         struct omap_sdrc_params *sp;
  62
  63         if (!sdrc_init_params)
  64                 return NULL;
  65
  66         sp = sdrc_init_params;
  67
  68         while (sp->rate && sp->rate != r)
  69                 sp++;
  70
  71         if (!sp->rate)
  72                 return NULL;
  73
  74         return sp;
  75 }
  76
  77
  78 void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
  79 {
  80         omap2_sdrc_base = omap2_globals->sdrc;
  81         omap2_sms_base = omap2_globals->sms;
  82 }
  83
  84 /**
  85  * omap2_sdrc_init - initialize SMS, SDRC devices on boot
  86  * @sp: pointer to a null-terminated list of struct omap_sdrc_params
  87  *
  88  * Turn on smart idle modes for SDRAM scheduler and controller.
  89  * Program a known-good configuration for the SDRC to deal with buggy
  90  * bootloaders.
  91  */
  92 void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
  93 {
  94         u32 l;
  95
  96         l = sms_read_reg(SMS_SYSCONFIG);
  97         l &= ~(0x3 << 3);
  98         l |= (0x2 << 3);
  99         sms_write_reg(l, SMS_SYSCONFIG);
 100
 101         l = sdrc_read_reg(SDRC_SYSCONFIG);
 102         l &= ~(0x3 << 3);
 103         l |= (0x2 << 3);
 104         sdrc_write_reg(l, SDRC_SYSCONFIG);
 105
 106         sdrc_init_params = sp;
 107
 108         /* XXX Enable SRFRONIDLEREQ here also? */
 109         l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
 110                 (1 << SDRC_POWER_PWDENA_SHIFT) |
 111                 (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
 112         sdrc_write_reg(l, SDRC_POWER);
 113 }