arch/arm/mach-omap2/sdrc.h

   1 #ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H
   2 #define __ARCH_ARM_MACH_OMAP2_SDRC_H
   3
   4 /*
   5  * OMAP2 SDRC register definitions
   6  *
   7  * Copyright (C) 2007 Texas Instruments, Inc.
   8  * Copyright (C) 2007 Nokia Corporation
   9  *
  10  * Written by Paul Walmsley
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16 #undef DEBUG
  17
  18 #include <plat/sdrc.h>
  19
  20 #ifndef __ASSEMBLER__
  21
  22 #include <linux/io.h>
  23
  24 extern void __iomem *omap2_sdrc_base;
  25 extern void __iomem *omap2_sms_base;
  26
  27 #define OMAP_SDRC_REGADDR(reg)                  (omap2_sdrc_base + (reg))
  28 #define OMAP_SMS_REGADDR(reg)                   (omap2_sms_base + (reg))
  29
  30 /* SDRC global register get/set */
  31
  32 static inline void sdrc_write_reg(u32 val, u16 reg)
  33 {
  34         __raw_writel(val, OMAP_SDRC_REGADDR(reg));
  35 }
  36
  37 static inline u32 sdrc_read_reg(u16 reg)
  38 {
  39         return __raw_readl(OMAP_SDRC_REGADDR(reg));
  40 }
  41
  42 /* SMS global register get/set */
  43
  44 static inline void sms_write_reg(u32 val, u16 reg)
  45 {
  46         __raw_writel(val, OMAP_SMS_REGADDR(reg));
  47 }
  48
  49 static inline u32 sms_read_reg(u16 reg)
  50 {
  51         return __raw_readl(OMAP_SMS_REGADDR(reg));
  52 }
  53 #else
  54 #define OMAP242X_SDRC_REGADDR(reg)                                      \
  55                         OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
  56 #define OMAP243X_SDRC_REGADDR(reg)                                      \
  57                         OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
  58 #define OMAP34XX_SDRC_REGADDR(reg)                                      \
  59                         OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
  60 #endif  /* __ASSEMBLER__ */
  61
  62 /* Minimum frequency that the SDRC DLL can lock at */
  63 #define MIN_SDRC_DLL_LOCK_FREQ          83000000
  64
  65 /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
  66 #define SDRC_MPURATE_SCALE              8
  67
  68 /* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
  69 #define SDRC_MPURATE_BASE_SHIFT         9
  70
  71 /*
  72  * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
  73  * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
  74  */
  75 #define SDRC_MPURATE_LOOPS              96
  76
  77
  78 #endif