arch/arm/mach-omap2/sleep34xx.S

   1 /*
   2  * (C) Copyright 2007
   3  * Texas Instruments
   4  * Karthik Dasu <karthik-dp@ti.com>
   5  *
   6  * (C) Copyright 2004
   7  * Texas Instruments, <www.ti.com>
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25 #include <linux/linkage.h>
  26
  27 #include <asm/assembler.h>
  28
  29 #include "omap34xx.h"
  30 #include "iomap.h"
  31 #include "cm3xxx.h"
  32 #include "prm3xxx.h"
  33 #include "sdrc.h"
  34 #include "sram.h"
  35 #include "control.h"
  36
  37 /*
  38  * Registers access definitions
  39  */
  40 #define SDRC_SCRATCHPAD_SEM_OFFS        0xc
  41 #define SDRC_SCRATCHPAD_SEM_V   OMAP343X_SCRATCHPAD_REGADDR\
  42                                         (SDRC_SCRATCHPAD_SEM_OFFS)
  43 #define PM_PREPWSTST_CORE_P     OMAP3430_PRM_BASE + CORE_MOD +\
  44                                         OMAP3430_PM_PREPWSTST
  45 #define PM_PWSTCTRL_MPU_P       OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
  46 #define CM_IDLEST1_CORE_V       OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
  47 #define CM_IDLEST_CKGEN_V       OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
  48 #define SRAM_BASE_P             OMAP3_SRAM_PA
  49 #define CONTROL_STAT            OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS
  50 #define CONTROL_MEM_RTA_CTRL    (OMAP343X_CTRL_BASE +\
  51                                         OMAP36XX_CONTROL_MEM_RTA_CTRL)
  52
  53 /* Move this as correct place is available */
  54 #define SCRATCHPAD_MEM_OFFS     0x310
  55 #define SCRATCHPAD_BASE_P       (OMAP343X_CTRL_BASE +\
  56                                         OMAP343X_CONTROL_MEM_WKUP +\
  57                                         SCRATCHPAD_MEM_OFFS)
  58 #define SDRC_POWER_V            OMAP34XX_SDRC_REGADDR(SDRC_POWER)
  59 #define SDRC_SYSCONFIG_P        (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
  60 #define SDRC_MR_0_P             (OMAP343X_SDRC_BASE + SDRC_MR_0)
  61 #define SDRC_EMR2_0_P           (OMAP343X_SDRC_BASE + SDRC_EMR2_0)
  62 #define SDRC_MANUAL_0_P         (OMAP343X_SDRC_BASE + SDRC_MANUAL_0)
  63 #define SDRC_MR_1_P             (OMAP343X_SDRC_BASE + SDRC_MR_1)
  64 #define SDRC_EMR2_1_P           (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
  65 #define SDRC_MANUAL_1_P         (OMAP343X_SDRC_BASE + SDRC_MANUAL_1)
  66 #define SDRC_DLLA_STATUS_V      OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
  67 #define SDRC_DLLA_CTRL_V        OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
  68
  69 /*
  70  * This file needs be built unconditionally as ARM to interoperate correctly
  71  * with non-Thumb-2-capable firmware.
  72  */
  73         .arm
  74
  75 /*
  76  * API functions
  77  */
  78
  79         .text
  80 /*
  81  * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
  82  * This function sets up a flag that will allow for this toggling to take
  83  * place on 3630. Hopefully some version in the future may not need this.
  84  */
  85 ENTRY(enable_omap3630_toggle_l2_on_restore)
  86         stmfd   sp!, {lr}       @ save registers on stack
  87         /* Setup so that we will disable and enable l2 */
  88         mov     r1, #0x1
  89         adrl    r3, l2dis_3630_offset   @ may be too distant for plain adr
  90         ldr     r2, [r3]                @ value for offset
  91         str     r1, [r2, r3]            @ write to l2dis_3630
  92         ldmfd   sp!, {pc}       @ restore regs and return
  93 ENDPROC(enable_omap3630_toggle_l2_on_restore)
  94
  95 /*
  96  * Function to call rom code to save secure ram context.
  97  *
  98  * r0 = physical address of the parameters
  99  */
 100 ENTRY(save_secure_ram_context)
 101         stmfd   sp!, {r4 - r11, lr}     @ save registers on stack
 102         mov     r3, r0                  @ physical address of parameters
 103         mov     r0, #25                 @ set service ID for PPA
 104         mov     r12, r0                 @ copy secure service ID in r12
 105         mov     r1, #0                  @ set task id for ROM code in r1
 106         mov     r2, #4                  @ set some flags in r2, r6
 107         mov     r6, #0xff
 108         dsb                             @ data write barrier
 109         dmb                             @ data memory barrier
 110         smc     #1                      @ call SMI monitor (smi #1)
 111         nop
 112         nop
 113         nop
 114         nop
 115         ldmfd   sp!, {r4 - r11, pc}
 116 ENDPROC(save_secure_ram_context)
 117
 118 /*
 119  * ======================
 120  * == Idle entry point ==
 121  * ======================
 122  */
 123
 124 /*
 125  * Forces OMAP into idle state
 126  *
 127  * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
 128  * and executes the WFI instruction. Calling WFI effectively changes the
 129  * power domains states to the desired target power states.
 130  *
 131  *
 132  * Notes:
 133  * - only the minimum set of functions gets copied to internal SRAM at boot
 134  *   and after wake-up from OFF mode, cf. omap_push_sram_idle. The function
 135  *   pointers in SDRAM or SRAM are called depending on the desired low power
 136  *   target state.
 137  * - when the OMAP wakes up it continues at different execution points
 138  *   depending on the low power mode (non-OFF vs OFF modes),
 139  *   cf. 'Resume path for xxx mode' comments.
 140  */
 141         .align  3
 142 ENTRY(omap34xx_cpu_suspend)
 143         stmfd   sp!, {r4 - r11, lr}     @ save registers on stack
 144
 145         /*
 146          * r0 contains information about saving context:
 147          *   0 - No context lost
 148          *   1 - Only L1 and logic lost
 149          *   2 - Only L2 lost (Even L1 is retained we clean it along with L2)
 150          *   3 - Both L1 and L2 lost and logic lost
 151          */
 152
 153         /*
 154          * For OFF mode: save context and jump to WFI in SDRAM (omap3_do_wfi)
 155          * For non-OFF modes: jump to the WFI code in SRAM (omap3_do_wfi_sram)
 156          */
 157         ldr     r4, omap3_do_wfi_sram_addr
 158         ldr     r5, [r4]
 159         cmp     r0, #0x0                @ If no context save required,
 160         bxeq    r5                      @  jump to the WFI code in SRAM
 161
 162
 163         /* Otherwise fall through to the save context code */
 164 save_context_wfi:
 165         /*
 166          * jump out to kernel flush routine
 167          *  - reuse that code is better
 168          *  - it executes in a cached space so is faster than refetch per-block
 169          *  - should be faster and will change with kernel
 170          *  - 'might' have to copy address, load and jump to it
 171          * Flush all data from the L1 data cache before disabling
 172          * SCTLR.C bit.
 173          */
 174         ldr     r1, kernel_flush
 175         mov     lr, pc
 176         bx      r1
 177
 178         /*
 179          * Clear the SCTLR.C bit to prevent further data cache
 180          * allocation. Clearing SCTLR.C would make all the data accesses
 181          * strongly ordered and would not hit the cache.
 182          */
 183         mrc     p15, 0, r0, c1, c0, 0
 184         bic     r0, r0, #(1 << 2)       @ Disable the C bit
 185         mcr     p15, 0, r0, c1, c0, 0
 186         isb
 187
 188         /*
 189          * Invalidate L1 data cache. Even though only invalidate is
 190          * necessary exported flush API is used here. Doing clean
 191          * on already clean cache would be almost NOP.
 192          */
 193         ldr     r1, kernel_flush
 194         blx     r1
 195         b       omap3_do_wfi
 196 ENDPROC(omap34xx_cpu_suspend)
 197 omap3_do_wfi_sram_addr:
 198         .word omap3_do_wfi_sram
 199 kernel_flush:
 200         .word v7_flush_dcache_all
 201
 202 /* ===================================
 203  * == WFI instruction => Enter idle ==
 204  * ===================================
 205  */
 206
 207 /*
 208  * Do WFI instruction
 209  * Includes the resume path for non-OFF modes
 210  *
 211  * This code gets copied to internal SRAM and is accessible
 212  * from both SDRAM and SRAM:
 213  * - executed from SRAM for non-off modes (omap3_do_wfi_sram),
 214  * - executed from SDRAM for OFF mode (omap3_do_wfi).
 215  */
 216         .align  3
 217 ENTRY(omap3_do_wfi)
 218         ldr     r4, sdrc_power          @ read the SDRC_POWER register
 219         ldr     r5, [r4]                @ read the contents of SDRC_POWER
 220         orr     r5, r5, #0x40           @ enable self refresh on idle req
 221         str     r5, [r4]                @ write back to SDRC_POWER register
 222
 223         /* Data memory barrier and Data sync barrier */
 224         dsb
 225         dmb
 226
 227 /*
 228  * ===================================
 229  * == WFI instruction => Enter idle ==
 230  * ===================================
 231  */
 232         wfi                             @ wait for interrupt
 233
 234 /*
 235  * ===================================
 236  * == Resume path for non-OFF modes ==
 237  * ===================================
 238  */
 239         nop
 240         nop
 241         nop
 242         nop
 243         nop
 244         nop
 245         nop
 246         nop
 247         nop
 248         nop
 249
 250 /*
 251  * This function implements the erratum ID i581 WA:
 252  *  SDRC state restore before accessing the SDRAM
 253  *
 254  * Only used at return from non-OFF mode. For OFF
 255  * mode the ROM code configures the SDRC and
 256  * the DPLL before calling the restore code directly
 257  * from DDR.
 258  */
 259
 260 /* Make sure SDRC accesses are ok */
 261 wait_sdrc_ok:
 262
 263 /* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */
 264         ldr     r4, cm_idlest_ckgen
 265 wait_dpll3_lock:
 266         ldr     r5, [r4]
 267         tst     r5, #1
 268         beq     wait_dpll3_lock
 269
 270         ldr     r4, cm_idlest1_core
 271 wait_sdrc_ready:
 272         ldr     r5, [r4]
 273         tst     r5, #0x2
 274         bne     wait_sdrc_ready
 275         /* allow DLL powerdown upon hw idle req */
 276         ldr     r4, sdrc_power
 277         ldr     r5, [r4]
 278         bic     r5, r5, #0x40
 279         str     r5, [r4]
 280
 281 is_dll_in_lock_mode:
 282         /* Is dll in lock mode? */
 283         ldr     r4, sdrc_dlla_ctrl
 284         ldr     r5, [r4]
 285         tst     r5, #0x4
 286         bne     exit_nonoff_modes       @ Return if locked
 287         /* wait till dll locks */
 288 wait_dll_lock_timed:
 289         ldr     r4, sdrc_dlla_status
 290         /* Wait 20uS for lock */
 291         mov     r6, #8
 292 wait_dll_lock:
 293         subs    r6, r6, #0x1
 294         beq     kick_dll
 295         ldr     r5, [r4]
 296         and     r5, r5, #0x4
 297         cmp     r5, #0x4
 298         bne     wait_dll_lock
 299         b       exit_nonoff_modes       @ Return when locked
 300
 301         /* disable/reenable DLL if not locked */
 302 kick_dll:
 303         ldr     r4, sdrc_dlla_ctrl
 304         ldr     r5, [r4]
 305         mov     r6, r5
 306         bic     r6, #(1<<3)             @ disable dll
 307         str     r6, [r4]
 308         dsb
 309         orr     r6, r6, #(1<<3)         @ enable dll
 310         str     r6, [r4]
 311         dsb
 312         b       wait_dll_lock_timed
 313
 314 exit_nonoff_modes:
 315         /* Re-enable C-bit if needed */
 316         mrc     p15, 0, r0, c1, c0, 0
 317         tst     r0, #(1 << 2)           @ Check C bit enabled?
 318         orreq   r0, r0, #(1 << 2)       @ Enable the C bit if cleared
 319         mcreq   p15, 0, r0, c1, c0, 0
 320         isb
 321
 322 /*
 323  * ===================================
 324  * == Exit point from non-OFF modes ==
 325  * ===================================
 326  */
 327         ldmfd   sp!, {r4 - r11, pc}     @ restore regs and return
 328 ENDPROC(omap3_do_wfi)
 329 sdrc_power:
 330         .word   SDRC_POWER_V
 331 cm_idlest1_core:
 332         .word   CM_IDLEST1_CORE_V
 333 cm_idlest_ckgen:
 334         .word   CM_IDLEST_CKGEN_V
 335 sdrc_dlla_status:
 336         .word   SDRC_DLLA_STATUS_V
 337 sdrc_dlla_ctrl:
 338         .word   SDRC_DLLA_CTRL_V
 339 ENTRY(omap3_do_wfi_sz)
 340         .word   . - omap3_do_wfi
 341
 342
 343 /*
 344  * ==============================
 345  * == Resume path for OFF mode ==
 346  * ==============================
 347  */
 348
 349 /*
 350  * The restore_* functions are called by the ROM code
 351  *  when back from WFI in OFF mode.
 352  * Cf. the get_*restore_pointer functions.
 353  *
 354  *  restore_es3: applies to 34xx >= ES3.0
 355  *  restore_3630: applies to 36xx
 356  *  restore: common code for 3xxx
 357  *
 358  * Note: when back from CORE and MPU OFF mode we are running
 359  *  from SDRAM, without MMU, without the caches and prediction.
 360  *  Also the SRAM content has been cleared.
 361  */
 362 ENTRY(omap3_restore_es3)
 363         ldr     r5, pm_prepwstst_core_p
 364         ldr     r4, [r5]
 365         and     r4, r4, #0x3
 366         cmp     r4, #0x0        @ Check if previous power state of CORE is OFF
 367         bne     omap3_restore   @ Fall through to OMAP3 common code
 368         adr     r0, es3_sdrc_fix
 369         ldr     r1, sram_base
 370         ldr     r2, es3_sdrc_fix_sz
 371         mov     r2, r2, ror #2
 372 copy_to_sram:
 373         ldmia   r0!, {r3}       @ val = *src
 374         stmia   r1!, {r3}       @ *dst = val
 375         subs    r2, r2, #0x1    @ num_words--
 376         bne     copy_to_sram
 377         ldr     r1, sram_base
 378         blx     r1
 379         b       omap3_restore   @ Fall through to OMAP3 common code
 380 ENDPROC(omap3_restore_es3)
 381
 382 ENTRY(omap3_restore_3630)
 383         ldr     r1, pm_prepwstst_core_p
 384         ldr     r2, [r1]
 385         and     r2, r2, #0x3
 386         cmp     r2, #0x0        @ Check if previous power state of CORE is OFF
 387         bne     omap3_restore   @ Fall through to OMAP3 common code
 388         /* Disable RTA before giving control */
 389         ldr     r1, control_mem_rta
 390         mov     r2, #OMAP36XX_RTA_DISABLE
 391         str     r2, [r1]
 392 ENDPROC(omap3_restore_3630)
 393
 394         /* Fall through to common code for the remaining logic */
 395
 396 ENTRY(omap3_restore)
 397         /*
 398          * Read the pwstctrl register to check the reason for mpu reset.
 399          * This tells us what was lost.
 400          */
 401         ldr     r1, pm_pwstctrl_mpu
 402         ldr     r2, [r1]
 403         and     r2, r2, #0x3
 404         cmp     r2, #0x0        @ Check if target power state was OFF or RET
 405         bne     logic_l1_restore
 406
 407         adr     r1, l2dis_3630_offset   @ address for offset
 408         ldr     r0, [r1]                @ value for offset
 409         ldr     r0, [r1, r0]            @ value at l2dis_3630
 410         cmp     r0, #0x1        @ should we disable L2 on 3630?
 411         bne     skipl2dis
 412         mrc     p15, 0, r0, c1, c0, 1
 413         bic     r0, r0, #2      @ disable L2 cache
 414         mcr     p15, 0, r0, c1, c0, 1
 415 skipl2dis:
 416         ldr     r0, control_stat
 417         ldr     r1, [r0]
 418         and     r1, #0x700
 419         cmp     r1, #0x300
 420         beq     l2_inv_gp
 421         adr     r0, l2_inv_api_params_offset
 422         ldr     r3, [r0]
 423         add     r3, r3, r0              @ r3 points to dummy parameters
 424         mov     r0, #40                 @ set service ID for PPA
 425         mov     r12, r0                 @ copy secure Service ID in r12
 426         mov     r1, #0                  @ set task id for ROM code in r1
 427         mov     r2, #4                  @ set some flags in r2, r6
 428         mov     r6, #0xff
 429         dsb                             @ data write barrier
 430         dmb                             @ data memory barrier
 431         smc     #1                      @ call SMI monitor (smi #1)
 432         /* Write to Aux control register to set some bits */
 433         mov     r0, #42                 @ set service ID for PPA
 434         mov     r12, r0                 @ copy secure Service ID in r12
 435         mov     r1, #0                  @ set task id for ROM code in r1
 436         mov     r2, #4                  @ set some flags in r2, r6
 437         mov     r6, #0xff
 438         ldr     r4, scratchpad_base
 439         ldr     r3, [r4, #0xBC]         @ r3 points to parameters
 440         dsb                             @ data write barrier
 441         dmb                             @ data memory barrier
 442         smc     #1                      @ call SMI monitor (smi #1)
 443
 444 #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
 445         /* Restore L2 aux control register */
 446                                         @ set service ID for PPA
 447         mov     r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
 448         mov     r12, r0                 @ copy service ID in r12
 449         mov     r1, #0                  @ set task ID for ROM code in r1
 450         mov     r2, #4                  @ set some flags in r2, r6
 451         mov     r6, #0xff
 452         ldr     r4, scratchpad_base
 453         ldr     r3, [r4, #0xBC]
 454         adds    r3, r3, #8              @ r3 points to parameters
 455         dsb                             @ data write barrier
 456         dmb                             @ data memory barrier
 457         smc     #1                      @ call SMI monitor (smi #1)
 458 #endif
 459         b       logic_l1_restore
 460
 461         .align
 462 l2_inv_api_params_offset:
 463         .long   l2_inv_api_params - .
 464 l2_inv_gp:
 465         /* Execute smi to invalidate L2 cache */
 466         mov r12, #0x1                   @ set up to invalidate L2
 467         smc     #0                      @ Call SMI monitor (smieq)
 468         /* Write to Aux control register to set some bits */
 469         ldr     r4, scratchpad_base
 470         ldr     r3, [r4,#0xBC]
 471         ldr     r0, [r3,#4]
 472         mov     r12, #0x3
 473         smc     #0                      @ Call SMI monitor (smieq)
 474         ldr     r4, scratchpad_base
 475         ldr     r3, [r4,#0xBC]
 476         ldr     r0, [r3,#12]
 477         mov     r12, #0x2
 478         smc     #0                      @ Call SMI monitor (smieq)
 479 logic_l1_restore:
 480         adr     r0, l2dis_3630_offset   @ adress for offset
 481         ldr     r1, [r0]                @ value for offset
 482         ldr     r1, [r0, r1]            @ value at l2dis_3630
 483         cmp     r1, #0x1                @ Test if L2 re-enable needed on 3630
 484         bne     skipl2reen
 485         mrc     p15, 0, r1, c1, c0, 1
 486         orr     r1, r1, #2              @ re-enable L2 cache
 487         mcr     p15, 0, r1, c1, c0, 1
 488 skipl2reen:
 489
 490         /* Now branch to the common CPU resume function */
 491         b       cpu_resume
 492 ENDPROC(omap3_restore)
 493
 494         .ltorg
 495
 496 /*
 497  * Local variables
 498  */
 499 pm_prepwstst_core_p:
 500         .word   PM_PREPWSTST_CORE_P
 501 pm_pwstctrl_mpu:
 502         .word   PM_PWSTCTRL_MPU_P
 503 scratchpad_base:
 504         .word   SCRATCHPAD_BASE_P
 505 sram_base:
 506         .word   SRAM_BASE_P + 0x8000
 507 control_stat:
 508         .word   CONTROL_STAT
 509 control_mem_rta:
 510         .word   CONTROL_MEM_RTA_CTRL
 511 l2dis_3630_offset:
 512         .long   l2dis_3630 - .
 513
 514         .data
 515         .align  2
 516 l2dis_3630:
 517         .word   0
 518
 519         .data
 520         .align  2
 521 l2_inv_api_params:
 522         .word   0x1, 0x00
 523
 524 /*
 525  * Internal functions
 526  */
 527
 528 /*
 529  * This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0
 530  * Copied to and run from SRAM in order to reconfigure the SDRC parameters.
 531  */
 532         .text
 533         .align  3
 534 ENTRY(es3_sdrc_fix)
 535         ldr     r4, sdrc_syscfg         @ get config addr
 536         ldr     r5, [r4]                @ get value
 537         tst     r5, #0x100              @ is part access blocked
 538         it      eq
 539         biceq   r5, r5, #0x100          @ clear bit if set
 540         str     r5, [r4]                @ write back change
 541         ldr     r4, sdrc_mr_0           @ get config addr
 542         ldr     r5, [r4]                @ get value
 543         str     r5, [r4]                @ write back change
 544         ldr     r4, sdrc_emr2_0         @ get config addr
 545         ldr     r5, [r4]                @ get value
 546         str     r5, [r4]                @ write back change
 547         ldr     r4, sdrc_manual_0       @ get config addr
 548         mov     r5, #0x2                @ autorefresh command
 549         str     r5, [r4]                @ kick off refreshes
 550         ldr     r4, sdrc_mr_1           @ get config addr
 551         ldr     r5, [r4]                @ get value
 552         str     r5, [r4]                @ write back change
 553         ldr     r4, sdrc_emr2_1         @ get config addr
 554         ldr     r5, [r4]                @ get value
 555         str     r5, [r4]                @ write back change
 556         ldr     r4, sdrc_manual_1       @ get config addr
 557         mov     r5, #0x2                @ autorefresh command
 558         str     r5, [r4]                @ kick off refreshes
 559         bx      lr
 560
 561 /*
 562  * Local variables
 563  */
 564         .align
 565 sdrc_syscfg:
 566         .word   SDRC_SYSCONFIG_P
 567 sdrc_mr_0:
 568         .word   SDRC_MR_0_P
 569 sdrc_emr2_0:
 570         .word   SDRC_EMR2_0_P
 571 sdrc_manual_0:
 572         .word   SDRC_MANUAL_0_P
 573 sdrc_mr_1:
 574         .word   SDRC_MR_1_P
 575 sdrc_emr2_1:
 576         .word   SDRC_EMR2_1_P
 577 sdrc_manual_1:
 578         .word   SDRC_MANUAL_1_P
 579 ENDPROC(es3_sdrc_fix)
 580 ENTRY(es3_sdrc_fix_sz)
 581         .word   . - es3_sdrc_fix