arch/arm/mach-omap2/sram34xx.S

   1 /*
   2  * linux/arch/arm/mach-omap3/sram.S
   3  *
   4  * Omap3 specific functions that need to be run in internal SRAM
   5  *
   6  * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
   7  * Copyright (C) 2008 Nokia Corporation
   8  *
   9  * Rajendra Nayak <rnayak@ti.com>
  10  * Richard Woodruff <r-woodruff2@ti.com>
  11  * Paul Walmsley
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28 #include <linux/linkage.h>
  29 #include <asm/assembler.h>
  30 #include <mach/hardware.h>
  31
  32 #include <mach/io.h>
  33
  34 #include "sdrc.h"
  35 #include "cm2xxx_3xxx.h"
  36
  37 /*
  38  * This file needs be built unconditionally as ARM to interoperate correctly
  39  * with non-Thumb-2-capable firmware.
  40  */
  41         .arm
  42
  43         .text
  44
  45 /* r1 parameters */
  46 #define SDRC_NO_UNLOCK_DLL              0x0
  47 #define SDRC_UNLOCK_DLL                 0x1
  48
  49 /* SDRC_DLLA_CTRL bit settings */
  50 #define FIXEDDELAY_SHIFT                24
  51 #define FIXEDDELAY_MASK                 (0xff << FIXEDDELAY_SHIFT)
  52 #define DLLIDLE_MASK                    0x4
  53
  54 /*
  55  * SDRC_DLLA_CTRL default values: TI hardware team indicates that
  56  * FIXEDDELAY should be initialized to 0xf.  This apparently was
  57  * empirically determined during process testing, so no derivation
  58  * was provided.
  59  */
  60 #define FIXEDDELAY_DEFAULT              (0x0f << FIXEDDELAY_SHIFT)
  61
  62 /* SDRC_DLLA_STATUS bit settings */
  63 #define LOCKSTATUS_MASK                 0x4
  64
  65 /* SDRC_POWER bit settings */
  66 #define SRFRONIDLEREQ_MASK              0x40
  67
  68 /* CM_IDLEST1_CORE bit settings */
  69 #define ST_SDRC_MASK                    0x2
  70
  71 /* CM_ICLKEN1_CORE bit settings */
  72 #define EN_SDRC_MASK                    0x2
  73
  74 /* CM_CLKSEL1_PLL bit settings */
  75 #define CORE_DPLL_CLKOUT_DIV_SHIFT      0x1b
  76
  77 /*
  78  * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
  79  *
  80  * Params passed in registers:
  81  *  r0 = new M2 divider setting (only 1 and 2 supported right now)
  82  *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
  83  *      SDRC rates < 83MHz
  84  *  r2 = number of MPU cycles to wait for SDRC to stabilize after
  85  *      reprogramming the SDRC when switching to a slower MPU speed
  86  *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
  87  *
  88  * Params passed via the stack. The needed params will be copied in SRAM
  89  *  before use by the code in SRAM (SDRAM is not accessible during SDRC
  90  *  reconfiguration):
  91  *  new SDRC_RFR_CTRL_0 register contents
  92  *  new SDRC_ACTIM_CTRL_A_0 register contents
  93  *  new SDRC_ACTIM_CTRL_B_0 register contents
  94  *  new SDRC_MR_0 register value
  95  *  new SDRC_RFR_CTRL_1 register contents
  96  *  new SDRC_ACTIM_CTRL_A_1 register contents
  97  *  new SDRC_ACTIM_CTRL_B_1 register contents
  98  *  new SDRC_MR_1 register value
  99  *
 100  * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into
 101  * the SDRC CS1 registers
 102  *
 103  * NOTE: This code no longer attempts to program the SDRC AC timing and MR
 104  * registers.  This is because the code currently cannot ensure that all
 105  * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the
 106  * SDRAM when the registers are written.  If the registers are changed while
 107  * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
 108  * may enter an unpredictable state.  In the future, the intent is to
 109  * re-enable this code in cases where we can ensure that no initiators are
 110  * touching the SDRAM.  Until that time, users who know that their use case
 111  * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
 112  * option.
 113  *
 114  * Richard Woodruff notes that any changes to this code must be carefully
 115  * audited and tested to ensure that they don't cause a TLB miss while
 116  * the SDRAM is inaccessible.  Such a situation will crash the system
 117  * since it will cause the ARM MMU to attempt to walk the page tables.
 118  * These crashes may be intermittent.
 119  */
 120 ENTRY(omap3_sram_configure_core_dpll)
 121         stmfd   sp!, {r1-r12, lr}       @ store regs to stack
 122
 123                                         @ pull the extra args off the stack
 124                                         @  and store them in SRAM
 125
 126 /*
 127  * PC-relative stores are deprecated in ARMv7 and lead to undefined behaviour
 128  * in Thumb-2: use a r7 as a base instead.
 129  * Be careful not to clobber r7 when maintaing this file.
 130  */
 131  THUMB( adr     r7, omap3_sram_configure_core_dpll                      )
 132         .macro strtext Rt:req, label:req
 133  ARM(   str     \Rt, \label                                             )
 134  THUMB( str     \Rt, [r7, \label - omap3_sram_configure_core_dpll]      )
 135         .endm
 136
 137         ldr     r4, [sp, #52]
 138         strtext r4, omap_sdrc_rfr_ctrl_0_val
 139         ldr     r4, [sp, #56]
 140         strtext r4, omap_sdrc_actim_ctrl_a_0_val
 141         ldr     r4, [sp, #60]
 142         strtext r4, omap_sdrc_actim_ctrl_b_0_val
 143         ldr     r4, [sp, #64]
 144         strtext r4, omap_sdrc_mr_0_val
 145         ldr     r4, [sp, #68]
 146         strtext r4, omap_sdrc_rfr_ctrl_1_val
 147         cmp     r4, #0                  @ if SDRC_RFR_CTRL_1 is 0,
 148         beq     skip_cs1_params         @  do not use cs1 params
 149         ldr     r4, [sp, #72]
 150         strtext r4, omap_sdrc_actim_ctrl_a_1_val
 151         ldr     r4, [sp, #76]
 152         strtext r4, omap_sdrc_actim_ctrl_b_1_val
 153         ldr     r4, [sp, #80]
 154         strtext r4, omap_sdrc_mr_1_val
 155 skip_cs1_params:
 156         mrc     p15, 0, r8, c1, c0, 0   @ read ctrl register
 157         bic     r10, r8, #0x800         @ clear Z-bit, disable branch prediction
 158         mcr     p15, 0, r10, c1, c0, 0  @ write ctrl register
 159         dsb                             @ flush buffered writes to interconnect
 160         isb                             @ prevent speculative exec past here
 161         cmp     r3, #1                  @ if increasing SDRC clk rate,
 162         bleq    configure_sdrc          @ program the SDRC regs early (for RFR)
 163         cmp     r1, #SDRC_UNLOCK_DLL    @ set the intended DLL state
 164         bleq    unlock_dll
 165         blne    lock_dll
 166         bl      sdram_in_selfrefresh    @ put SDRAM in self refresh, idle SDRC
 167         bl      configure_core_dpll     @ change the DPLL3 M2 divider
 168         mov     r12, r2
 169         bl      wait_clk_stable         @ wait for SDRC to stabilize
 170         bl      enable_sdrc             @ take SDRC out of idle
 171         cmp     r1, #SDRC_UNLOCK_DLL    @ wait for DLL status to change
 172         bleq    wait_dll_unlock
 173         blne    wait_dll_lock
 174         cmp     r3, #1                  @ if increasing SDRC clk rate,
 175         beq     return_to_sdram         @ return to SDRAM code, otherwise,
 176         bl      configure_sdrc          @ reprogram SDRC regs now
 177 return_to_sdram:
 178         mcr     p15, 0, r8, c1, c0, 0   @ restore ctrl register
 179         isb                             @ prevent speculative exec past here
 180         mov     r0, #0                  @ return value
 181         ldmfd   sp!, {r1-r12, pc}       @ restore regs and return
 182 unlock_dll:
 183         ldr     r11, omap3_sdrc_dlla_ctrl
 184         ldr     r12, [r11]
 185         bic     r12, r12, #FIXEDDELAY_MASK
 186         orr     r12, r12, #FIXEDDELAY_DEFAULT
 187         orr     r12, r12, #DLLIDLE_MASK
 188         str     r12, [r11]              @ (no OCP barrier needed)
 189         bx      lr
 190 lock_dll:
 191         ldr     r11, omap3_sdrc_dlla_ctrl
 192         ldr     r12, [r11]
 193         bic     r12, r12, #DLLIDLE_MASK
 194         str     r12, [r11]              @ (no OCP barrier needed)
 195         bx      lr
 196 sdram_in_selfrefresh:
 197         ldr     r11, omap3_sdrc_power   @ read the SDRC_POWER register
 198         ldr     r12, [r11]              @ read the contents of SDRC_POWER
 199         mov     r9, r12                 @ keep a copy of SDRC_POWER bits
 200         orr     r12, r12, #SRFRONIDLEREQ_MASK   @ enable self refresh on idle
 201         str     r12, [r11]              @ write back to SDRC_POWER register
 202         ldr     r12, [r11]              @ posted-write barrier for SDRC
 203 idle_sdrc:
 204         ldr     r11, omap3_cm_iclken1_core      @ read the CM_ICLKEN1_CORE reg
 205         ldr     r12, [r11]
 206         bic     r12, r12, #EN_SDRC_MASK         @ disable iclk bit for SDRC
 207         str     r12, [r11]
 208 wait_sdrc_idle:
 209         ldr     r11, omap3_cm_idlest1_core
 210         ldr     r12, [r11]
 211         and     r12, r12, #ST_SDRC_MASK         @ check for SDRC idle
 212         cmp     r12, #ST_SDRC_MASK
 213         bne     wait_sdrc_idle
 214         bx      lr
 215 configure_core_dpll:
 216         ldr     r11, omap3_cm_clksel1_pll
 217         ldr     r12, [r11]
 218         ldr     r10, core_m2_mask_val   @ modify m2 for core dpll
 219         and     r12, r12, r10
 220         orr     r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
 221         str     r12, [r11]
 222         ldr     r12, [r11]              @ posted-write barrier for CM
 223         bx      lr
 224 wait_clk_stable:
 225         subs    r12, r12, #1
 226         bne     wait_clk_stable
 227         bx      lr
 228 enable_sdrc:
 229         ldr     r11, omap3_cm_iclken1_core
 230         ldr     r12, [r11]
 231         orr     r12, r12, #EN_SDRC_MASK         @ enable iclk bit for SDRC
 232         str     r12, [r11]
 233 wait_sdrc_idle1:
 234         ldr     r11, omap3_cm_idlest1_core
 235         ldr     r12, [r11]
 236         and     r12, r12, #ST_SDRC_MASK
 237         cmp     r12, #0
 238         bne     wait_sdrc_idle1
 239 restore_sdrc_power_val:
 240         ldr     r11, omap3_sdrc_power
 241         str     r9, [r11]               @ restore SDRC_POWER, no barrier needed
 242         bx      lr
 243 wait_dll_lock:
 244         ldr     r11, omap3_sdrc_dlla_status
 245         ldr     r12, [r11]
 246         and     r12, r12, #LOCKSTATUS_MASK
 247         cmp     r12, #LOCKSTATUS_MASK
 248         bne     wait_dll_lock
 249         bx      lr
 250 wait_dll_unlock:
 251         ldr     r11, omap3_sdrc_dlla_status
 252         ldr     r12, [r11]
 253         and     r12, r12, #LOCKSTATUS_MASK
 254         cmp     r12, #0x0
 255         bne     wait_dll_unlock
 256         bx      lr
 257 configure_sdrc:
 258         ldr     r12, omap_sdrc_rfr_ctrl_0_val   @ fetch value from SRAM
 259         ldr     r11, omap3_sdrc_rfr_ctrl_0      @ fetch addr from SRAM
 260         str     r12, [r11]                      @ store
 261 #ifdef CONFIG_OMAP3_SDRC_AC_TIMING
 262         ldr     r12, omap_sdrc_actim_ctrl_a_0_val
 263         ldr     r11, omap3_sdrc_actim_ctrl_a_0
 264         str     r12, [r11]
 265         ldr     r12, omap_sdrc_actim_ctrl_b_0_val
 266         ldr     r11, omap3_sdrc_actim_ctrl_b_0
 267         str     r12, [r11]
 268         ldr     r12, omap_sdrc_mr_0_val
 269         ldr     r11, omap3_sdrc_mr_0
 270         str     r12, [r11]
 271 #endif
 272         ldr     r12, omap_sdrc_rfr_ctrl_1_val
 273         cmp     r12, #0                 @ if SDRC_RFR_CTRL_1 is 0,
 274         beq     skip_cs1_prog           @  do not program cs1 params
 275         ldr     r11, omap3_sdrc_rfr_ctrl_1
 276         str     r12, [r11]
 277 #ifdef CONFIG_OMAP3_SDRC_AC_TIMING
 278         ldr     r12, omap_sdrc_actim_ctrl_a_1_val
 279         ldr     r11, omap3_sdrc_actim_ctrl_a_1
 280         str     r12, [r11]
 281         ldr     r12, omap_sdrc_actim_ctrl_b_1_val
 282         ldr     r11, omap3_sdrc_actim_ctrl_b_1
 283         str     r12, [r11]
 284         ldr     r12, omap_sdrc_mr_1_val
 285         ldr     r11, omap3_sdrc_mr_1
 286         str     r12, [r11]
 287 #endif
 288 skip_cs1_prog:
 289         ldr     r12, [r11]              @ posted-write barrier for SDRC
 290         bx      lr
 291
 292         .align
 293 omap3_sdrc_power:
 294         .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
 295 omap3_cm_clksel1_pll:
 296         .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
 297 omap3_cm_idlest1_core:
 298         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
 299 omap3_cm_iclken1_core:
 300         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
 301
 302 omap3_sdrc_rfr_ctrl_0:
 303         .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 304 omap3_sdrc_rfr_ctrl_1:
 305         .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
 306 omap3_sdrc_actim_ctrl_a_0:
 307         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
 308 omap3_sdrc_actim_ctrl_a_1:
 309         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
 310 omap3_sdrc_actim_ctrl_b_0:
 311         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
 312 omap3_sdrc_actim_ctrl_b_1:
 313         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
 314 omap3_sdrc_mr_0:
 315         .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
 316 omap3_sdrc_mr_1:
 317         .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
 318 omap_sdrc_rfr_ctrl_0_val:
 319         .word 0xDEADBEEF
 320 omap_sdrc_rfr_ctrl_1_val:
 321         .word 0xDEADBEEF
 322 omap_sdrc_actim_ctrl_a_0_val:
 323         .word 0xDEADBEEF
 324 omap_sdrc_actim_ctrl_a_1_val:
 325         .word 0xDEADBEEF
 326 omap_sdrc_actim_ctrl_b_0_val:
 327         .word 0xDEADBEEF
 328 omap_sdrc_actim_ctrl_b_1_val:
 329         .word 0xDEADBEEF
 330 omap_sdrc_mr_0_val:
 331         .word 0xDEADBEEF
 332 omap_sdrc_mr_1_val:
 333         .word 0xDEADBEEF
 334
 335 omap3_sdrc_dlla_status:
 336         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 337 omap3_sdrc_dlla_ctrl:
 338         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
 339 core_m2_mask_val:
 340         .word 0x07FFFFFF
 341 ENDPROC(omap3_sram_configure_core_dpll)
 342
 343 ENTRY(omap3_sram_configure_core_dpll_sz)
 344         .word   . - omap3_sram_configure_core_dpll
 345