arch/arm/mach-orion5x/common.c

   1 /*
   2  * arch/arm/mach-orion5x/common.c
   3  *
   4  * Core functions for Marvell Orion 5x SoCs
   5  *
   6  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/serial_8250.h>
  18 #include <linux/mv643xx_i2c.h>
  19 #include <linux/ata_platform.h>
  20 #include <linux/delay.h>
  21 #include <linux/clk-provider.h>
  22 #include <net/dsa.h>
  23 #include <asm/page.h>
  24 #include <asm/setup.h>
  25 #include <asm/system_misc.h>
  26 #include <asm/timex.h>
  27 #include <asm/mach/arch.h>
  28 #include <asm/mach/map.h>
  29 #include <asm/mach/time.h>
  30 #include <mach/bridge-regs.h>
  31 #include <mach/hardware.h>
  32 #include <mach/orion5x.h>
  33 #include <plat/orion_nand.h>
  34 #include <plat/ehci-orion.h>
  35 #include <plat/time.h>
  36 #include <plat/common.h>
  37 #include <plat/addr-map.h>
  38 #include "common.h"
  39
  40 /*****************************************************************************
  41  * I/O Address Mapping
  42  ****************************************************************************/
  43 static struct map_desc orion5x_io_desc[] __initdata = {
  44         {
  45                 .virtual        = ORION5X_REGS_VIRT_BASE,
  46                 .pfn            = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
  47                 .length         = ORION5X_REGS_SIZE,
  48                 .type           = MT_DEVICE,
  49         }, {
  50                 .virtual        = ORION5X_PCIE_IO_VIRT_BASE,
  51                 .pfn            = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
  52                 .length         = ORION5X_PCIE_IO_SIZE,
  53                 .type           = MT_DEVICE,
  54         }, {
  55                 .virtual        = ORION5X_PCI_IO_VIRT_BASE,
  56                 .pfn            = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
  57                 .length         = ORION5X_PCI_IO_SIZE,
  58                 .type           = MT_DEVICE,
  59         }, {
  60                 .virtual        = ORION5X_PCIE_WA_VIRT_BASE,
  61                 .pfn            = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
  62                 .length         = ORION5X_PCIE_WA_SIZE,
  63                 .type           = MT_DEVICE,
  64         },
  65 };
  66
  67 void __init orion5x_map_io(void)
  68 {
  69         iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
  70 }
  71
  72
  73 /*****************************************************************************
  74  * CLK tree
  75  ****************************************************************************/
  76 static struct clk *tclk;
  77
  78 static void __init clk_init(void)
  79 {
  80         tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
  81                                        orion5x_tclk);
  82
  83         orion_clkdev_init(tclk);
  84 }
  85
  86 /*****************************************************************************
  87  * EHCI0
  88  ****************************************************************************/
  89 void __init orion5x_ehci0_init(void)
  90 {
  91         orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
  92                         EHCI_PHY_ORION);
  93 }
  94
  95
  96 /*****************************************************************************
  97  * EHCI1
  98  ****************************************************************************/
  99 void __init orion5x_ehci1_init(void)
 100 {
 101         orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
 102 }
 103
 104
 105 /*****************************************************************************
 106  * GE00
 107  ****************************************************************************/
 108 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
 109 {
 110         orion_ge00_init(eth_data,
 111                         ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
 112                         IRQ_ORION5X_ETH_ERR);
 113 }
 114
 115
 116 /*****************************************************************************
 117  * Ethernet switch
 118  ****************************************************************************/
 119 void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
 120 {
 121         orion_ge00_switch_init(d, irq);
 122 }
 123
 124
 125 /*****************************************************************************
 126  * I2C
 127  ****************************************************************************/
 128 void __init orion5x_i2c_init(void)
 129 {
 130         orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
 131
 132 }
 133
 134
 135 /*****************************************************************************
 136  * SATA
 137  ****************************************************************************/
 138 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
 139 {
 140         orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
 141 }
 142
 143
 144 /*****************************************************************************
 145  * SPI
 146  ****************************************************************************/
 147 void __init orion5x_spi_init()
 148 {
 149         orion_spi_init(SPI_PHYS_BASE);
 150 }
 151
 152
 153 /*****************************************************************************
 154  * UART0
 155  ****************************************************************************/
 156 void __init orion5x_uart0_init(void)
 157 {
 158         orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
 159                          IRQ_ORION5X_UART0, tclk);
 160 }
 161
 162 /*****************************************************************************
 163  * UART1
 164  ****************************************************************************/
 165 void __init orion5x_uart1_init(void)
 166 {
 167         orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
 168                          IRQ_ORION5X_UART1, tclk);
 169 }
 170
 171 /*****************************************************************************
 172  * XOR engine
 173  ****************************************************************************/
 174 void __init orion5x_xor_init(void)
 175 {
 176         orion_xor0_init(ORION5X_XOR_PHYS_BASE,
 177                         ORION5X_XOR_PHYS_BASE + 0x200,
 178                         IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
 179 }
 180
 181 /*****************************************************************************
 182  * Cryptographic Engines and Security Accelerator (CESA)
 183  ****************************************************************************/
 184 static void __init orion5x_crypto_init(void)
 185 {
 186         orion5x_setup_sram_win();
 187         orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
 188                           SZ_8K, IRQ_ORION5X_CESA);
 189 }
 190
 191 /*****************************************************************************
 192  * Watchdog
 193  ****************************************************************************/
 194 void __init orion5x_wdt_init(void)
 195 {
 196         orion_wdt_init();
 197 }
 198
 199
 200 /*****************************************************************************
 201  * Time handling
 202  ****************************************************************************/
 203 void __init orion5x_init_early(void)
 204 {
 205         orion_time_set_base(TIMER_VIRT_BASE);
 206 }
 207
 208 int orion5x_tclk;
 209
 210 int __init orion5x_find_tclk(void)
 211 {
 212         u32 dev, rev;
 213
 214         orion5x_pcie_id(&dev, &rev);
 215         if (dev == MV88F6183_DEV_ID &&
 216             (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
 217                 return 133333333;
 218
 219         return 166666667;
 220 }
 221
 222 static void __init orion5x_timer_init(void)
 223 {
 224         orion5x_tclk = orion5x_find_tclk();
 225
 226         orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 227                         IRQ_ORION5X_BRIDGE, orion5x_tclk);
 228 }
 229
 230 struct sys_timer orion5x_timer = {
 231         .init = orion5x_timer_init,
 232 };
 233
 234
 235 /*****************************************************************************
 236  * General
 237  ****************************************************************************/
 238 /*
 239  * Identify device ID and rev from PCIe configuration header space '0'.
 240  */
 241 static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
 242 {
 243         orion5x_pcie_id(dev, rev);
 244
 245         if (*dev == MV88F5281_DEV_ID) {
 246                 if (*rev == MV88F5281_REV_D2) {
 247                         *dev_name = "MV88F5281-D2";
 248                 } else if (*rev == MV88F5281_REV_D1) {
 249                         *dev_name = "MV88F5281-D1";
 250                 } else if (*rev == MV88F5281_REV_D0) {
 251                         *dev_name = "MV88F5281-D0";
 252                 } else {
 253                         *dev_name = "MV88F5281-Rev-Unsupported";
 254                 }
 255         } else if (*dev == MV88F5182_DEV_ID) {
 256                 if (*rev == MV88F5182_REV_A2) {
 257                         *dev_name = "MV88F5182-A2";
 258                 } else {
 259                         *dev_name = "MV88F5182-Rev-Unsupported";
 260                 }
 261         } else if (*dev == MV88F5181_DEV_ID) {
 262                 if (*rev == MV88F5181_REV_B1) {
 263                         *dev_name = "MV88F5181-Rev-B1";
 264                 } else if (*rev == MV88F5181L_REV_A1) {
 265                         *dev_name = "MV88F5181L-Rev-A1";
 266                 } else {
 267                         *dev_name = "MV88F5181(L)-Rev-Unsupported";
 268                 }
 269         } else if (*dev == MV88F6183_DEV_ID) {
 270                 if (*rev == MV88F6183_REV_B0) {
 271                         *dev_name = "MV88F6183-Rev-B0";
 272                 } else {
 273                         *dev_name = "MV88F6183-Rev-Unsupported";
 274                 }
 275         } else {
 276                 *dev_name = "Device-Unknown";
 277         }
 278 }
 279
 280 void __init orion5x_init(void)
 281 {
 282         char *dev_name;
 283         u32 dev, rev;
 284
 285         orion5x_id(&dev, &rev, &dev_name);
 286         printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
 287
 288         /*
 289          * Setup Orion address map
 290          */
 291         orion5x_setup_cpu_mbus_bridge();
 292
 293         /* Setup root of clk tree */
 294         clk_init();
 295
 296         /*
 297          * Don't issue "Wait for Interrupt" instruction if we are
 298          * running on D0 5281 silicon.
 299          */
 300         if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
 301                 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
 302                 disable_hlt();
 303         }
 304
 305         /*
 306          * The 5082/5181l/5182/6082/6082l/6183 have crypto
 307          * while 5180n/5181/5281 don't have crypto.
 308          */
 309         if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
 310             dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
 311                 orion5x_crypto_init();
 312
 313         /*
 314          * Register watchdog driver
 315          */
 316         orion5x_wdt_init();
 317 }
 318
 319 void orion5x_restart(char mode, const char *cmd)
 320 {
 321         /*
 322          * Enable and issue soft reset
 323          */
 324         orion5x_setbits(RSTOUTn_MASK, (1 << 2));
 325         orion5x_setbits(CPU_SOFT_RESET, 1);
 326         mdelay(200);
 327         orion5x_clrbits(CPU_SOFT_RESET, 1);
 328 }
 329
 330 /*
 331  * Many orion-based systems have buggy bootloader implementations.
 332  * This is a common fixup for bogus memory tags.
 333  */
 334 void __init tag_fixup_mem32(struct tag *t, char **from,
 335                             struct meminfo *meminfo)
 336 {
 337         for (; t->hdr.size; t = tag_next(t))
 338                 if (t->hdr.tag == ATAG_MEM &&
 339                     (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
 340                      t->u.mem.start & ~PAGE_MASK)) {
 341                         printk(KERN_WARNING
 342                                "Clearing invalid memory bank %dKB@0x%08x\n",
 343                                t->u.mem.size / 1024, t->u.mem.start);
 344                         t->hdr.tag = 0;
 345                 }
 346 }