]>
git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - arch/arm/mach-pnx4008/clock.c
2 * arch/arm/mach-pnx4008/clock.c
4 * Clock control driver for PNX4008
6 * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
7 * Generic clock management functions are partially based on:
8 * linux/arch/arm/mach-omap/clock.c
10 * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/errno.h>
20 #include <linux/device.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
24 #include <asm/semaphore.h>
25 #include <asm/hardware.h>
28 #include <asm/arch/clock.h>
31 /*forward declaration*/
32 static struct clk per_ck
;
33 static struct clk hclk_ck
;
34 static struct clk ck_1MHz
;
35 static struct clk ck_13MHz
;
36 static struct clk ck_pll1
;
37 static int local_set_rate(struct clk
*clk
, u32 rate
);
39 static inline void clock_lock(void)
44 static inline void clock_unlock(void)
49 static void propagate_rate(struct clk
*clk
)
54 while (tmp_clk
->propagate_next
) {
55 tmp_clk
= tmp_clk
->propagate_next
;
56 local_set_rate(tmp_clk
, tmp_clk
->user_rate
);
60 static inline void clk_reg_disable(struct clk
*clk
)
63 __raw_writel(__raw_readl(clk
->enable_reg
) &
64 ~(1 << clk
->enable_shift
), clk
->enable_reg
);
67 static inline void clk_reg_enable(struct clk
*clk
)
70 __raw_writel(__raw_readl(clk
->enable_reg
) |
71 (1 << clk
->enable_shift
), clk
->enable_reg
);
74 static inline void clk_reg_disable1(struct clk
*clk
)
77 __raw_writel(__raw_readl(clk
->enable_reg1
) &
78 ~(1 << clk
->enable_shift1
), clk
->enable_reg1
);
81 static inline void clk_reg_enable1(struct clk
*clk
)
84 __raw_writel(__raw_readl(clk
->enable_reg1
) |
85 (1 << clk
->enable_shift1
), clk
->enable_reg1
);
88 static int clk_wait_for_pll_lock(struct clk
*clk
)
92 while (i
++ < 0xFFF && !(__raw_readl(clk
->scale_reg
) & 1)) ; /*wait for PLL to lock */
94 if (!(__raw_readl(clk
->scale_reg
) & 1)) {
96 "%s ERROR: failed to lock, scale reg data: %x\n",
97 clk
->name
, __raw_readl(clk
->scale_reg
));
103 static int switch_to_dirty_13mhz(struct clk
*clk
)
112 clk_reg_enable1(clk
);
114 tmp_reg
= __raw_readl(clk
->parent_switch_reg
);
115 /*if 13Mhz clock selected, select 13'MHz (dirty) source from OSC */
116 if (!(tmp_reg
& 1)) {
117 tmp_reg
|= (1 << 1); /* Trigger switch to 13'MHz (dirty) clock */
118 __raw_writel(tmp_reg
, clk
->parent_switch_reg
);
120 while (i
++ < 0xFFF && !(__raw_readl(clk
->parent_switch_reg
) & 1)) ; /*wait for 13'MHz selection status */
122 if (!(__raw_readl(clk
->parent_switch_reg
) & 1)) {
124 "%s ERROR: failed to select 13'MHz, parent sw reg data: %x\n",
125 clk
->name
, __raw_readl(clk
->parent_switch_reg
));
131 clk_reg_disable1(clk
);
136 static int switch_to_clean_13mhz(struct clk
*clk
)
145 clk_reg_enable1(clk
);
147 tmp_reg
= __raw_readl(clk
->parent_switch_reg
);
148 /*if 13'Mhz clock selected, select 13MHz (clean) source from OSC */
150 tmp_reg
&= ~(1 << 1); /* Trigger switch to 13MHz (clean) clock */
151 __raw_writel(tmp_reg
, clk
->parent_switch_reg
);
153 while (i
++ < 0xFFF && (__raw_readl(clk
->parent_switch_reg
) & 1)) ; /*wait for 13MHz selection status */
155 if (__raw_readl(clk
->parent_switch_reg
) & 1) {
157 "%s ERROR: failed to select 13MHz, parent sw reg data: %x\n",
158 clk
->name
, __raw_readl(clk
->parent_switch_reg
));
164 clk_reg_disable1(clk
);
169 static int set_13MHz_parent(struct clk
*clk
, struct clk
*parent
)
173 if (parent
== &ck_13MHz
)
174 ret
= switch_to_clean_13mhz(clk
);
175 else if (parent
== &ck_pll1
)
176 ret
= switch_to_dirty_13mhz(clk
);
181 #define PLL160_MIN_FCCO 156000
182 #define PLL160_MAX_FCCO 320000
185 * Calculate pll160 settings.
186 * Possible input: up to 320MHz with step of clk->parent->rate.
187 * In PNX4008 parent rate for pll160s may be either 1 or 13MHz.
188 * Ignored paths: "feedback" (bit 13 set), "div-by-N".
189 * Setting ARM PLL4 rate to 0 will put CPU into direct run mode.
190 * Setting PLL5 and PLL3 rate to 0 will disable USB and DSP clock input.
191 * Please refer to PNX4008 IC manual for details.
194 static int pll160_set_rate(struct clk
*clk
, u32 rate
)
196 u32 tmp_reg
, tmp_m
, tmp_2p
, i
;
200 parent_rate
= clk
->parent
->rate
;
205 /* set direct run for ARM or disable output for others */
206 clk_reg_disable(clk
);
208 /* disable source input as well (ignored for ARM) */
209 clk_reg_disable1(clk
);
211 tmp_reg
= __raw_readl(clk
->scale_reg
);
212 tmp_reg
&= ~0x1ffff; /*clear all settings, power down */
213 __raw_writel(tmp_reg
, clk
->scale_reg
);
215 rate
-= rate
% parent_rate
; /*round down the input */
217 if (rate
> PLL160_MAX_FCCO
)
218 rate
= PLL160_MAX_FCCO
;
226 clk_reg_enable1(clk
);
227 tmp_reg
= __raw_readl(clk
->scale_reg
);
229 if (rate
== parent_rate
) {
230 /*enter direct bypass mode */
231 tmp_reg
|= ((1 << 14) | (1 << 15));
232 __raw_writel(tmp_reg
, clk
->scale_reg
);
233 clk
->rate
= parent_rate
;
240 for (tmp_2p
= 1; tmp_2p
< 16; tmp_2p
<<= 1) {
241 if (rate
* tmp_2p
>= PLL160_MIN_FCCO
)
247 tmp_reg
|= ((i
- 1) << 11);
249 tmp_reg
|= (1 << 14); /*direct mode, no divide */
251 tmp_m
= rate
* tmp_2p
;
252 tmp_m
/= parent_rate
;
254 tmp_reg
|= (tmp_m
- 1) << 1; /*calculate M */
255 tmp_reg
|= (1 << 16); /*power up PLL */
256 __raw_writel(tmp_reg
, clk
->scale_reg
);
258 if (clk_wait_for_pll_lock(clk
) < 0) {
259 clk_reg_disable(clk
);
260 clk_reg_disable1(clk
);
262 tmp_reg
= __raw_readl(clk
->scale_reg
);
263 tmp_reg
&= ~0x1ffff; /*clear all settings, power down */
264 __raw_writel(tmp_reg
, clk
->scale_reg
);
270 clk
->rate
= (tmp_m
* parent_rate
) / tmp_2p
;
272 if (clk
->flags
& RATE_PROPAGATES
)
282 /*configure PER_CLK*/
283 static int per_clk_set_rate(struct clk
*clk
, u32 rate
)
287 tmp
= __raw_readl(clk
->scale_reg
);
289 tmp
|= ((clk
->parent
->rate
/ clk
->rate
) - 1) << 2;
290 __raw_writel(tmp
, clk
->scale_reg
);
296 static int hclk_set_rate(struct clk
*clk
, u32 rate
)
299 tmp
= __raw_readl(clk
->scale_reg
);
312 __raw_writel(tmp
, clk
->scale_reg
);
317 static u32
hclk_round_rate(struct clk
*clk
, u32 rate
)
327 static u32
per_clk_round_rate(struct clk
*clk
, u32 rate
)
329 return CLK_RATE_13MHZ
;
332 static int on_off_set_rate(struct clk
*clk
, u32 rate
)
338 clk_reg_disable(clk
);
344 static int on_off_inv_set_rate(struct clk
*clk
, u32 rate
)
347 clk_reg_disable(clk
); /*enable bit is inverted */
356 static u32
on_off_round_rate(struct clk
*clk
, u32 rate
)
358 return (rate
? 1 : 0);
361 static u32
pll4_round_rate(struct clk
*clk
, u32 rate
)
363 if (rate
> CLK_RATE_208MHZ
)
364 rate
= CLK_RATE_208MHZ
;
365 if (rate
== CLK_RATE_208MHZ
&& hclk_ck
.user_rate
== 1)
366 rate
= CLK_RATE_208MHZ
- CLK_RATE_13MHZ
;
367 return (rate
- (rate
% (hclk_ck
.user_rate
* CLK_RATE_13MHZ
)));
370 static u32
pll3_round_rate(struct clk
*clk
, u32 rate
)
372 if (rate
> CLK_RATE_208MHZ
)
373 rate
= CLK_RATE_208MHZ
;
374 return (rate
- rate
% CLK_RATE_13MHZ
);
377 static u32
pll5_round_rate(struct clk
*clk
, u32 rate
)
379 return (rate
? CLK_RATE_48MHZ
: 0);
382 static u32
ck_13MHz_round_rate(struct clk
*clk
, u32 rate
)
384 return (rate
? CLK_RATE_13MHZ
: 0);
387 static int ck_13MHz_set_rate(struct clk
*clk
, u32 rate
)
390 clk_reg_disable(clk
); /*enable bit is inverted */
392 clk
->rate
= CLK_RATE_13MHZ
;
393 ck_1MHz
.rate
= CLK_RATE_1MHZ
;
402 static int pll1_set_rate(struct clk
*clk
, u32 rate
)
404 #if 0 /* doesn't work on some boards, probably a HW BUG */
406 clk_reg_disable(clk
); /*enable bit is inverted */
407 if (!clk_wait_for_pll_lock(clk
)) {
408 clk
->rate
= CLK_RATE_13MHZ
;
424 static struct clk osc_13MHz
= {
427 .rate
= CLK_RATE_13MHZ
,
430 static struct clk ck_13MHz
= {
432 .parent
= &osc_13MHz
,
433 .flags
= NEEDS_INITIALIZATION
,
434 .round_rate
= &ck_13MHz_round_rate
,
435 .set_rate
= &ck_13MHz_set_rate
,
436 .enable_reg
= OSC13CTRL_REG
,
438 .rate
= CLK_RATE_13MHZ
,
441 static struct clk osc_32KHz
= {
444 .rate
= CLK_RATE_32KHZ
,
448 static struct clk ck_1MHz
= {
450 .flags
= FIXED_RATE
| PARENT_SET_RATE
,
454 /* PLL1 (397) - provides 13' MHz clock */
455 static struct clk ck_pll1
= {
457 .parent
= &osc_32KHz
,
458 .flags
= NEEDS_INITIALIZATION
,
459 .round_rate
= &ck_13MHz_round_rate
,
460 .set_rate
= &pll1_set_rate
,
461 .enable_reg
= PLLCTRL_REG
,
463 .scale_reg
= PLLCTRL_REG
,
464 .rate
= CLK_RATE_13MHZ
,
468 static struct clk ck_pll4
= {
471 .flags
= RATE_PROPAGATES
| NEEDS_INITIALIZATION
,
472 .propagate_next
= &per_ck
,
473 .round_rate
= &pll4_round_rate
,
474 .set_rate
= &pll160_set_rate
,
475 .rate
= CLK_RATE_208MHZ
,
476 .scale_reg
= HCLKPLLCTRL_REG
,
477 .enable_reg
= PWRCTRL_REG
,
479 .parent_switch_reg
= SYSCLKCTRL_REG
,
480 .set_parent
= &set_13MHz_parent
,
484 static struct clk ck_pll5
= {
487 .flags
= NEEDS_INITIALIZATION
,
488 .round_rate
= &pll5_round_rate
,
489 .set_rate
= &pll160_set_rate
,
490 .scale_reg
= USBCTRL_REG
,
491 .enable_reg
= USBCTRL_REG
,
493 .enable_reg1
= USBCTRL_REG
,
497 /* XPERTTeak DSP PLL */
498 static struct clk ck_pll3
= {
501 .flags
= NEEDS_INITIALIZATION
,
502 .round_rate
= &pll3_round_rate
,
503 .set_rate
= &pll160_set_rate
,
504 .scale_reg
= DSPPLLCTRL_REG
,
505 .enable_reg
= DSPCLKCTRL_REG
,
507 .enable_reg1
= DSPCLKCTRL_REG
,
509 .parent_switch_reg
= DSPCLKCTRL_REG
,
510 .set_parent
= &set_13MHz_parent
,
513 static struct clk hclk_ck
= {
516 .flags
= PARENT_SET_RATE
,
517 .set_rate
= &hclk_set_rate
,
518 .round_rate
= &hclk_round_rate
,
519 .scale_reg
= HCLKDIVCTRL_REG
,
524 static struct clk per_ck
= {
528 .propagate_next
= &hclk_ck
,
529 .set_rate
= &per_clk_set_rate
,
530 .round_rate
= &per_clk_round_rate
,
531 .scale_reg
= HCLKDIVCTRL_REG
,
532 .rate
= CLK_RATE_13MHZ
,
533 .user_rate
= CLK_RATE_13MHZ
,
536 static struct clk m2hclk_ck
= {
539 .flags
= NEEDS_INITIALIZATION
,
540 .round_rate
= &on_off_round_rate
,
541 .set_rate
= &on_off_inv_set_rate
,
544 .enable_reg
= PWRCTRL_REG
,
547 static struct clk vfp9_ck
= {
550 .flags
= NEEDS_INITIALIZATION
,
551 .round_rate
= &on_off_round_rate
,
552 .set_rate
= &on_off_set_rate
,
555 .enable_reg
= VFP9CLKCTRL_REG
,
558 static struct clk keyscan_ck
= {
559 .name
= "keyscan_ck",
560 .parent
= &osc_32KHz
,
561 .flags
= NEEDS_INITIALIZATION
,
562 .round_rate
= &on_off_round_rate
,
563 .set_rate
= &on_off_set_rate
,
565 .enable_reg
= KEYCLKCTRL_REG
,
568 static struct clk touch_ck
= {
570 .parent
= &osc_32KHz
,
571 .flags
= NEEDS_INITIALIZATION
,
572 .round_rate
= &on_off_round_rate
,
573 .set_rate
= &on_off_set_rate
,
575 .enable_reg
= TSCLKCTRL_REG
,
578 static struct clk pwm1_ck
= {
580 .parent
= &osc_32KHz
,
581 .flags
= NEEDS_INITIALIZATION
,
582 .round_rate
= &on_off_round_rate
,
583 .set_rate
= &on_off_set_rate
,
585 .enable_reg
= PWMCLKCTRL_REG
,
588 static struct clk pwm2_ck
= {
590 .parent
= &osc_32KHz
,
591 .flags
= NEEDS_INITIALIZATION
,
592 .round_rate
= &on_off_round_rate
,
593 .set_rate
= &on_off_set_rate
,
595 .enable_reg
= PWMCLKCTRL_REG
,
598 static struct clk jpeg_ck
= {
601 .flags
= NEEDS_INITIALIZATION
,
602 .round_rate
= &on_off_round_rate
,
603 .set_rate
= &on_off_set_rate
,
605 .enable_reg
= JPEGCLKCTRL_REG
,
608 static struct clk ms_ck
= {
611 .flags
= NEEDS_INITIALIZATION
,
612 .round_rate
= &on_off_round_rate
,
613 .set_rate
= &on_off_set_rate
,
615 .enable_reg
= MSCTRL_REG
,
618 static struct clk dum_ck
= {
621 .flags
= NEEDS_INITIALIZATION
,
622 .round_rate
= &on_off_round_rate
,
623 .set_rate
= &on_off_set_rate
,
625 .enable_reg
= DUMCLKCTRL_REG
,
628 static struct clk flash_ck
= {
631 .round_rate
= &on_off_round_rate
,
632 .set_rate
= &on_off_set_rate
,
633 .enable_shift
= 1, /* Only MLC clock supported */
634 .enable_reg
= FLASHCLKCTRL_REG
,
637 static struct clk i2c0_ck
= {
640 .flags
= NEEDS_INITIALIZATION
,
641 .round_rate
= &on_off_round_rate
,
642 .set_rate
= &on_off_set_rate
,
644 .enable_reg
= I2CCLKCTRL_REG
,
647 static struct clk i2c1_ck
= {
650 .flags
= NEEDS_INITIALIZATION
,
651 .round_rate
= &on_off_round_rate
,
652 .set_rate
= &on_off_set_rate
,
654 .enable_reg
= I2CCLKCTRL_REG
,
657 static struct clk i2c2_ck
= {
660 .flags
= NEEDS_INITIALIZATION
,
661 .round_rate
= &on_off_round_rate
,
662 .set_rate
= &on_off_set_rate
,
664 .enable_reg
= USB_OTG_CLKCTRL_REG
,
667 static struct clk spi0_ck
= {
670 .flags
= NEEDS_INITIALIZATION
,
671 .round_rate
= &on_off_round_rate
,
672 .set_rate
= &on_off_set_rate
,
674 .enable_reg
= SPICTRL_REG
,
677 static struct clk spi1_ck
= {
680 .flags
= NEEDS_INITIALIZATION
,
681 .round_rate
= &on_off_round_rate
,
682 .set_rate
= &on_off_set_rate
,
684 .enable_reg
= SPICTRL_REG
,
687 static struct clk dma_ck
= {
690 .round_rate
= &on_off_round_rate
,
691 .set_rate
= &on_off_set_rate
,
693 .enable_reg
= DMACLKCTRL_REG
,
696 static struct clk uart3_ck
= {
699 .flags
= NEEDS_INITIALIZATION
,
700 .round_rate
= &on_off_round_rate
,
701 .set_rate
= &on_off_set_rate
,
704 .enable_reg
= UARTCLKCTRL_REG
,
707 static struct clk uart4_ck
= {
710 .flags
= NEEDS_INITIALIZATION
,
711 .round_rate
= &on_off_round_rate
,
712 .set_rate
= &on_off_set_rate
,
714 .enable_reg
= UARTCLKCTRL_REG
,
717 static struct clk uart5_ck
= {
720 .flags
= NEEDS_INITIALIZATION
,
721 .round_rate
= &on_off_round_rate
,
722 .set_rate
= &on_off_set_rate
,
725 .enable_reg
= UARTCLKCTRL_REG
,
728 static struct clk uart6_ck
= {
731 .flags
= NEEDS_INITIALIZATION
,
732 .round_rate
= &on_off_round_rate
,
733 .set_rate
= &on_off_set_rate
,
735 .enable_reg
= UARTCLKCTRL_REG
,
738 static struct clk wdt_ck
= {
741 .flags
= NEEDS_INITIALIZATION
,
742 .round_rate
= &on_off_round_rate
,
743 .set_rate
= &on_off_set_rate
,
745 .enable_reg
= TIMCLKCTRL_REG
,
748 /* These clocks are visible outside this module
749 * and can be initialized
751 static struct clk
*onchip_clks
[] = {
781 static int local_clk_enable(struct clk
*clk
)
785 if (!(clk
->flags
& FIXED_RATE
) && !clk
->rate
&& clk
->set_rate
787 ret
= clk
->set_rate(clk
, clk
->user_rate
);
791 static void local_clk_disable(struct clk
*clk
)
793 if (!(clk
->flags
& FIXED_RATE
) && clk
->rate
&& clk
->set_rate
)
794 clk
->set_rate(clk
, 0);
797 static void local_clk_unuse(struct clk
*clk
)
799 if (clk
->usecount
> 0 && !(--clk
->usecount
)) {
800 local_clk_disable(clk
);
802 local_clk_unuse(clk
->parent
);
806 static int local_clk_use(struct clk
*clk
)
809 if (clk
->usecount
++ == 0) {
811 ret
= local_clk_use(clk
->parent
);
818 ret
= local_clk_enable(clk
);
820 if (ret
!= 0 && clk
->parent
) {
821 local_clk_unuse(clk
->parent
);
829 static int local_set_rate(struct clk
*clk
, u32 rate
)
834 if (clk
->user_rate
== clk
->rate
&& clk
->parent
->rate
) {
835 /* if clock enabled or rate not set */
836 clk
->user_rate
= clk
->round_rate(clk
, rate
);
837 ret
= clk
->set_rate(clk
, clk
->user_rate
);
839 clk
->user_rate
= clk
->round_rate(clk
, rate
);
845 int clk_set_rate(struct clk
*clk
, unsigned long rate
)
849 if (clk
->flags
& FIXED_RATE
)
853 if ((clk
->flags
& PARENT_SET_RATE
) && clk
->parent
) {
855 clk
->user_rate
= clk
->round_rate(clk
, rate
);
856 /* parent clock needs to be refreshed
857 for the setting to take effect */
859 ret
= local_set_rate(clk
, rate
);
868 EXPORT_SYMBOL(clk_set_rate
);
870 struct clk
*clk_get(struct device
*dev
, const char *id
)
872 struct clk
*clk
= ERR_PTR(-ENOENT
);
876 for (clkp
= onchip_clks
; clkp
< onchip_clks
+ ARRAY_SIZE(onchip_clks
);
878 if (strcmp(id
, (*clkp
)->name
) == 0
879 && try_module_get((*clkp
)->owner
)) {
888 EXPORT_SYMBOL(clk_get
);
890 void clk_put(struct clk
*clk
)
893 if (clk
&& !IS_ERR(clk
))
894 module_put(clk
->owner
);
897 EXPORT_SYMBOL(clk_put
);
899 unsigned long clk_get_rate(struct clk
*clk
)
907 EXPORT_SYMBOL(clk_get_rate
);
909 int clk_enable(struct clk
*clk
)
914 ret
= local_clk_use(clk
);
919 EXPORT_SYMBOL(clk_enable
);
921 void clk_disable(struct clk
*clk
)
924 local_clk_unuse(clk
);
928 EXPORT_SYMBOL(clk_disable
);
930 long clk_round_rate(struct clk
*clk
, unsigned long rate
)
935 ret
= clk
->round_rate(clk
, rate
);
942 EXPORT_SYMBOL(clk_round_rate
);
944 int clk_set_parent(struct clk
*clk
, struct clk
*parent
)
947 if (!clk
->set_parent
)
951 ret
= clk
->set_parent(clk
, parent
);
953 clk
->parent
= parent
;
960 EXPORT_SYMBOL(clk_set_parent
);
962 static int __init
clk_init(void)
966 /* Disable autoclocking, as it doesn't seem to work */
967 __raw_writel(0xff, AUTOCLK_CTRL
);
969 for (clkp
= onchip_clks
; clkp
< onchip_clks
+ ARRAY_SIZE(onchip_clks
);
971 if (((*clkp
)->flags
& NEEDS_INITIALIZATION
)
972 && ((*clkp
)->set_rate
)) {
973 (*clkp
)->user_rate
= (*clkp
)->rate
;
974 local_set_rate((*clkp
), (*clkp
)->user_rate
);
975 if ((*clkp
)->set_parent
)
976 (*clkp
)->set_parent((*clkp
), (*clkp
)->parent
);
978 pr_debug("%s: clock %s, rate %ld\n",
979 __FUNCTION__
, (*clkp
)->name
, (*clkp
)->rate
);
982 local_clk_use(&ck_pll4
);
984 /* if ck_13MHz is not used, disable it. */
985 if (ck_13MHz
.usecount
== 0)
986 local_clk_disable(&ck_13MHz
);
988 /* Disable autoclocking */
989 __raw_writeb(0xff, AUTOCLK_CTRL
);
994 arch_initcall(clk_init
);