arch/arm/mach-pxa/gpio.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/gpio.c
   3  *
   4  *  Generic PXA GPIO handling
   5  *
   6  *  Author:     Nicolas Pitre
   7  *  Created:    Jun 15, 2001
   8  *  Copyright:  MontaVista Software Inc.
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License version 2 as
  12  *  published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/irq.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/io.h>
  20
  21 #include <asm/gpio.h>
  22 #include <mach/hardware.h>
  23 #include <mach/pxa-regs.h>
  24 #include <mach/pxa2xx-gpio.h>
  25
  26 #include "generic.h"
  27
  28
  29 struct pxa_gpio_chip {
  30         struct gpio_chip chip;
  31         void __iomem     *regbase;
  32 };
  33
  34 int pxa_last_gpio;
  35
  36 /*
  37  * Configure pins for GPIO or other functions
  38  */
  39 int pxa_gpio_mode(int gpio_mode)
  40 {
  41         unsigned long flags;
  42         int gpio = gpio_mode & GPIO_MD_MASK_NR;
  43         int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
  44         int gafr;
  45
  46         if (gpio > pxa_last_gpio)
  47                 return -EINVAL;
  48
  49         local_irq_save(flags);
  50         if (gpio_mode & GPIO_DFLT_LOW)
  51                 GPCR(gpio) = GPIO_bit(gpio);
  52         else if (gpio_mode & GPIO_DFLT_HIGH)
  53                 GPSR(gpio) = GPIO_bit(gpio);
  54         if (gpio_mode & GPIO_MD_MASK_DIR)
  55                 GPDR(gpio) |= GPIO_bit(gpio);
  56         else
  57                 GPDR(gpio) &= ~GPIO_bit(gpio);
  58         gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
  59         GAFR(gpio) = gafr |  (fn  << (((gpio) & 0xf)*2));
  60         local_irq_restore(flags);
  61
  62         return 0;
  63 }
  64 EXPORT_SYMBOL(pxa_gpio_mode);
  65
  66 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  67 {
  68         unsigned long        flags;
  69         u32                  mask = 1 << offset;
  70         u32                  value;
  71         struct pxa_gpio_chip *pxa;
  72         void __iomem         *gpdr;
  73
  74         pxa = container_of(chip, struct pxa_gpio_chip, chip);
  75         gpdr = pxa->regbase + GPDR_OFFSET;
  76         local_irq_save(flags);
  77         value = __raw_readl(gpdr);
  78         value &= ~mask;
  79         __raw_writel(value, gpdr);
  80         local_irq_restore(flags);
  81
  82         return 0;
  83 }
  84
  85 static int pxa_gpio_direction_output(struct gpio_chip *chip,
  86                                         unsigned offset, int value)
  87 {
  88         unsigned long        flags;
  89         u32                  mask = 1 << offset;
  90         u32                  tmp;
  91         struct pxa_gpio_chip *pxa;
  92         void __iomem         *gpdr;
  93
  94         pxa = container_of(chip, struct pxa_gpio_chip, chip);
  95         __raw_writel(mask,
  96                         pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET));
  97         gpdr = pxa->regbase + GPDR_OFFSET;
  98         local_irq_save(flags);
  99         tmp = __raw_readl(gpdr);
 100         tmp |= mask;
 101         __raw_writel(tmp, gpdr);
 102         local_irq_restore(flags);
 103
 104         return 0;
 105 }
 106
 107 /*
 108  * Return GPIO level
 109  */
 110 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
 111 {
 112         u32                  mask = 1 << offset;
 113         struct pxa_gpio_chip *pxa;
 114
 115         pxa = container_of(chip, struct pxa_gpio_chip, chip);
 116         return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask;
 117 }
 118
 119 /*
 120  * Set output GPIO level
 121  */
 122 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 123 {
 124         u32                  mask = 1 << offset;
 125         struct pxa_gpio_chip *pxa;
 126
 127         pxa = container_of(chip, struct pxa_gpio_chip, chip);
 128
 129         if (value)
 130                 __raw_writel(mask, pxa->regbase + GPSR_OFFSET);
 131         else
 132                 __raw_writel(mask, pxa->regbase + GPCR_OFFSET);
 133 }
 134
 135 #define GPIO_CHIP(_n)                                                   \
 136         [_n] = {                                                        \
 137                 .regbase = GPIO##_n##_BASE,                             \
 138                 .chip = {                                               \
 139                         .label            = "gpio-" #_n,                \
 140                         .direction_input  = pxa_gpio_direction_input,   \
 141                         .direction_output = pxa_gpio_direction_output,  \
 142                         .get              = pxa_gpio_get,               \
 143                         .set              = pxa_gpio_set,               \
 144                         .base             = (_n) * 32,                  \
 145                         .ngpio            = 32,                         \
 146                 },                                                      \
 147         }
 148
 149 static struct pxa_gpio_chip pxa_gpio_chip[] = {
 150         GPIO_CHIP(0),
 151         GPIO_CHIP(1),
 152         GPIO_CHIP(2),
 153 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 154         GPIO_CHIP(3),
 155 #endif
 156 };
 157
 158 /*
 159  * PXA GPIO edge detection for IRQs:
 160  * IRQs are generated on Falling-Edge, Rising-Edge, or both.
 161  * Use this instead of directly setting GRER/GFER.
 162  */
 163
 164 static unsigned long GPIO_IRQ_rising_edge[4];
 165 static unsigned long GPIO_IRQ_falling_edge[4];
 166 static unsigned long GPIO_IRQ_mask[4];
 167
 168 /*
 169  * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
 170  * function of a GPIO, and GPDRx cannot be altered once configured. It
 171  * is attributed as "occupied" here (I know this terminology isn't
 172  * accurate, you are welcome to propose a better one :-)
 173  */
 174 static int __gpio_is_occupied(unsigned gpio)
 175 {
 176         if (cpu_is_pxa25x() || cpu_is_pxa27x())
 177                 return GAFR(gpio) & (0x3 << (((gpio) & 0xf) * 2));
 178         else
 179                 return 0;
 180 }
 181
 182 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
 183 {
 184         int gpio, idx;
 185
 186         gpio = IRQ_TO_GPIO(irq);
 187         idx = gpio >> 5;
 188
 189         if (type == IRQ_TYPE_PROBE) {
 190                 /* Don't mess with enabled GPIOs using preconfigured edges or
 191                  * GPIOs set to alternate function or to output during probe
 192                  */
 193                 if ((GPIO_IRQ_rising_edge[idx] |
 194                      GPIO_IRQ_falling_edge[idx] |
 195                      GPDR(gpio)) & GPIO_bit(gpio))
 196                         return 0;
 197
 198                 if (__gpio_is_occupied(gpio))
 199                         return 0;
 200
 201                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 202         }
 203
 204         GPDR(gpio) &= ~GPIO_bit(gpio);
 205
 206         if (type & IRQ_TYPE_EDGE_RISING)
 207                 __set_bit(gpio, GPIO_IRQ_rising_edge);
 208         else
 209                 __clear_bit(gpio, GPIO_IRQ_rising_edge);
 210
 211         if (type & IRQ_TYPE_EDGE_FALLING)
 212                 __set_bit(gpio, GPIO_IRQ_falling_edge);
 213         else
 214                 __clear_bit(gpio, GPIO_IRQ_falling_edge);
 215
 216         GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
 217         GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
 218
 219         pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
 220                 ((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
 221                 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
 222         return 0;
 223 }
 224
 225 /*
 226  * GPIO IRQs must be acknowledged.  This is for GPIO 0 and 1.
 227  */
 228
 229 static void pxa_ack_low_gpio(unsigned int irq)
 230 {
 231         GEDR0 = (1 << (irq - IRQ_GPIO0));
 232 }
 233
 234 static void pxa_mask_low_gpio(unsigned int irq)
 235 {
 236         ICMR &= ~(1 << (irq - PXA_IRQ(0)));
 237 }
 238
 239 static void pxa_unmask_low_gpio(unsigned int irq)
 240 {
 241         ICMR |= 1 << (irq - PXA_IRQ(0));
 242 }
 243
 244 static struct irq_chip pxa_low_gpio_chip = {
 245         .name           = "GPIO-l",
 246         .ack            = pxa_ack_low_gpio,
 247         .mask           = pxa_mask_low_gpio,
 248         .unmask         = pxa_unmask_low_gpio,
 249         .set_type       = pxa_gpio_irq_type,
 250 };
 251
 252 /*
 253  * Demux handler for GPIO>=2 edge detect interrupts
 254  */
 255
 256 #define GEDR_BITS       (sizeof(gedr) * BITS_PER_BYTE)
 257
 258 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
 259 {
 260         int loop, bit, n;
 261         unsigned long gedr[4];
 262
 263         do {
 264                 gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
 265                 gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
 266                 gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
 267                 gedr[3] = GEDR3 & GPIO_IRQ_mask[3];
 268
 269                 GEDR0 = gedr[0]; GEDR1 = gedr[1];
 270                 GEDR2 = gedr[2]; GEDR3 = gedr[3];
 271
 272                 loop = 0;
 273                 bit = find_first_bit(gedr, GEDR_BITS);
 274                 while (bit < GEDR_BITS) {
 275                         loop = 1;
 276
 277                         n = PXA_GPIO_IRQ_BASE + bit;
 278                         generic_handle_irq(n);
 279
 280                         bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
 281                 }
 282         } while (loop);
 283 }
 284
 285 static void pxa_ack_muxed_gpio(unsigned int irq)
 286 {
 287         int gpio = irq - IRQ_GPIO(2) + 2;
 288         GEDR(gpio) = GPIO_bit(gpio);
 289 }
 290
 291 static void pxa_mask_muxed_gpio(unsigned int irq)
 292 {
 293         int gpio = irq - IRQ_GPIO(2) + 2;
 294         __clear_bit(gpio, GPIO_IRQ_mask);
 295         GRER(gpio) &= ~GPIO_bit(gpio);
 296         GFER(gpio) &= ~GPIO_bit(gpio);
 297 }
 298
 299 static void pxa_unmask_muxed_gpio(unsigned int irq)
 300 {
 301         int gpio = irq - IRQ_GPIO(2) + 2;
 302         int idx = gpio >> 5;
 303         __set_bit(gpio, GPIO_IRQ_mask);
 304         GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
 305         GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
 306 }
 307
 308 static struct irq_chip pxa_muxed_gpio_chip = {
 309         .name           = "GPIO",
 310         .ack            = pxa_ack_muxed_gpio,
 311         .mask           = pxa_mask_muxed_gpio,
 312         .unmask         = pxa_unmask_muxed_gpio,
 313         .set_type       = pxa_gpio_irq_type,
 314 };
 315
 316 void __init pxa_init_gpio(int gpio_nr, set_wake_t fn)
 317 {
 318         int irq, i, gpio;
 319
 320         pxa_last_gpio = gpio_nr - 1;
 321
 322         /* clear all GPIO edge detects */
 323         for (i = 0; i < gpio_nr; i += 32) {
 324                 GFER(i) = 0;
 325                 GRER(i) = 0;
 326                 GEDR(i) = GEDR(i);
 327         }
 328
 329         /* GPIO 0 and 1 must have their mask bit always set */
 330         GPIO_IRQ_mask[0] = 3;
 331
 332         for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
 333                 set_irq_chip(irq, &pxa_low_gpio_chip);
 334                 set_irq_handler(irq, handle_edge_irq);
 335                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 336         }
 337
 338         for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
 339                 set_irq_chip(irq, &pxa_muxed_gpio_chip);
 340                 set_irq_handler(irq, handle_edge_irq);
 341                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 342         }
 343
 344         /* Install handler for GPIO>=2 edge detect interrupts */
 345         set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
 346
 347         pxa_low_gpio_chip.set_wake = fn;
 348         pxa_muxed_gpio_chip.set_wake = fn;
 349
 350         /* add a GPIO chip for each register bank.
 351          * the last PXA25x register only contains 21 GPIOs
 352          */
 353         for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) {
 354                 if (gpio + 32 > gpio_nr)
 355                         pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio;
 356                 gpiochip_add(&pxa_gpio_chip[i].chip);
 357         }
 358 }
 359
 360 #ifdef CONFIG_PM
 361
 362 static unsigned long saved_gplr[4];
 363 static unsigned long saved_gpdr[4];
 364 static unsigned long saved_grer[4];
 365 static unsigned long saved_gfer[4];
 366
 367 static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
 368 {
 369         int i, gpio;
 370
 371         for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
 372                 saved_gplr[i] = GPLR(gpio);
 373                 saved_gpdr[i] = GPDR(gpio);
 374                 saved_grer[i] = GRER(gpio);
 375                 saved_gfer[i] = GFER(gpio);
 376
 377                 /* Clear GPIO transition detect bits */
 378                 GEDR(gpio) = GEDR(gpio);
 379         }
 380         return 0;
 381 }
 382
 383 static int pxa_gpio_resume(struct sys_device *dev)
 384 {
 385         int i, gpio;
 386
 387         for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
 388                 /* restore level with set/clear */
 389                 GPSR(gpio) = saved_gplr[i];
 390                 GPCR(gpio) = ~saved_gplr[i];
 391
 392                 GRER(gpio) = saved_grer[i];
 393                 GFER(gpio) = saved_gfer[i];
 394                 GPDR(gpio) = saved_gpdr[i];
 395         }
 396         return 0;
 397 }
 398 #else
 399 #define pxa_gpio_suspend        NULL
 400 #define pxa_gpio_resume         NULL
 401 #endif
 402
 403 struct sysdev_class pxa_gpio_sysclass = {
 404         .name           = "gpio",
 405         .suspend        = pxa_gpio_suspend,
 406         .resume         = pxa_gpio_resume,
 407 };
 408
 409 static int __init pxa_gpio_init(void)
 410 {
 411         return sysdev_class_register(&pxa_gpio_sysclass);
 412 }
 413
 414 core_initcall(pxa_gpio_init);